Analog & Digital VLSI Design

Dr. Vilas H Gaidhane

BITS Pilani
Dubai Campus
VLSI Design

VLSI
Design

Analog and Digital VLSI Design 1

 Course Objectives
1. To understand the need and importance of digital VLSI design

2. To understand the DC behavior of static CMOS circuits, VTC

3. To understand the design and behavior of basic sequential circuits

4. To analyze the clock generation technique using feedback

5. To study various low power design techniques and effect of

interconnect parasitics

6. To design the CMOS based circuits at the sub system level, using
different topologies for adders and multipliers.

7. To study and design the basic cells of semiconductor memory using

low power design techniques.

8. To understand the basics of VLSI testability and fault tolerant design

Analog and Digital VLSI Design 2

 Course Objectives

Text Book

1. Digital Integrated Circuits, A Design

Perspective, Jan M Rabaey, Anantha
Chandrakasan, Borivoje Nikolic, 2nd edition,
Prentice Hall, 2005.

Analog and Digital VLSI Design 3

 Course Objectives

1. Essentials of VLSI Circuits and Systems, Kamran Eshraghian, Douglas A Pucknell, Sholeh
Eshraghian, Prentice Hall India, 2009.
2. CMOS VLSI Design, A Circuits and Systems Perspective, 4th edition, Neil H E Weste, David
Money Harris, Pearson
3. CMOS Logic Circuit Design, Uyemura, John P., Springer, 1999, ISBN: 9780792384526
4. Principles of CMOS VLSI Design, A Systems Perspective, Neil H Weste, Kamran
Eshraghian, second edition, Pearson Education India, 2010

Analog and Digital VLSI Design 4

 A brief History
• Integration Levels:

Era Year Logic blocks /Chip

• Single Transistor 1958 <1
• One gate 1960 1
• SSI 1964 5 - 20 gates
• MSI 1967 20-200 gates
• LSI 1972 200-2000 gates
• VLSI 1978 2000-20000 gates
• ULSI 1989 >20000 gates

Analog and Digital VLSI Design 8

 A brief History
• The digital electronics
computing started with Vacuum
tubes

• ENIAC the first computer (80

feet long several feet wide)
with 18000 vacuum tubes

• Vacuum tubes ruled in first half

of 20th century Large,
expensive, power-hungry,
unreliable

Analog and Digital VLSI Design 9

 A brief History
• First Transistor John Bardeen and Walter Brattain at Bell lab in 1947

• BJT by Schokley in 1949

Analog and Digital VLSI Design 10

 A brief History
• 1958: First integrated
circuit

• Flip-flop using two

transistors

• Built by Jack Kilby at

Texas Instruments

(Win the Nobel Prize for his work)

Analog and Digital VLSI Design 11

 A brief History
➢ 1962 Transistor- Transistor logic was invented (Beeson).

➢ 1970’s processes usually had only nMOS transistors. Inexpensive, but

consume power while idle

➢ 1980s- onwards: CMOS processes for low idle power

Intel386TM DX
Processor
Intel486TM DX
Processor

Pentium® Processor

Pentium® Pro &

Pentium® II Processors

Analog and Digital VLSI Design 12

 Moore’s Law
➢ Gordon Moore: co-founder of Intel
➢ Predicted that the number of transistors per chip would grow
exponentially (double every 18 months) (1960)

Gordon Earle Moore is an American

businessman, co-founder and Chairman
Emeritus of Intel Corporation, and the
author of Moore's law. As of January
2015, his net worth is $6.7 billion.

January 3, 1929 (age 86), San

Francisco, California, United States

Analog and Digital VLSI Design 13

 Moore’s Law
➢ Twice the number of transistors, approximately every two years (2000)
1 Billion
K Transistors
1,000,000

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected

Analog and Digital VLSI Design 14

 Moore’s Law
Frequency

10000 Not true

Doubles every
2 years
any more!
1000
Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286
8080
1 Microprocessors frequency doubles every 2 years
Lead
8008
4004
0.1
1970 1980 1990 2000 2010
Year

Analog and Digital VLSI Design 15

 VLSI Design Methodologies
➢ The growth in complexity has been sustained by constant advances in
manufacturing technologies.

➢ It has created challenges in many areas like development of

technology, CAD tools, chip design, fabrication, packaging, testing and
reliability qualification.

➢ Design complexity of the of the logic chips increases exponentially

with the number of transistors to be integrated. This is translated in
the design cycle time, which is the time from start of chip
development until the mask-tape delivery time.

➢ The design cycles time devoted to achieving the desired level of the
chip performance at an acceptable cost.

Analog and Digital VLSI Design 16

 VLSI Design Methodologies
➢ The level of circuit performance strongly depend on the efficiency of
the design methodologies as well as on the design style.

➢ Full custom design (geometry & placement of every transistor

optimized individually) requires a longer time. Final product has high
level of performance but the larger cost.

➢ semi-custom design (standard cell based design or FPGA) required

the shorter time. It may have higher performance than full custom
but offers less opportunity for performance improvement.

➢ Performance of the final product will be less than full custom design

Analog and Digital VLSI Design 17

VLSI Design Methodologies

Analog and Digital VLSI Design 18

 VLSI Design Flow
➢ The Y-chart introduced by D. Gajski illustrate a simplified design flow
for using three axes activities.

➢ It consist of:

1. behavioral domain

2. structural domain

3. geometric layout domain

Analog and Digital VLSI Design 19

Simplified VLSI Design Flow

System
Specifications

Functional Design Circuit Design

Functional Circuit Verification

Verification

Physical Design
Logic Design

Layout verification
Logic Verification

Analog and Digital VLSI Design 20

 VLSI Design Style
➢ The chose of the particular design style for a VLSI product depends
on:

i) performance requirement ii) Technology being used

iii) expected lifetime iv) cost of the project

➢ Several design styles can be considered for chip implementation

➢ Proper choice has to be made by designer in order to provide the

specific functionality at low cost and within less time.

• FPGA,

• Gate Array Design,

• Standard cell-based design

• Full Custom Design

Analog and Digital VLSI Design 21

 VLSI Design Style
➢ Field programmable gate array (FPGA)

• Logic gates with programmable interconnects

• I/O buffers, configurable logic blocks (CLBs) and programmable

interconnect structures

• For fast prototyping and small-volume ASIC production (short turn-

around time)

➢ Design flow of FPGA:

• Behavioral description of its functionality

• Technology-mapped into circuits or logic cells

• Assigns logic cells to FPGA CLBs and determines the routing pattern

Analog and Digital VLSI Design 22

 VLSI Design Style

Figure: General Architecture of Xilinx FPGAs

Analog and Digital VLSI Design 23

 VLSI Design Style
➢ Configurable logic blocks (CLBs)

• Independent combinational function generators

• Clock signal terminal

• User-programmable multiplexers

• Flip flops

➢ Programmable interconnect

• Six pass transistors per switch matrix interconnect point

• Accomplished by data in RAM

Analog and Digital VLSI Design 24

 VLSI Design Style
➢ Gate Array Design

• Uncommitted transistors separated by routing channels

• Circuit implementation:

1st phase: generic masks for uncommitted transistors on each

GA chip (stored)

2nd phase: Customization by (multiple) metal fabrication process

• Ranks second after FPGA with a turn-around time of a few days

• Chip utilization factor is higher than that of the FPGA

Analog and Digital VLSI Design 25

 VLSI Design Style

Figure: Basic Processing steps required for gate array

Analog and Digital VLSI Design 26

 VLSI Design Style
➢ Standard cell based Design

Commonly used logics are developed, characterized and stored in a

standard cell library

• Cell library includes:

• Circuit simulation model

• Timing simulation model

• Fault simulation model

• Cell data for place-and-route

• Mask data

Analog and Digital VLSI Design 27

 VLSI Design Style
➢ Standard cell based Design

➢ Standard cell arrangement:

• Fixed cell height

• Parallel power and ground rails

• Input and output pins are located on the upper and lower boundaries

• Cells are placed side by side in standard-cell based design

• The required logic circuits are realized using the cells in the library

• Complete mask sets are developed for chip fabrication

• One of the most prevalent design style for ASIC applications

Analog and Digital VLSI Design 28

VLSI Design Style

Analog and Digital VLSI Design 29

 VLSI Design Style
➢ Full Custom Design

• Design and develop the IC from scratch

• Possibly to achieve the highest

performance compared with other
design styles

• Highest development cost and design

cycle time

• Design reuse is coming popular

• Suitable for design of high-performance

processors, FPGAs and memory chips

Analog and Digital VLSI Design 30

 VLSI Design Quality
➢ It is desirable to measure the quality of design in order to improve the
chip design. Accepted metric to decide the quality of design are:

1. Testability

2. Yield and Manufacturability

3. Reliability

4. Updatability

Analog and Digital VLSI Design 31

 VLSI Design Quality
1. Testability

➢ Time and effort for chip test increase exponentially with design
complexity.

➢ The fabricated chip should be fully testable to ensure the proper

functioning without causing failure. Such a goal requires

• Generation of good test vectors

• Availability of reliable test fixture at speed

• Design of testable chip

Analog and Digital VLSI Design 32

 VLSI Design Quality
2. Yield and Manufacturability
➢ Yield is the ratio of good tested chips to total tested chips.
Classified into two categories, Functionality and Parametric yield
Functionality yield:
• Testing the chips at lower speed
• Identify problems of shorts, opens and leakage current
• Detect logic and circuit design failure

Parametric yield
• Test at the required speed
• Delay testing is performed at this stage
• Consider manufacturability of the chip in the design phase
• Sufficient tolerance to device fluctuations and margin for
measurement uncertainty

Analog and Digital VLSI Design 33

 VLSI Design Quality
3. Reliability

Reliability is depends on the design and process conditions

➢ Major chip reliability problems:

• Electrostatic discharge (ESD) and electrical overstress (EOS)

• Electro migration

• Latch-up in CMOS I/O and internal circuits

• Hot-carrier induced aging

• Oxide breakdown

• Power and ground bouncing

• On-chip noise and crosstalk

Analog and Digital VLSI Design 34

 VLSI Design Quality
4. Updatability

• Be technology-updated to new design rules

• Fast migration to new process technology

• “Dumb shrink” method with uniform scaling is rarely practiced

• Silicon compilation: generate physical layout from high-level

specifications

Analog and Digital VLSI Design 35

Issues in Digital IC Design
SYSTEM
Design abstraction Levels

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

Analog and Digital VLSI Design 36

 Issues in Digital IC Design
➢ Change in technology in every two years requires a redesign of
library

➢ Library based approach is works fine when speed, power are not
stringent.

➢ The interconnection wire contribute to delay as they introduce

parasitics like resistance, capacitance and inductance and going to
be increase in the years due to the scaling in size.

➢ Increasing the size of digital circuits, connected more cells to supply

causes a voltage drop over the wires and slow down the all the
connected cells.

➢ Clock distribution is an another issue

Analog and Digital VLSI Design 37

 Issues in Digital IC Design
➢ New design issues and constraints tend to over time

➢ Deviation from the expected output may caused due to the

variations in fabrication process parameters or inductance of the
package or badly modeled clock.

➢ Expertise is required for troubleshooting

Analog and Digital VLSI Design 38

 Introduction
A Switch! An MOS Transistor
VGS  V T |VGS|

Ron
S D

Analog and Digital VLSI Design 39

 Introduction
Metal Oxide semiconductor (MOS) Transistor
D D

G G

S S

NMOS Enhancement NMOS Depletion

D D

G G B

S S

PMOS Enhancement NMOS with

Bulk Contact

Analog and Digital VLSI Design 41

 MOS Structure
➢Now consider behavior under external bias voltage. Assume VB =0
and gate voltage VG as controlling parameter.
➢Based on the polarity and magnitude of the gate voltage three
different operating regions can be observed:

1. Accumulation
2. Depletion
3. Inversion

Analog and Digital VLSI Design 41

 MOS Structure
➢Now consider behavior under external bias voltage. Assume VB =0
and gate voltage VG as controlling parameter.
➢Based on the polarity and magnitude of the gate voltage three
different operating regions can be observed:

1. Accumulation
2. Depletion
3. Inversion

Analog and Digital VLSI Design 41

 I-V Characteristics
Gradual Channel Approximation method for calculation of Current

V ( y ) : 0 → Vds as y : 0 → L

Analog and Digital VLSI Design 41

 MOSFET I-V Characteristics
Current-Voltage Equation for n-MOS Current-Voltage Equation for p-MOS
Cut-off Region: VGS  VT 0 Cut-off Region: VGS  VT 0
ID = 0 ID = 0

Trode Region: VGS  VT 0 and VDS  VGS − VT 0 Trode Region: VGS  VT 0 and VDS  VGS − VT 0
 C W  nCOX  W 
I D = n OX    2 (VGS − VT 0 )VDS − VDS 2  ID =    2 (VGS − VT 0 )VDS − VDS 
2

2 L 2 L

Saturation Region: VGS  VT 0 and VDS  VGS − VT 0 Saturation Region: VGS  VT 0 and VDS  VGS − VT 0
nCOX  W  nCOX  W 
ID =   (VGS − VT 0 )  (VGS − VT 0 )
2
ID =
2

2 L 2 L

Analog and Digital VLSI Design 58

 MOSFET I-V Characteristics

ID saturation
triode
VDS ≥ VG s – VTO
increasing
VGS
VDS<VGS-VTO

VDS
Cut-off VGS<VTO
0.1 v
Analog and Digital VLSI Design 59
 MOSFET I-V Characteristics
➢Actual length of the inverted channel gradually decreases as the
potential between the drain and Source increases.
➢The channel pinch-off point moves slightly away from drain as VDS >
VDSsat
➢The effective channel length (Leff) reduces with VDS.
➢Electrons travel to pinch-off point will be swept to drain by electric field.
➢The length accounted for conductance in the channel is replaced by Leff
. This effect is called as channel length modulation.
Leff = L − L
−1
1 1  L  1
= = 1 −
Leff  L   L  L
L 1 −
 L 
1  L  1
 1 +
Leff  L  L

Analog and Digital VLSI Design 60

 MOSFET I-V Characteristics

➢Then the saturation current

1 n Cox W
I Dsat = (VGS − VT 0 )
2

 L  2 L
1 − L 
 
 L  L
 1 +   1 +  VDS As = VDS
 L  L
C W
I Dsat = n ox (VGS − VTO )2 (1 +  VDS )
2 L
Here, λ is the empirical model
parameter and called as channel
length modulation coefficient.

Analog and Digital VLSI Design 61