VLSI Design

( 3151105 )
Prepared by :
Jayesh Diwan
EC Department
VGEC
 CHAPTER 1

INTRODUCTION TO VLSI DESIGN

 Introduction
 The use of integrated circuits in high-performance computing, telecommunications, and
consumer electronics has been growing at a very fast pace

 Typically, the required computational and information processing power of these applications
is the driving force for the fast development of this field.

 The current leading-edge technologies already provide the end-users a certain amount of
processing power and portability. This trend is expected to continue.
 Driving forces for system integration are:

 Increasing need for very high processing power and bandwidth

 tend to become more personalized

 more intelligent

 also be portable to allow more mobility

 As more and more complex functions are required in various data processing and
telecommunications devices, the need to integrate these functions in a small package is also
increasing. The level of integration is measured by no. of logic gates per chip.
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Moore’s Law
 By Gordon Moore, Intel’s co-founder

Transistors on a die
doubles every 1 to 2 years

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Moore’s law in Microprocessors
Transistors on Lead Microprocessors double every 2 years
1000

100
2X growth in 1.96 years!
Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

5
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VLSI Design triangle

POWER

SPEED AREA
 Overview of VLSI Design Methodology
 The structural (design) complexity of digital integrated circuits is expressed by the number of
transistors (no. of logic gates) per chip.

 The design complexity has been increasing at an exponential rate over the last thirty years.

 This phenomenal growth rate has been sustained primarily by the constant advances in
manufacturing technology, as well as by the increasing need for integrating more complex
functions on a chip.

 This rapidly rising chip complexity has created significant challenges in many areas;

 Hundreds of team members are involved in the development of a VLSI product,

 Includes the development technology, Computer-Aided Design (CAD) tools

 chip design, fabrication, packaging, testing and reliability qualification.

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 The design complexity of logic chips increases almost exponentially with the number of
transistors to be integrated. This increases the design cycle time

 Design Cycle Time: the time period from the start of chip development until the mask-tape
delivery time.

 The majority of this design cycle time is typically devoted to achieving the desired level of
chip performance at an acceptable cost.

 During the design cycle, the circuit performance can be increased by design improvements;
more rapidly in the beginning, then more gradually until the performance finally saturates for
the particular design style and technology being used.

 The level of performance which can be reached within a certain design time strongly depends
on the efficiency of the design methodologies, as well as on the design style.

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 There are two VLSI design methodologies:

1. Full Custom design style where the geometry and the placement of every transistor can be
optimized individually

2. Semi Custom design style which is a standard-cell based design or FPGA

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 Full Custom design style:

 requires a longer time until design maturity can be reached

 It has inherent flexibility of adjusting almost every aspect of circuit design which allows
far more opportunity for circuit performance improvement

 The final product typically has a high level of performance (e.g., high processing speed,
low power dissipation) and the silicon area is relatively small because of better area
utilization. But this comes at a larger cost in terms of design time.

 Semi Custom design style:

 allows a shorter design time until design maturity can be achieved

 some of the components used in semi-custom design are already optimized, so In the early
design phase, the circuit performance can be even higher than that of a full- custom design.

 But the semi-custom design style offers less opportunity for performance improvement,
and the overall performance of the final product will inevitably be less than that of a full-
custom design.
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 The choice of the particular design style for a VLSI product depends on:

 the performance requirements

 the technology being used

 the expected lifetime of the product and

 the cost of the project

 In addition to VLSI design style, we must consider the constantly evolving nature of
manufacturing technology.

 Approximately every two years, a new generation of technology is introduced, which

typically allows for smaller device dimensions and consequently higher integration density
and higher performance

 In order to make the best use of the current technology, the chip development time has to be
short enough to allow the maturing of chip manufacturing and timely delivery of the product
to customers.

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 Design cycle time is kept shorter than what would be necessary for developing an optimum
performance chip, thus leaving enough time for the production and marketing of the chip
during the current generation.

 When the next generation of manufacturing technology arrives, the design can be updated to
take advantage of higher integration density and better performance.
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 Simplified VLSI Design Flow
 This VLSI design flow takes into account the
various representations, or abstractions of
design: behavioral, logic, circuit and mask
layout.
 Note that the verification of design plays a very
important role in every step during this process. The
failure to properly verify a design in its early phases
typically causes significant and expensive re-design
at a later stage, which ultimately increases the time-
to-market.

 This flow is described in linear fashion but

actually There are many iterations, especially
between any two neighboring steps, and
occasionally even remotely separated pairs.

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 VLSI Design Flow
 The design process, at various levels, is usually evolutionary in nature.

 It starts with a given set of requirements. Initial design is developed and tested against the
requirements. When requirements are not met, the design has to be improved. if such
improvement is either not possible or too costly, then a revision of requirements and an
impact analysis must be considered.

 The Y-chart (first introduced by D. Gajski) illustrates a simplified design flow for most logic
chips, using design activities on three different axes (domains) which resemble the letter "Y."
In reality, there exist many feedback loops that are not shown for simplicity.

 The Y-chart consists of three domains of representation, namely (i) behavioral domain, (ii)
structural domain, and (iii) geometrical layout domain.

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Y Chart Prepared By : Jayesh Diwan
 Y Chart:

 The design flow starts from the algorithm that describes the behavior of the target chip.

 The corresponding architecture of the processor is first defined.

 It is mapped onto the chip surface by floor-planning.

 The next design evolution in the behavioral domain defines finite state machines (FSMs)
which are structurally implemented with functional modules such as registers and
arithmetic logic units (ALUs).

 These modules are then geometrically placed onto the chip surface using CAD tools for
automatic module placement followed by routing, with a goal of minimizing the
interconnects’ area and signal delays.

 The third evolution starts with a behavioral module description.

 Individual modules are then implemented with leaf cells. At this stage the chip is described
in terms of logic gates (leaf cells), which can be placed and interconnected by using a cell
placement and routing program.

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  The last evolution involves a detailed Boolean description of leaf cells followed by a
transistor level implementation of leaf cells and mask generation.

 In the standard-cell based design style, leaf cells are pre-designed (at the transistor level) and
stored in a library for logic implementation, effectively eliminating the need for the transistor
level design.

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 Design Hierarchy
 Some of the classical techniques for reducing the complexity of IC design are: Hierarchy,
regularity, modularity and locality.

 The use of the hierarchy, or "divide and conquer" technique involves dividing a module into
sub-modules and then repeating this operation on the sub-modules until the complexity of the
smaller parts becomes manageable.

 A hierarchy structure can be described in three domains separately, namely (i) behavioral
domain, (ii) structural domain, and (iii) geometrical layout domain.. However, it is important
for the simplicity of design that the hierarchies in different domains be mapped into each
other easily.

 The example of structural hierarchy is explained using 4-bit adder.

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 Figure shows the structural decomposition of a CMOS 4-bit adder into its components.

 The adder can be decomposed progressively into 1-bit adders, separate carry and sum
circuits, and finally into individual logic gates.

 At this lower level of hierarchy, the design of a simple circuit realizing a well-defined
Boolean function is much easier to handle than at the higher levels of hierarchy.

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 In the physical domain, partitioning a complex system into its various functional blocks will
provide a valuable guide for the actual realization of these blocks on the chip.

 The approximate shape and size of each sub-module should be estimated in order to provide a
useful floor-plan.
 The figure shows the
hierarchical decomposition of
the four-bit adder in
geometrical layout domain,
resulting in a simple floor-plan.

 This physical view describes

the external geometry of the
adder, I/O pin locations and the
pin locations that allow some signals (here the carry signals) to be transferred from
one sub- block to the other without external routing.
 At lower levels of hierarchy, the internal mask layout of each adder defines the locations and the
connections of each transistor and wire.
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 Regularity, Modularity and Locality
 The hierarchical design approach reduces the design complexity by dividing the large system
into several sub-modules.

 Regularity means that the hierarchical decomposition of a large system should result in not
only simple, but also similar blocks, as much as possible.

 A good example of regularity is the design of array structures consisting of identical cells-
such as a parallel multiplication array.

 Regularity can exist at all levels of abstraction. For example, at the transistor level,
uniformly sized transistors simplify the design and at the logic level, identical gate
structures can be used.

2-1 MUX

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 D-Flip Flop
 If the designer has a small library of well-characterized basic building blocks, a number of
different functions can be constructed by using this principle.

 Regularity usually reduces the number of different modules that need to be designed and
verified, at all levels of abstraction.

 Modularity means that the various functional blocks which make up the larger system must
have well-defined functions and interfaces.

 Modularity allows that each block or module can be designed relatively independently
from each other, since there is no ambiguity about the function and the signal interface of
these blocks.
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  All of the blocks can be combined with ease at the end of the design process, to form the
large system.

 The concept of modularity enables the parallelization of the design process.

 The well-defined functionality and signal interface also allow the use of generic modules in
various designs.

 Locality ensures that connections are mostly between neighboring modules, avoiding long-
distance connections as much as possible.

 This is extremely important for avoiding long interconnect delays.

 Time-critical operations should be performed locally, without the need to access distant
modules or signals.

 Sometimes, the repli­cation of some logic in distant location for local use may solve this
problem in large system architectures.

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
VLSI Design Styles
Several design styles can be considered for chip implementation of specified algorithms or
logic functions such as;

 Field Programmable Gate Array(FPGA)

 Gate Array Design

 Standard Cells Based Design

 Full Custom Design

 Each design style has its own merits and shortcomings, and thus a proper choice has to be
made by designers to provide the specified functionality at low cost and in a timely manner.

 Field Programmable Gate Array (FPGA)

 FPGA chips are available for custom hardware programming to realize desired functionality.
 FPGA chips contain tens to hundreds of thousands, or even more, of logic gates with programmable
interconnects.

 This design style provides a means for fast prototyping and also for cost-effective chip design, especially
for low-volume applications.
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 A typical FPGA chip consists of I/O buffers, an array of Configurable Logic Blocks (CLBs),
and programmable interconnect structures.

 The programming of the interconnects is accomplished by programming of RAM cells whose

output terminals are connected to the gates of MOS pass transistors.

 Thus, the signal routing between the CLBs and the I/O blocks is accomplished by setting the
configurable switch matrices accordingly.

General Architecture of FPGAs

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Detailed View of switch matrices and interconnection routing between CLBs

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 Simplified block diagram of a CLB (XC4000 family from Xilinx)
 Each CLB contains:
 two independent 4-input combinational function generators,
 a clock signal terminal,
 user-programmable multiplexers and two flip-flops.

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 The function generators, which are capable of realizing any arbitrarily defined Boolean
function of their four inputs, are implemented as memory look-up tables.

 A third function generator can implement any Boolean function of its three inputs: F', G' and
a third input from outside the CLB.

 Thus, the CLB offers significant flexibility of implementing a wide range of functions, with
up to nine input variables.

 The user-programmable multiplexers within the CLB control the internal signal routing, and
therefore, the functionality of the block.

 The complexity of a FPGA chip is typically determined by the number of CLBs it contains.
 In Xilinx XC4000 family of FPGAs,

 Size of the CLB array can range from 8 x 8 (64 CLBs) to 32 x 32 (1024 CLBs),

 Approximate gate count of 25,000,

 Larger FPGA chips with an equivalent gate count of about 200,000 are also available.

 FPGA chips can support system clock frequencies up to hundreds of MHz.

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 Typical Design Flow
 Design flow of an FPGA chip starts with the behavioral description of its functionality, using
a hardware description language such as VHDL.
 The synthesized architecture is then technology-mapped (or partitioned) into circuits or logic
cells. At this stage, the chip design is completely described in terms of available logic cells.
 Next, the placement and routing step assigns individual logic cells to FPGA sites (CLBs) and
determines the routing patterns among the cells in accordance with the netlist.
 After routing is completed, the on-chip performance of the design can be simulated and
verified before downloading the design for programming of the FPGA chip.
 The programming of the chip remains valid as long as the chip is powered-on, or until it is re-
programmed.

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 Advantages:
 The largest advantage of FPGA-based design is the very short turn-around time, i.e., the
time required from the start of the design process until a functional chip is available.
 Since no physical manufacturing step is necessary for customizing the FPGA chip, a
functional sample can be obtained almost as soon as the design is mapped into a specific
technology.
 The typical price of FPGA chips is usually higher than other alternatives (such as gate
array or standard cells) of the same design, but for small-volume production of ASIC chips
and for fast prototyping, FPGA offers a very valuable option.

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  Gate Array Design
 The gate array (GA) ranks second after the FPGA in terms of fast prototyping capability.
 Gate array implementation requires a two-step manufacturing process:
 The first phase, which is based on generic (standard) masks, results in an array of
uncommitted transistors on each GA chip.
 These uncommitted chips can be stored for later customization, which is completed by
defining the metal interconnects between the transistors of the array.
 Since the patterning of metallic interconnects is done at the end of the chip fabrication
process, the turn-around time can still be short, a few days to a few weeks.

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 A corner of a gate array chip contains bonding pads, diodes for I/O protection, nMOS and
pMOS transistors for chip output driver circuits adjacent to bonding pads, arrays of nMOS
and pMOS transistors, under­pass wire segments, and power and ground buses along with
contact windows.

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 Typical gate array platforms allow dedicated areas, called channels, for inter-cell routing
between rows or columns of MOS transistors. They simplify the interconnections.
 Interconnection patterns that perform basic logic gates can be stored in a library, which can
then be used to customize rows of uncommitted transistors according to the netlist.
 In most of the modern GAs, multiple metal layers are used for channel routing.
 With the use of multiple interconnect layers, the routing can also be achieved over the active
cell areas: thus, the routing channels can be removed as in Sea-of-Gates (SOG) chips. Here,
the entire chip surface is covered with uncommitted nMOS and pMOS transistors.
 As in the gate array case, neighboring transistors can be customized using a metal mask to
form basic logic gates.
 For intercell routing, however, some of the uncommitted transistors must be sacrificed. This
approach results in more flexibility for interconnections and usually in a higher density.
 GA chip utilization factor is measured by the used chip area divided by the total chip area. It
is higher than that of the FPGA and so is the chip speed.

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 Comparison between the Channeled (GA) V/s the Channelless (SOG) designs

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 Standard Cell Based Design
 The standard cells based design require development of a full custom mask set.
 The standard cell is also called the polycell.
 In this design style, all of the commonly used logic cells are developed, characterized and
stored in a standard cell library.
 A typical library may contain a few hundred cells including inverters, NAND gates, NOR
gates. complex AOI, OAI gates, D-latches and Flip-flops.
 Each gate type can be implemented in several versions to provide adequate driving capability
for different fan-outs.
 Each cell is characterized according to several different characterization categories, such as,
 Delay time versus load capacitance
 Circuit simulation model
 Timing simulation model
 Fault simulation model
 Cell data for place-and-route
 Mask data

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 To enable automated placement of the cells and routing, each cell layout is designed with a
fixed height, so that a number of cells can be abutted side-by-side to form rows.
 The power and ground rails typically run parallel to the upper and lower boundaries of the
cell. thus, neighboring cells share a common power bus and a common ground bus.
 The input and output pins are located on the upper and lower boundaries of the cell.
 nMOS are located closer to the ground rail while pMOS are placed closer to the power rail.
 The signal delay. noise margins, and power I/O
Cells

consumption of each cell should be also

optimized with proper sizing of transistors
using circuit simulation.

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 Full Custom Design
 In a full-custom design, the entire mask design is done anew without use of any library.
 The development cost of such a design style is becoming high. Thus, the concept of design
reuse is becoming popular in order to reduce design cycle time and development cost.
 For logic chip design, a good compromise can be achieved by using a combination of
different design styles on the same chip, such as standard cells, data-path cells, and
programmable logic arrays (PLAs).
 In real full custom layout in which the geometry, orientation, and placement of every
transistor is done individually by the designer, design productivity is usually very low—
typically a few tens of transistors per day, per designer.
 In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost.

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Full Custom Design
 Huge design effort
 High Design Costs
 High Performance
 Typically used for high-volume
applications

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 Design Approaches
Top down Approach:
· Start with functionality and move to layout.
· Top-down design adds functional detail.
· Create lower levels of abstraction from upper levels.

Bottom up Approach:
· When chip area, speed or power is constrained.
· Feed forward low level information to higher level and remove or modify some function.
· Bottom-up design creates abstractions from low-level behavior

Mixed Approach
· Good design needs both top-down and bottom-up efforts.

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Major Design Consideration

PD2C2S
1. Power
2. Delay
3. Design Time
4. Complexity
5. Cost
6. Size
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General Design Considerations
 Production volume  Intellectual Property
 Component Price  Tools investment/purchase
 Inventory / Bill of Materials  Market cost trends
 Production costs  Technology and performance
 Through life costs  Design for test
 Size/miniaturization  Package types
 Power consumption  Quality and Reliability
 Complexity  Vendor service
 Flexibility  Security
 Migration path  Risk
 Time to volume production
 Training costs
 Tools and documentation available

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 Design Quality
 It is desirable to measure the quality of design in order to improve the chip design.
 The following criteria are considered to be important:
 Testability
 Yield and manufacturability
 Reliability
 Technology updateability
 Testability
 Developed chips are eventually inserted into PCBs or multichip modules for system
applications.
 The correct functionality of the system reflects the correct functionality of the chips used.
Therefore, fabricated chips should be fully testable to ensure that all the chips passing the
specified chip test can be inserted into the system, either in packaged or in bare die form,
without causing failures.
 Such a goal requires:
 Generation of good test vectors
 Availability of reliable test fixture at speed
 Design of testable chip
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 In fact, some chip projects had to be abandoned after chip fabrication because of inadequate
testability of the design.
 As the complexity of the chips increases, additional circuitry for self testing has to be
included to ensure that the fabricated chips can be fully tested. This translates into an increase
in chip area and some speed penalty, but such a trade-off will become unavoidable in VLSI
design.
 Yield and Manufacturability
 The definition of the yield can be the number of good tested chips divided by the total
number of chip sites available at the start of the wafer processing.
 Since some wafers may be scrapped in the process line due to mishandling or for other
reasons, such a metric may not reflect the design quality.
 Also, poor design of the wafer array for chips may cause some chips to fail routinely due to
un­controllable process variations and handling problems.
 Poor chip design can cause processing problems and, therefore, drop-outs during the processing. In such
a case, the first yield metric will overestimate the design quality.
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 The chip yield can be further divided into the following subcategories:
 Functional yield
 Parametric yield
 The functional yield is obtained by testing the functionality of the chip at a speed usually
lower than the required chip speed. The functional test weeds out the problems of shorts,
opens, and leakage current, and can detect logic and circuit design faults.
 The parametric yield is usually performed at the required speed on chips that passed the
functional test. All the delay testing is performed at this stage.
 Poor design that failed to consider uncontrollable process variations which cause significant
variations in chip performance may cause poor parametric yield.
 In order to achieve high chip yield, chip designers should consider manufacturability of the
chip by considering realistic fluctuations in device parameters that cause performance
fluctuations, and also some margin for measurement uncertainty.

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 Reliability
 The reliability of the chip depends on the design and process conditions.
 The major causes for chip reliability problems can be characterized into the following:
 Electrostatic discharge (ESD) and electrical overstress (EOS)
 Electro migration
 Latch-up in CMOS I/O and internal circuits
 Hot-carrier induced aging
 Oxide breakdown
 Single event upset
 Power and ground bouncing
 On-chip noise and crosstalk

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 Technology Updateability
 Process technology development has progressed rapidly.
 The time pressure to develop increasingly more complex chips in a shorter time is constantly
increasing.
 Under such circumstances, the chip products often have to be technology-updated to new
design rules.
 Even without any change in the chip's functionality, the task of updating the mask to new
design rules is very formidable.
 The so-called "dumb shrink" method whereby mask dimensions are scaled uniformly.
 Thus, the design style should be chosen such that the technology update of the chip or
functional modules for design reuse can be achieved quickly with minimal cost.
 Designers can develop and use advanced CAD tools that can automatically generate the
physical layout, the so-called silicon compilation, which meets the timing requirements with
proper gate sizing or transistor sizing.

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 Package Technology
• Pin-through-hole (PTH).
• Surface- mounted technology (SMT).

Dual In-line Packages (DIP) :

• This PTH package has been the most dominant IC package type for more than
20 years.
• advantage :
- low cost
• Disadvantage:
- high interconnect inductances, which can lead to significant noise problems in
high-frequency applications.
- The maximum pin count of DIP is typically limited to 64.
Pin Grid Array (PGA) Packages
• This PTH package type offers a higher pin count (typically several hundreds)
and higher thermal conductivity (hence, better power dissipation characteristics)
compared to DIP
• PGA packages require a large PCB area, and the package cost is higher than
DIP,
• More recently, Ball Grid Array (BGA) packages have been introduced to
reduce parasitics for high performance chips.
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 Package Technology
 Chip Carrier Packages (CCP)
- This SMT package type is available in two varia­tions. the leadless chip carrier
and the leaded chip carrier
- The leadless chip carrier is designed to be mounted directly on the PCB. and it
can support a high pin count.
- The main drawback is the inherent difference in thermal coefficients between
the chip carrier and the PCB, which can eventually
cause mechanical stresses to occur on the surface of the PCB.
- The leaded chip carrier package solves this problem since the added leads can
accommodate small dimension variations caused by the differences in thermal
coefficients.
 Quad Flat Packs (QFP)
- This SMT package type is similar to leaded chip carrier packages, except that the
leads extend outward rather than being bent under the pack­age body.
- Ceramic and plastic QFPs with very high pin counts (up to 500) are be­coming
popular package types in recent years.

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Package Technology

 Multi-Chip Modules (MM)

- This IC package option can be used for special ap­plications requiring very high
performance, where multiple chips are assembled on a common substrate
contained in a single package. -
- Thus, a large number of critical interconnections between the chips can be made
within the package.
- Advantages in­clude significant savings of overall system size,
reduced package lead counts, and faster operation since chips can be placed in
very close proximity.

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CCP - Leadless

CCP - Leaded

MCM
BGA

PGA

SMD

DIP
CAD Tools
The CAD technology for VLSI chip design
can he categorized into the following areas
 High level synthesis
 Logic synthesis
 Circuit optimization
 Layout
 Simulation
 Design rules checking
 Formal verification
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Synthesis Tools
 The high-level synthesis tools using hardware description languages
(HDL, such as VHDL or Veri log, address the automation of the
design phase in the top level of the design hierarchy.

Layout Tools
 The tools for circuit optimization are concerned with transistor sizing
for mininimization of delays and with process variations, noise, and
reliability hazards.
 The layout CAD tools include floorplanning, place-and-route. and
module generation. Sophisti­cated layout tools are goal driven and
include some degree of optimization functions.

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Simulation and Verification Tools
 The simulation category, which is the most mature area of VLSI CAD,
includes many tools ranging from circuit-level simulation (SPICE or its
derivatives. such as HSPICE), timing level simulation, logic level simulation.
and behavioral simulation.
 Many other simulation tools have also been developed for device-level
simulation and process simulation for technology development.
 The aim of all simulation CAD tools is to determine if the designed circuit
meets the required specifications, at all stages of the design process.

DRC Tools
 The design rules checking CAD category includes the tools for layout rules
checking, electrical rules checking. and reliability rules checking.
 The layout rules checking program has been highly effective in weeding out
potential yield prob­lems and circuit malfunctions.

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