Low Power Design Methodology and Design Flow

Adopted From LOW POWER DESIGN

ESSENTIALS - JAN M. RABAEY

Low-Power Design Methodology - Motivations

Minimize power
Reduce power in various modes of device operation
Dynamic power, leakage power, or total power

Minimize time
Reduce power quickly
Complete the design in as little time as possible

Prevent downstream issues caused by LPD techniques

Avoid complicating timing and functional verification

Minimize effort
Reduce power efficiently
Complete the design with as few resources as possible

Prevent downstream issues caused by LPD techniques

Avoid complicating timing and functional verification

Methodology Issues
Power Characterization and Modeling
How to generate macro-model power data?
Model accuracy

Power Analysis
When to analyze?
Which modes to analyze?
How to use the data?

Power Reduction
Logical modes of operation
For which modes should power be reduced?

Dynamic power versus leakage power

Physical design implications
Functional and timing verification
Return on Investment
How much power is reduced for the extra effort? Extra logic? Extra area?

Power Integrity
Peak instantaneous power
Electromigration
Impact on timing

Some Methodology Reflections

Generate required models to support chosen methodology
Analyze power early and often
Employ (only) as many LPD techniques as needed to
reach the power spec
Some techniques are used at only 1 abstraction level; others are
used at several
Clock Gating: multiple levels
Timing slack redistribution: only physical level

Methodology particulars dependent upon choice of

techniques
Power gating versus Clock gating
Very different methodologies

No free lunch
Most LPD techniques complicate the design flow
Methodology must avoid or mitigate the complications

Power Characterization and Modeling

Objective: Build models to support low power
design methodology
Power consumption models
Current waveform models
Voltage-sensitive timing models

Issues
Model formats, structures, and complexity
Example: Liberty-power

Run times
Accuracy
[Ref: Liberty]

Power Characterization and Modeling

Process
Model

Vdd

Spice
Netlists

Library
Params

Power Characterization
(using a circuit or power simulator)

IL
Isc
Ileakage

Model
Templates

CL

Characterization
Database
(raw power data)

Power Modeler

Power
Models

[Ref: J. Frenkil, Kluwer02]

Generalized Low-Power Design Flow

Design Phase
System-Level Design

RTL Design

Implementation

Low Power Design Activities

Explore architectures and algorithms for power efficiency
Map functions to sw and/or hw blocks for power efficiency
Choose voltages and frequencies
Evaluate power consumption for different operational
modes
Generate budgets for power, performance, area
Generate RTL to match system-level model
Select IP blocks
Analyze and optimize power at module level and chip level
Analyze power implications of test features
Check power against budget for various modes

Synthesize RTL to gates using power optimizations

Floorplan, place and route design
Optimize dynamic and leakage power
Verify power budgets and power delivery

Power-Analysis Methodology
Motivation
Determine if the design will meet the power spec ASAP
Identify opportunities for power reduction, if needed

Method
Set up regular, automatic power analysis runs (nightly, weekly)
Run regular power analysis regressions as soon as a simulation
environment is ready
Initially can re-use functional verification tests
Add targeted mode- and module-specific tests to increase coverage

Compare analysis results against design spec

Check against spec for different operational modes

Compare analysis results against previous analysis results

Identify power mistakes - changes / fixes resulting in increased power

Identify opportunities for power reduction

Power Analysis Methodology Issues

Development phases
System
Description available early in the design cycle
Least accurate but fastest turn times

Design
Most common design representation
Easy to identify power savings opportunities
Power results can be associated with specific lines of code

Implementation
Gate level design available late in the design cycle
Slowest turn times (due to lengthy gate level simulations) but most
accurate results
Difficult to interpret results for identifying power saving opportunities
cant see the forest for the trees

Availability of data
When are simulation traces available?
When is parasitic data available?

System-Phase Analysis Methodology

ESL
stimulus

IP sim
models

ESL Simulation

ESL
Code

IP power
models

Env.
Data

Tech.
Data

ESL Synthesis

RTL
Code
Trans.
traces

RTL Power Analysis

Power
Reports

Design-Phase Analysis Methodology

mode 1
mode 2
RTL
mode n
Stimulus
RTL
Stimulus
RTL
Stimulus

RTL
Design

IP power
models

Env.
Data

Tech.
Data

RTL Simulation

mode 1
mode 2
Activity
mode n
Data
Activity
Data
Activity
Data

RTL Power Analysis

Power
Power
Reports
Reports
Power
Reports

Implementation-Phase Analysis

mode 1
mode 2
RTL
mode n
Stimulus
RTL
Stimulus
RTL
Stimulus

RTL Simulation

mode 1
mode 2
Activity
mode n
Data
Activity
Data
Activity
Data

IP power
models

RTL
Design

Env.
Data

Tech.
Data

RTL Synthesis

gate
netlist

Gate level
Power Analysis

Power
Power
Reports
Reports
Power
Reports

Power Analysis Over Project Duration

Weekly power regression results

[Courtesy: Tensilica, Inc.]

System-Phase Low Power Design

Primary objectives: minimize feff and VDD
Modes
Modes enable power to track workload
Software programmable; set / controlled by OS
Hardware component needed to facilitate control
Software timers and protocols needed to determine when to change
modes and how long to stay in a mode

Parallelism and Pipelining

VDD can be reduced, since equivalent throughput can be achieved
with slower speeds

Challenges
Evaluating different alternatives

Power Down Modes - Example

Modes control clock frequency, VDD, or both
Active mode: maximum power consumption
Full clock frequency at max VDD

Doze mode: ~10X power reduction from active mode

Core clock stopped

Nap mode: ~ 50% power reduction from doze mode

VDD reduced, PLL & bus snooping stopped

Sleep mode: ~10X power reduction from nap mode

All clocks stopped, core VDD shut-off

Issues and Tradeoffs

Determining appropriate modes and appropriate controls
Trading-off power reduction to wake-up time

[Ref: S. Gary, D&T94]

Parallelism and Pipelining - Example

Concept: maintain performance with reduced VDD
Total area increases but each datapath works less in each cycle
VDD can be reduced such that the work requires the full cycle time
Cycle time remains the same, but with reduced VDD

Pipelining a datapath
Power can be reduced by 50% or more
Modest area overhead due to additional registers

Paralleling a datapath
Power can be reduced by 50% or more
Significant area overhead due to paralleled logic

Multiple CPU cores

Enables multi-threaded performance gains with a constrained VDD

Issues and Tradeoffs

Application: can it be paralleled or threaded?
Area: what is the area increase for the power reduction?
Latency: how much can be tolerated?
[Ref: A. Chandrakasan, JSSC92]

System-Phase Low-Power Design Flow

Create design in C / C++

Simulate C / C++ under typical

work loads

Create / synthesize different

versions

Evaluate power of each version

Transmitter
Design
(IFFT Block)

Area
(mm2)

Symbol
Latency
(cycles)

Min. Freq to
Achieve Req.
Rate
Avg. Power

Avg. Power
(mW)

Combinational

4.91

10

1.0 MHz

3.99

Pipelined

5.25

12

1.0 MHz

4.92

Folded (16 Bfly4s)

3.97

12

1.0 MHz

7.27

Folded (8 Bfly4s)

3.69

15

1.5 MHz

10.9

Folded (4 Bfly4s)

2.45

21

12

3.0 MHz

14.4

Folded (2 Bfly4s)

1.84

33

24

6.0 MHz

21.1

Folded (1 Bfly4)

1.52

57

48

12.0 MHz

34.6

Example: Exploration of IFFT block for 802.11a

transmitter using BlueSpec SystemVerilog
[Ref: N. Dave, Memocode06]

Choose lowest power version

Throughput
(cycle/symbol
)

Design-Phase Low Power Design

Primary objective: minimize feff
Clock gating
Reduces / inhibits unnecessary clocking
Registers need not be clocked if data input hasnt changed

Data gating
Prevents nets from toggling when results wont be used
Reduces wasted operations

Memory system design

Reduces the activity internal to a memory
Cost (power) of each access is minimized

Clock Gating
Power is reduced by two mechanisms
Clock net toggles less frequently, reducing feff
Registers internal clock buffering switches less often

din
en

en
clk

dout

enF

FSM

enE

Execution
Unit

qn
clk

clk

din

q
qn
clk

Local Gating

dout
enM
clk

Memory
Control

Global Gating

Clock Gating Insertion

Local clock gating: 3 methods
Logic synthesizer finds and implements local
gating opportunities
RTL code explicitly specifies clock gating
Clock gating cell explicitly instantiated in RTL

Global clock gating: 2 methods

RTL code explicitly specifies clock gating
Clock gating cell explicitly instantiated in RTL

Clock Gating Verilog Code

Conventional RTL Code
//always clock the register
always @ (posedge clk) begin
if (enable) q = din;
end

// form the flip-flop

Low Power Clock Gated RTL Code

//only clock the register when enable is true
assign gclk = enable && clk;
// gate the clock
always @ (posedge gclk) begin // form the flip-flop
q = din;
end

Instantiated Clock Gating Cell

//instantiate a clock gating cell from the target library
clkgx1 i1 .en(enable), .cp(clk), .gclk_out(gclk);
always @ (posedge gclk) begin
// form the flip-flop
q = din;
end

Clock Gating: Glitch Free Verilog

Add a Latch to Prevent Clock Glitching
L1

enable

en_out

LATCH
gn

clk

G1

gclk

Clock Gating Code with Glitch Prevention Latch

always @ (enable or clk) begin
if !clk then en_out = enable // build latch
end
assign gclk = en_out && clk;
// gate the clock

Data Gating
Objective
Reduce wasted operations => reduce feff

Example
Multiplier whose inputs change
every cycle, whose output
conditionally feeds an ALU

Low Power Version

Inputs are prevented from
rippling through multiplier
if multiplier output is not
selected

Data Gating Insertion

Two insertion methods
Logic synthesizer finds and implements data
gating opportunities
RTL code explicitly specifies data gating
Some opportunities cannot be found by synthesizers

Issues
Extra logic in data path slows timing
Additional area due to gating cells

Data Gating Verilog Code: Operand Isolation

Conventional Code
assign muxout = sel ? A : A*B ;

// build mux

muxout
A
sel

Low Power Code

assign multinA = sel & A ; // build and gate
assign multinB = sel & B ; // build and gate
assign muxout = sel ? A : multinA*multinB ;

B
X

A
sel

muxout

Memory System Design

Primary objectives: minimize feff and Ceff
Reduce number of accesses or (power) cost of
an access

Power Reduction Methods

Memory banking / splitting
Minimization of number of memory accesses

Challenges and Tradeoffs

Dependency upon access patterns
Placement and routing

Split Memory Access

din

16K x 32
RAM
dout

addr

32

write
15

pre_addr

noe

addr[14:0]
addr[14:1]

dout

clock
32

addr[0]

Implementation Phase Low Power Design

Primary objective: minimize power consumed by individual instances
Low power synthesis
Dynamic power reduction via local clock gating insertion, pin-swapping

Slack redistribution
Reduces dynamic and/or leakage power

Power gating
Largest reductions in leakage power

Multiple supply voltages

The implementation of earlier choices

Power integrity design

Ensures adequate and reliable power delivery to logic

Slack Redistribution
Objective
Reduce dynamic power or leakage power
or both by trading-off positive timing slack
Physical level optimization
Best optimized post-route
Must be noise aware

Post-optimized

Dynamic power reduction by cell resizing

Cells along non-speed critical path resized
Usually downsized, sometimes upsized

Power reduction of 10% to 15%

Leakage power reduction by VTH

assignment
Cells along non-speed critical path set to High
VTH

Leakage reduction of 20% to 60%

Dynamic & leakage power can be

optimized independently or together
[Ref: Q. Wang, TCAD02]

Pre-optimized

Dynamic Power Optimization: Cell Resizing

Positive Slack Trade-off for Reduced Dynamic Power
Objective: reduce dynamic power where speed is not needed
Optimization performed post-route for optimum results
Cells along paths with positive slack replaced with lower drive cells
Switching currents, input capacitances, and area are all reduced
Incremental re-route required new cells may have different
footprints from the previous cells
2x

1x
2x
2x

2x
2x

2x

1x

2x
2x

High speed, high power

2x

2x
2x

2x

2x
2x

Reduced speed, lower power

Leakage Power Optimization: Multi-VTH

Trade-off Positive Slack for Reduced Leakage Power
Objective: reduce leakage power where speed is not needed
Optimization performed post-route for optimum results
Cells along paths with positive slack replaced with High-V TH cells
Leakage currents reduced where timing margins permits
Re-route not required new cells have same footprint as
previous cells
L

H
L
L

L
L

L
L

High speed, high leakage

L
L

L
L

Reduced speed, low leakage

Slack Redistribution Flows

Fix Timing

Place & Route

Place & Route

Check Timing

Check Timing

Fix Timing

OK
y

Check Noise

Fix Noise

OK
y

OR

Check Noise
Fix Noise
(timing aware)

OK

OK

Check Pwr

Reduce Pwr

OK
y

Check Pwr
Reduce Power
(timing and
noise aware)

OK
y

Slack Redistribution: Trade-offs and Issues

Yield
Slack redistribution effectively turns non-critical paths into critical
or semi-critical paths
Increased sensitivity to process variation and speed faults

Libraries
Cell resizing needs a fine granularity of drive strengths for best
optimization results => more cells in the library
Multi-VTH requires an additional library for each additional VTH

Iterative loops
Timing and noise must be re-verified after each optimization
Both optimizations increase noise and glitch sensitivities

Done late in the design process

Difficult to predict in advance how much power will be saved
Very dependent upon design characteristics

Power Gating
Objective
Reduce leakage currents by inserting a switch transistor (usually
high VTH) into the logic stack (usually low VTH)
Switch transistors change the bias points (VSB) of the logic transistors

Most effective for systems with standby operational modes

1 to 3 orders of magnitude leakage reduction possible
But switches add many complications
Vdd
Logic
Cell

Vdd

Logic
Cell
Virtual
Ground
sleep

Switch
Cell

Power-Gating Physical Design

Switch placement
In each cell?
Very large area overhead, but placement and routing is easy

Grid of switches?
Area efficient, but a third global rail must be routed

Ring of switches?
Useful for hard layout blocks, but area overhead can be significant
Global Supply
Virtual Grounds

Module

Switch Integrated
Within Each Cell

Switch-in-cell

Switch
Cells

Switch Cell

Grid of Switches
[Ref: S. Kosonocky, ISLPED01]

Virtual
Supply

Ring of Switches

Power Gating Switch Sizing

Tradeoff between area, performance, leakage
Larger switches => less voltage drop, larger leakage, more area
Smaller switches => larger voltage drop, less leakage, less area

Switch
Cell
Area
(2)
ILKG
tD
Vvg_max (mV)
Lvg_max ()

[Ref: J. Frenkil, Springer07]

Power Gating: Additional Issues

Library design: special cells are needed
Switches, isolation cells, state retention flip-flops (SRFFs)

Headers or Footers?
Headers better for gate leakage reduction, but ~ 2X larger

Which modules, and how many, to power gate?

Sleep control signal must be available, or must be created

State retention: which registers must retain state?

Large area overhead for using SRFFs

Floating signal prevention

Power-gate outputs that drive always-on blocks must not float

Rush currents and wakeup time

Rush currents must settle quickly and not disrupt circuit operation

Delay effects and timing verification

Switches affect source voltages which affect delays

Power-up & power-down sequencing

Controller must be designed and sequencing verified

Power Gating Flow

Design power gating
library cells

Determine floorplan

Determine which blocks

to power gate

Power gating aware

placement

Determine state
retention mechanism

Clock tree synthesis

Determine rush current

control scheme

Route

Design power gating

controller

Power gating aware

synthesis

Verify virtual rail

electrical
characteristics

Verify timing

Multi-VDD
Objective
Reduce dynamic power by reducing the VDD2 term
Higher supply voltage used for speed-critical logic
Lower supply voltage used for non speed-critical logic

Example
Memory VDD = 1.2 V
Logic VDD = 1.0 V
Logic dynamic power
savings = 30%

Multi-VDD Issues
Partitioning
Which blocks and modules should use with voltages?
Physical and logical hierarchies should match as much as possible

Voltages
Voltages should be as low as possible to minimize CVDD2f
Voltages must be high enough to meet timing specs

Level shifters
Needed (generally) to buffer signals crossing islands
May be omitted if voltage differences are small, ~ 100mV

Added delays must be considered

Physical design
Multiple VDD rails must be considered during floorplanning

Timing verification
Signoff timing verification must be performed for all corner cases across
voltage islands.
For example, for 2 voltage islands Vhi, Vlo
Number of timing verification corners doubles

Multi-VDD Flow
Determine which blocks
run at which Vdd
Multi-voltage
synthesis

Determine floor plan

Multi-voltage placement

Clock tree synthesis

Route

Verify timing

Power Integrity Methodologies

Motivation
Ensure that the power delivery network will not
adversely affect the intended performance of the IC
Functional operation
Performance speed and power
Reliability

Method
Analyze specific voltage drop parameters

Effective grid resistances

Static voltage drop
Dynamic voltage drop
Electromigration

Analyze impact of voltage drop upon timing and noise

Power-Integrity Verification Flow

Floorplan, Power Grid
Distribution
Placement, Power
Routing
Check Effective
Resistances

Stimulus Selection
(Vectorless or simulation based)

Static Voltage Drop

Analysis
Dynamic Voltage Drop
Analysis & Optimization

Extracted
Grid RLC

Voltage Drop & EM analyses

(Compute time varying currents)

Routing
Dynamic Voltage Drop
& EM Analysis
Dynamic Voltage Drop
Optimization
Voltage Aware
Timing & SI Analysis
Power Grid Sign-off

Package
Model
Instance
Currents

Voltage Drop optimization

(Spread peak currents,
insert & optimize decaps)

Voltage aware STA/SI

(Compute voltage drop effects
on timing & SI)

Decap
Models

Power Integrity: Effective Resistance Check

Motivation

Resistance Histogram

Verify connectivity of all

circuit elements to the
power grid
Are all elements
connected?
Are all elements
connected to the grid
with a low resistance?

Method
Extract power grid to
obtain R
Isolate and analyze R
in the equation
V(t) = I(t)*R + C*dv/dt *R + L*di/dt

Well formed distribution

of resistances indicates
well-connected
instances

Unexpected outliers
indicate poorly
connected (high R)
Instances.

Power Integrity: Stimulus Selection

Power Integrity: Static Voltage Drop

Motivation
Verify first order voltage drop
Is grid sufficient to handle
average current flows?
Static voltage drop should only
be a few % of the supply
voltage

Method
Extract power grid to
obtain R
Select stimulus
Compute time averaged power
consumption for a typical
operation to obtain I
Compute: V = IR
Non time-varying

0% drop
2.5% drop
5% drop
7.5% drop
10% drop

Typical static voltage drop bulls-eye of

an appropriately constructed power
grid.
But 10% static voltage drop is very
high.

Power Integrity: Dynamic Voltage Drop

Motivation
Verify dynamic voltage drop
Are current and voltage transients within spec?
Can chip function as expected in external RLC environment?

Method

Extract power grid to obtain on-chip R and C

Include RLC model of the package and bond wires
Select stimulus
Compute time varying power for specific operation to obtain I(t)
Compute V(t) = I(t)*R + C*dv/dt*R + L*di/dt

Timestep 1 @ 20 ps

Timestep 2 @ 40 ps

Timestep 3 @ 60 ps

Timestep 4 @ 80 ps

Voltage Drop Mitigation with Decoupling Caps

Explicit decoupling caps can be added to the power
delivery network
Effectiveness highly dependent upon proximity to supply noise aggressor
DECAP
Rpkg Lpkg

On-chip

RVdd

CVdd

Cpkg

Rdecap
Cdecap

Ccoupling

Kmutual

Package +
bond-wire

Rpkg Lpkg
Cpkg

VDD

Rdecap

RVss
CVss

Cn-well

Ron

Ccell
Cp-well

Rsignal
Ron

Csignal

VSS

Decoupling Cap Effectiveness

Decaps placement
based upon
available space

Decaps optimized
placement based
upon dynamic
voltage drop

47 mV improvement after
decap placement optimization

Dynamic Voltage Drop Impact

Timing analysis without voltage drop finds no negative slack paths
Timing analysis with voltage drop uncovers numerous timing violations

Without Voltage Drop

With Voltage Drop

4500
4000
Number of paths

3500

90000

70000

2500
2000
1500
1000

60000

500

50000

40000

-2

-1.5

-1

30000
20000
10000

15

14

13

12

11

10

Slack(ns)

-1

0
-2

Number of paths

80000

3000

-0.5

0.5

Summary - Low Power Methodology Review

Characterization and modeling for power
Required for SoC cell based design flows

Power analysis
Run early and often, during all design phases

Power reduction
Multiple techniques and opportunities during all phases
Most effective opportunities occur during the early design phases

Power integrity
Voltage drop analysis is a critical verification step
Consider the impact of voltage drop upon timing and noise

Some Useful References

Books and Book Chapters

A. Chandrakasan, R. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995.
D. Chinnery, K. Keutzer, Closing the Power Gap Between ASIC and Custom, Springer, 2007.
J. Frenkil, Tools and Methodologies for Power Sensitive Design, in Power Aware Design Methodologies, M. Pedram
and J. Rabaey, Kluwer, 2002.
J. Frenkil and S. Venkatraman, Power Gating Design Automation, in [Chinnery, Springer07].
M. Keating et al, Low Power Methodology Manual For System-on-Chip Design, Springer, 2007.
C. Piguet, Ed., Low-Power Electronics Design, Ch. 38-42, CRC Press, 2005

Articles and Web Sites

Cadence Power Forward Initiative, http://www.cadence.com/partners/power_forward/index.aspx

A. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power Digital CMOS Design," IEEE Journal of Solid State
Circuits, pp. 473-484, April 1992.
N. Dave, M. Pellauer, S. Gerding, Arvind, 802.11a Transmitter: A Case Study in Microarchitectural Exploration,
MEMOCODE 2006.
S. Gary, P. Ippolito, G. Gerosa, C. Dietz, J. Eno, H., Sanchez, PowerPC603, A Microprocessor for Portable
Computers, IEEE Design and Test of Computers, Volume 11, Issue 4, pp. 14-23, Winter 1994.
S. Kosonocky, et. al., Enhanced multi-threshold (MTCMOS) circuits using variable well bias, ISLPED Proceedings,
pp. 165-169, 2001.
Liberty Modeling Standard, http://www.opensourceliberty.org/resources_ccs.html#1
Sequence PowerTheatre, http://www.sequencedesign.com/solutions/powertheater.php
Sequence CoolTime,
http://www.sequencedesign.com/solutions/coolproducts.php
Synopsys Galaxy Power Environment, http://www.synopsys.com/products/solutions/galaxy/power/power.html
Q. Wang and S. Vrudhula, Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 3, pp 306318, March
2002.