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I - Hierarchy of Limits of Power PDF

This document appears to be a seminar presentation on low power VLSI design. It discusses the hierarchy of power limits from fundamental to system level limits. At each level, it describes the theoretical limits constrained by physics and technology, as well as practical limits related to costs. For example, at the device level, theoretical limits include channel length and oxide thickness, while practical limits consider the costs of manufacturing. The presentation aims to explain the key principles for low power design across different levels of abstraction.

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monishabe23
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862 views12 pages

I - Hierarchy of Limits of Power PDF

This document appears to be a seminar presentation on low power VLSI design. It discusses the hierarchy of power limits from fundamental to system level limits. At each level, it describes the theoretical limits constrained by physics and technology, as well as practical limits related to costs. For example, at the device level, theoretical limits include channel length and oxide thickness, while practical limits consider the costs of manufacturing. The presentation aims to explain the key principles for low power design across different levels of abstraction.

Uploaded by

monishabe23
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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NANDHA ENGINEERING COLLEGE

(AUTONOMOUS)
SEMINAR PPT 1

NAME : R.MONISHA
REG NO :19VLF04
DEPT&YEAR : M.E-VLSI DESIGN/II-YEAR
SUBJECT : LOW POWER VLSI DESIGN
TITLE : HIERARCHY OF LIMITS OF POWER
DATE :
HIERARCHY OF LIMITS OF POWER
PRINCIPLES OF LOW- POWER DESIGN

The main key principles of low-power design are:

• Using the lowest possible supply voltage.


• Operating at lowest possible frequency.
• Using parallelism and pipelining to lower required possible
frequency.
• Power management when the system is idle.
• Designing systems to have lowest requirements on
subsystem performance.
HIERARCHY OF LIMITS
Hierarchy of limits have five levels:
• Fundamental
• material
• device
• circuit
• system
Each level has two types of limits:
• Theoretical considerations
• Practical considerations
THEORETICAL LIMITS

The basis for practical limits are:

• Theoretical limits are constrained by the laws of physics and


technological invention.
PRACTICAL LIMITS

The basis for practical limits are:

• The cost of designing, manufacturing, testing and packaging.

• These will cause the cost per function to level off and begin to
increase.
FUNDAMENTAL LIMITS

Independent of devices, materials and Circuits.

Fundamental limits are derived from three basic principles:

• Thermodynamics

• Quantum Mechanics and

• Electromagnetic Theory
MATERIAL LIMITS

• Independent of the particular devices built with the materials.

• The circuits composed from these devices.

• The attributes of material limits are carrier mobility, carrier


saturation velocity, electric field strength and thermal
conductivity.
DEVICE LIMITS
• These are independent of the circuits that may have been
composed with the devices.

• Consider the MOSFET, in which its important attribute is its


minimum effective channel length Lmin.

• To achieve Lmin, both the gate oxide thickness Tox and source-
drain junction depth Xj should be small.

• Also consider the thickness of the oxide layer and its permittivity
for short channel effects.

• For the device limits the switching energy is considered.


CIRCUIT LIMITS
These are independent of the architecture of a particular
system.Here CMOS circuits are considered for discussing the
circuit limits.

Four Basic Principal circuit level limits:

• Basic requirement is the zero error.

• Switching energy per transition.

• Intrinsic gate is delay given by the time taken to


charge/discharge the load capacitance.
SYSTEM LIMITS
These depends on all other limits and are more restrictive ones
in the hierarchy.

Five generic system limits:

• Architecture of the chip,

• Power-delay product of the CMOS technology.

• Heat removal capacity of the chip package.

• Clock frequency and

• Physical size
THANK YOU

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