Assignment Questions
1. Realize the function Y AB CD using CMOS technology .
2. Compare the performance of three MOS switches.
3. The no. of transistors required to implement a -ve edge triggered F/F using CMOS switches is
____.
4. Implement the XNOR gate using only 5 transistors. Assume the variables (A,B) and their
complements ( A , B ) to be available
5. Draw the circuit diagram of tristate inverter using transmission gate.
6. Why is NMOS technology preferred over PMOS technology?
7. List anyone merit and demerit of bipolar ICs over CMOS ICs.
8. State anyone advantage of CMOS logic circuits over bipolar logic circuits.
9. Compare the characteristics of CMOS devices fabricated using n well and p well processes.
10. What is the disadvantage of CMOS device fabricated using n-well process over that using p-well
process?
11. State and explain any three advantages of logic circuits implemented using MUX.
12. Distinguish between positive and negative Photoresists used in IC fabrication.
13. How is schottky diode formed in VLSI circuits?
14. How is the formation of schottky diodes prevented in MOS circuits?
15. What is meant by stick diagram?
16. What is meant by layout design rule?
17. What is meant by (i) DRC (ii) LVS
18. Draw the parasitic bipolar transistors in CMOS circuits.
19. State anyone technique for latch up prevention.
20. What is the voltage across the CMOS gate when latch up occurs?
21. Draw the stick diagram of a CMOS inverter.
22. Explain the different steps in the fabrication of a CMOS device.
23. What are the merits and demerits of SOI process for CMOS device fabrication?
24. No. of transistors required to implement a +ve level triggered latch using CMOS switches is
____.
25. In a IC fab, out of every 500 ICs fabricated 60 ICs were found to be bad in a particular batch.
The yield of the process is ----
26. As per the MOSIS rules what should be the minimum width of (i) metal track (ii) poly
27. In a 180nm technology, the supply voltage used for MOS device is ----.
28. When an NMOS switch is fed with an input voltage of 5V, the voltage at the output is ----.
29. As per the MOSIS rules, the minimum width of the metal interconnect is ----.
30. The no. of MOS devices required to implement a 8 to 1 MUX using CMOS switches is ----.
31. The minimum no. of transistors required to implement a 2 to 1 MUX using transmission gate
(CMOS switches) is --- and that using CMOS gate is ----
32. Compare the no. of transistors required to implement a 4 to 1 MUX using (i) CMOS switches (ii)
CMOS gate
33. Implement the three input EXOR gate using (i) MUX (ii) CMOS gate
34. Compare the minimum no. of transistors required to implement a N variable Boolean function
using (i) CMOS technology (ii) NMOS technology
35. Implement the function Y AB BC CA using only 10 MOS devices.
36. Explain how a programmable logic circuit can be implemented using MUX
37. Explain where the thick oxide is used and why is it used?
38. Implement the XNOR gate using CMOS technology
39. Explain the following properties of MOS technology (i) self isolation (ii) lateral diffusion (iii) self
alignment
40. Explain the layout design rules and their importance
41. In a 90nm technology, what is the length of the smallest transistor? What is the supply voltage
used
42. The value of lambda corresponding to 0.35 micron technology is ----.
43. Estimate the area required for implementing 3 input NOR using MOSIS rules
44. MOS capacitor which is used as a polarized capacitor is ---- . It is normally used as ---- capacitor.
45. What makes the parasitic transistors to conduct
46. Why does the power dissipation in CMOS circuits change with frequency
47. How can the rise time and fall time of a CMOS inverter be made equal
48. List the different steps in fabrication of NMOS and PMOS devices using nwell technology
49. List the advantages of SOI technology
50. In a CMOS inverter, the (W/L ) ratio of PMOS device is double that of NMOS device. The rise
time of the inverter ----
51. The current through an NMOS device is I ds in the saturation region. If the overdrive voltage
(Vgs-Vt ) and length are increased by a factor of 2, the new current Ids’ is ------ Ids.
52. The no. of MOS devices (both NMOS and PMOS) required to realize a 4 to 1 multiplexer using
transmission gate is
53. The frequency of a CMOS circuit is doubled and the supply voltage is reduced by a factor of 4,
the power dissipated by the modified circuit is --- compared to the original circuit
54. The physical characteristics of the MOS device represented by the SPICE parameter “PHI” is
-----.
55. In a MOS device, the drain current I D is increased by a factor of 2 while V GS is kept constant. If
the device operates in saturation region, the transconductance gm increases by a factor of ----.
56. The circuit shown in Fig.1 is (a) NAND (b) NOR (c) AND (d) OR
57. In the circuit shown, The lengths of the transistors are identical and widths of the M1 and M2 are
in the ratio 1:4. The ratio Iout/Iin is
(a) 4 (b) 2 (c) 0.25 (d) 0.5
58. In a PMOS device, the drain is connected to gate and the source is connected to Vdd. Which of
the following statements are true:
(i) It suffers from body effect (ii) It operates in saturation region
(a) only (i) (b) only (ii) (c) both (i) and (ii) (d) neither (i) nor (ii)
59. In a MOS transistor operated in the saturation mode, the drain current is 0.5 mA when Vgs is 2.5
V and Vt is 0.5 V. If the Vgs is changed to 4.5 V and the device remains in saturation, the drain
current is ---- mA.(a) 0.9 (b) 1 (c) 1.5 (d) 2
60. A Common Source amplifier with MOS transistor M1 has the NMOS diode connected transistor
M2 as the load. The W/L ratios of M1 and M2 are A and B respectively. The W/L ratio of M2
required to increase the voltage gain of this amplifier by a factor of 2 is (a) 0.25 B (b) 0.5B
(c) 2B (d) 4B
61.
62.
63.
64. The drain current Ids of MOSFET in saturation is given by I ds= k(VGS-VT)2. The
transconductance gm is given by
(a) (b) (c) (d) 2
65. How are Ron , the resistance of the channel in the triode region and g m, the transconductance of
the MOS device in the saturation region related ?
66. Determine how the transconductance of a MOSFET operating in saturation region changes if
(a) W/L is doubled but ID remains constant
(b) VGS – VTH is doubled but ID remains constant
(c) ID is doubled but W/L remains constant
(d) ID is doubled but VGS – VTH remains constant
67.
68. In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation (using steam or
water vapor) produces
69. In a MOSFET operating in the saturation region, the channel length modulation effect causes (A)
an increase in the gate-source capacitance (B) a decrease in the Transconductance (C) a decrease
in the unity-gain cutoff frequency (D) a decrease in the output resistance
70. In CMOS technology, shallow P-well or N-well regions can be formed using
(A) low pressure chemical vapour deposition
(B) low energy sputtering
(C) low temperature dry oxidation
(D) low energy ion-implantation
71. In MOSFET fabrication, the channel length is defined during the process of
(A) Isolation oxide growth
(B) Channel stop implantation
(C) Poly-silicon gate patterning
(D) Lithography step leading to the contact pads
72. The slope of the ID vs VGS curve of an n-channel MOSFET in linear regime is 10-3at V DS0.1V. For the
same device, neglecting channel length modulation, the slope of the √I D
vs VGS curve in √A /V under
saturation regime is approximately ___________.
73. An ideal MOS capacitor has boron doping-concentration of 10 15 cm-3 in the substrate. When a gate voltage
is applied, a depletion region of width 0.5 μm is formed with a surface (channel) potential of 0.2 V. Given
that o8.854 × 10-14 F/cm and the relative permittivities of silicon and silicon dioxide are 12 and 4,
respectively, the peak electric field (in V/μm) in the oxide region is __________________.
74. The output (Y) of the circuit shown in the figure is
75. The current through an NMOS device is Ids in the saturation region. If the overdrive voltage
(Vgs-Vt ) and length are increased by a factor of 2, the new current Ids’ is ------ Ids.
(a) 0.5 times (b) equal to (c) 2 times (d) 4 times
