Unit-1

MOS Transistor Principle

•NMOS and PMOS transistors

•Process parameters for MOS and CMOS
•Electrical properties of CMOS circuits and device modeling
•Scaling principles and fundamental limits
•CMOS inverter scaling
• propagation delays
•Stick diagram
•Layout Diagrams

[Link] AP/ECE
 Silicon Lattice
• Transistors are built on a silicon substrate
• Silicon is a Group IV material
• Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

[Link] AP/ECE
 Dopants
• Silicon is a semiconductor
• Pure silicon has no free carriers and conducts poorly
• Adding dopants increases the conductivity
• Group V: extra electron (n-type)
• Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

[Link] AP/ECE
 P-N JUNCTIONS
• A junction between p-type and n-type semiconductor
forms a diode.
• Current flows only in one direction

p-type n-type

anode cathode

[Link] AP/ECE
 NMOS-Transistor
Source Gate Drain
Polysilicon
SiO 2

G
n+ n+
S D
p bulk Si

@NMOS: Body is (commonly) tied to ground (0 V)

@PMOS: Body is (commonly) tied to VDD

[Link] AP/ECE
 PMOS-Transistor

Source Gate Drain

Polysilicon
SiO2

p+ p+

n bulk Si

[Link] AP/ECE
 Transistors as Switches
• We can view MOS transistors as electrically controlled
switches
• Voltage at gate controls path from source to drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

[Link] AP/ECE
 MOS Transistor Theory
INTRODUCTION

Three modes
1. Accumulation mode
2. Depletion region
3. Inversion region

[Link] AP/ECE
 NMOS CUTOFF

• No channel
• Ids = 0 Vgs = 0 Vgd
+ g +
• This mode of - -
s d
Operation is
n+ n+
called cutoff p-type body
b

[Link] AP/ECE
 NMOS LINEAR
• Channel forms Vgs > Vt Vgd = Vgs
g
+ +
• Current flows from -s -
d

drain to source n+ n+ Vds = 0

p-type body
• Ids increases with Vds b

• Similar to linear Vgs > Vt Vgs > Vgd > Vt

g
resistor + +
-s -
d Ids
• Linear, resistive, n+ n+ 0 < Vds < Vgs-Vt
p-type body
unsaturated b

[Link] AP/ECE
 NMOS SATURATION

• Channel pinches off

• Ids independent of Vds
• We say current saturates
• Similar to current source
V gs > V t
g V gd < V t
+ +
- -
s d Ids

n+ n+
V ds > V gs -Vt
p-type body
b

[Link] AP/ECE
 IDEAL I-V CHARACTERISTICS
• MOS transistor have three regions of operation:
1. cutoff region
2. Linear or non saturation region
3. Saturation region

Transistor Dimensions Average gate to channel voltage

[Link] AP/ECE
 I-V CHARACTERISTICS

nMOS Transistor pMOS Transistor

[Link] AP/ECE
 C-V CHARACTERISTICS

•Each terminal of MOS transistor having capacitance

to other terminals. These capacitances are non-linear
and voltage dependent(C-V)

SIMPLE MOS CAPACITANCE MODEL:

•Gate of a MOS transistor is a good capacitor and it’s
capacitance is necessary to attract charge carriers to
invert channel.

•So high Cg is required to get high Ids.

•Cg is the capacitance with the gate on top and

channel on bottom [Link]
thin dielectric as Sio2.
AP/ECE
 SIMPLE MOS CAPACITANCE MODEL cont……
Therefore, the capacitance is,
•Most transistor used in minimum transistor length which
results in greater speed & lowest power consumption. We can
define

Where,

•The S and D also have capacitances and they are not

fundamental to the operation of devices.
•But do impact on circuit performance & hence are called
parasitic capacitance.
•They arise from the reversed biased p-n junctions b/w the
S or D diffusion and the body and hence also called
diffusion capacitances Csb and Cdb.
[Link] AP/ECE
DETAILED MOS GATE CAPACITANCE:

•MOS gate sits above the channel and overlap S & D diffusion
areas. Therefore, the Cg has 2 components:

Intrinsic capacitance(over the channel)

The overlap capacitance( to the S, D, body)

•The intrinsic capacitance approximated as simple parallel plate

capacitance as

•Bottom plate of the capacitor depends on the mode of

operation

[Link] AP/ECE
DETAILED MOS GATE CAPACITANCE cont…..

[Link] AP/ECE
DETAILED MOS GATE CAPACITANCE cont…..

Fig. overlap capacitance

[Link] AP/ECE
DETAILED MOS GATE CAPACITANCE cont…..

•The G overlaps S & D and also by a small amount in a real

device & also has fringing fields terminating on the S and D.
This leads to a additional overlap capacitance.

•These capacitance are proportional to the width of the

transistor. The values are Cgsol = Cgdol =0.2-0.4fF/μm.

[Link] AP/ECE
DETAILED MOS DIFFUSION CAPACITANCE MODEL:
•Reverse biased p-n junction b/w the S diffusion & the body
contributes parasitic capacitance ant it depends on both area
AS & sidewall perimeter PS of the S diffusion region.

•The area AS = W*D and the perimeter PS = 2W + 2D.

•The total Source parasitic capacitance is

Csb = AS * Cjbs + PS*Cjbssw

Cjbs = Capacitance / area

Cjbssw = capacitance / legth.

[Link] AP/ECE
[Link] AP/ECE
 Non ideal I-V effects
• The ideal I-V model neglects many effects that are
important to modern devices.
Ids (A)

Simulated
Vgs = 1.0
Ideal
1200
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

1000
Ion = 747 mA @
Channel length modulation: V = V = V
gs ds DD
Saturation current increases
800 with Vds Vgs = 1.0

Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Vgs = 0.8
Saturation current increases less than
400 quadratically with Vgs

Vgs = 0.6
200 Vgs = 0.6
Vgs = 0.4
0 Vds
0 0.2 0.4 0.6 0.8 1
[Link] AP/ECE
 Velocity Saturation & Mobility Degradation
• At high lateral field strengths (Vds/L), carrier velocity
ceases to increase linearly with field strength. This is
called velocity Saturation.

• Strong vertical electrical fields

resulting from large Vgs causes
the carriers to scatter against the
surface and also reduces the
Carrier Mobility. This effect is
called mobility degradation. This
Leads to less current than expected
at high Vgs.
[Link] AP/ECE
 Channel Length Modulation
• Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse bias
– Leff = L – Ld
• Shorter Leff gives more current
– Ids increases with Vds
– Even in saturation GND V V DD DD
Source Gate Drain
Depletion Region
Width: Ld

n L n
+ Leff +
p GND bulk Si
[Link] AP/ECE
 Channel Length Modulation


  Vt  1  Vds 
2
I ds  V gs
2
 = channel length modulation coefficient
not feature size
Empirically fit to I-V characteristics

[Link] AP/ECE
 Body Effect

• Body is a fourth transistor terminal

• Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
Vt  Vt 0  g  fs  Vsb  fs 
• fs = surface potential at threshold
NA
fs  2vT ln
ni
– Depends on doping level NA
– And intrinsic carrier concentration ni
• g = body effect coefficient
tox 2q si N A
g 2q si N A 
 ox Cox

[Link] AP/ECE
 Subthreshold Conduction
• Several sources of leakage resulting in current flow in
nominal off transistors.
• Vgs<Vt , the current drops off exponentially rather than
abruptly becoming zero. This is called subthreshold
conduction.

[Link] AP/ECE
 Junction Leakage
• The source and drain diffusions are reverse-biased
diodes and also experience junction leakage into the
substrate or well.

p+ n+ n+ p+ p+ n+

n well
p substrate

[Link] AP/ECE
 Tunneling

• The current into the gate Ig is ideally zero.

However, as the thickness of gate oxide reduces
to only a small number of atomic layers,
electrons tunnel through the gate, causing some
gate current.

[Link] AP/ECE
 Temperature Sensitivity
• Increasing temperature
– Reduces mobility
– Reduces Vt
• ION decreases with temperature
• IOFF increases with temperature

[Link] AP/ECE
 CMOS TECHNOLOGIES
• The four main CMOS technologies
 n-Well process
 p-Well process
 Twin-tub Process
 Silicon on Insulator

[Link] AP/ECE
 Fabrication process of a simple metal
oxide semiconductor (MOS) transistor

polysilicon gate metal connection to gate

doped silicon
top nitride metal connection
to drain
metal connection
to source

field oxide
oxide gate oxide
source drain
silicon substrate gate oxide
[Link] AP/ECE
The manufacture of a single MOS
transistor begins with a silicon
substrate.

silicon substrate
[Link] AP/ECE
 A layer of silicon dioxide (field oxide)
provides isolation between devices
manufactured on the same substrate.

field oxide

oxide

silicon substrate
[Link] AP/ECE
Photoresist provides the means for
transferring the image of a mask
onto the top surface of the wafer.

photoresist
oxide
silicon substrate
[Link] AP/ECE
 Ultraviolet light exposes
photoresist through windows in a
photomask.
Ultraviolet Light

Chrome plated
glass mask
Shadow on
photoresist

Exposed area of
photoresist

photoresist
oxide

silicon substrate
[Link] AP/ECE
 Exposed photoresist becomes
soluble and can be easily removed
by the develop chemical.

Exposed area of photoresist

Unexposed area
of photoresist

photoresist
oxide

silicon substrate
[Link] AP/ECE
 Unexposed photoresist remains on
surface of oxide to serve as a
temporary protective mask for areas of
the oxide that are not to be etched.

Shadow on
photoresist photoresist
photoresist

oxide

silicon substrate
[Link] AP/ECE
Areas of oxide protected by
photoresist remain on the silicon
substrate while exposed oxide is
removed by the etching process.

photoresist

oxide oxide
siliconsubstrate
silicon substrate
[Link] AP/ECE
 The photoresist is stripped off --
revealing the pattern of the field oxide.

field oxide

oxide oxide
siliconsubstrate
silicon substrate
[Link] AP/ECE
 A thin layer of oxide is grown on the
silicon and will later serve as the gate
oxide insulator for the transistor being
constructed.

thin oxide layer

gate oxide

oxide oxide

silicon substrate
[Link] AP/ECE
The gate insulator area is defined by
patterning the gate oxide with a
masking and etching process.

gate oxide

oxide oxide

silicon substrate
[Link] AP/ECE
 Polysilicon is deposited and will
serve as the building material for
the gate of the transistor.

gate oxide

gate oxide
polysilicon

oxide oxide

silicon substrate
[Link] AP/ECE
 The shape of the gate is defined
by a masking and etching step.

ultra-thin
gate oxide
polysilicon
gate

gate
oxide gate oxide

silicon substrate
[Link] AP/ECE
 Dopant ions are selectively implanted
through windows in the photoresist mask.
ion beam

Scanning direction of
ion beam
implanted ions in active
region of transistors
photoresist
Implanted ions in
photoresist to be
removed during
resist strip.

gate
oxide gate oxide
source drain
silicon substrate
[Link] AP/ECE
 The source and drain regions of the
transistor are made conductive by
implanting dopant atoms into
selected areas of the substrate.

doped silicon

gate
oxide gate oxide
source drain
silicon substrate
[Link] AP/ECE
A layer of silicon nitride is deposited
on top of the completed transistor to
protect it from the environment.

top nitride

gate
source drain
silicon substrate
[Link] AP/ECE
Holes are etched into selected
parts of the top nitride where
metal contacts will be formed.

contact holes

gate
source drain
silicon substrate
[Link] AP/ECE
Metal is deposited and selectively
etched to provide electrical contacts
to the three active parts of the
transistor.
metal contacts

oxide gate oxide

source drain
silicon substrate
[Link] AP/ECE
 Completed structure of a simple MOS
transistor

polysilicon gate metal connection to gate

doped silicon
top nitride metal connection
to drain
metal connection
to source

field oxide
oxide gate oxide
source drain
silicon substrate gate oxide
[Link] AP/ECE
 P-Well process

•In p-well process the structure consists of an n-type substrate in which

p-devices may be formed by suitable masking and diffusion.

[Link] AP/ECE
The twin-tub process

[Link] AP/ECE
 The twin-tub process

Advantages:
1. Both n-well and p-well are fabricated on single n-
type substrate.
2. Possible to tune independently threshold voltage,
body effect..
3. Separate optimization of the p-type & n- type
transistors.

Disadvantages:
1. Requires lot of mask
2. Complex

[Link] AP/ECE
 Silicon on Insulator

• Transistors are fabricated on an insulator.

• Two main insulators are used, Sio2 and sapphire.
• Advantages:
1. Insulating Substrate eliminates the capacitance
between the source/ drain and body, leading to
higher-speed devices.
2. Lower Subthreshold Leakge
Two types:
1. Sapphire substrate
2. Silicon based SOI process

[Link] AP/ECE
• Sapphire substrate

• Silicon Based SOI

[Link] AP/ECE
• SOI Devices are categorized as Partially depleted(PD) or
fully depleted(FD).

• In FD SOI, the body is thinner than the channel

depletion width, so the body charge is fixed and thus the
body voltage does not change.

• In PD SOI, the body is thicker and its voltage can vary

depending on how much charge is present. This varying
body voltage in turn changes Vt through the body effect.

• FD SOI has been difficult to manufacture because of the

thin body.

[Link] AP/ECE
• Floating Body Voltage:
If the body voltage were constant, the threshold
voltage would be constant and the transistor would
behave much like conventional bulk device except
that the diffusion capacitance is lower.

In Pd SOI, the floating body voltage varies as it

charges or discharges.

Two path for charging:

1. Reverse biased drain to body and source to body
junctions carry small leakage current into the body.

2. High energy carriers cause impact ionization. This

current into the body is AP/ECE
[Link] modeled as current source.
• SOI Advantages:
1. Lower diffusion capacitance.
2. In SOI process lower nominal Vt results in faster
transistors, especially in lower Vdd.
• SOI Disadvantages:
[Link] SOI suffers from history effect. Body voltage
reduces the threshold and makes gate faster, but the
uncertainty makes circuit design more challenging.
2. Presence of parasitic bipolar transistor within each
transistor.
3. Self heating.

[Link] AP/ECE
 CMOS Fabrication
• CMOS transistors are fabricated on silicon
wafer
• Lithography process similar to printing press
• On each step, different materials are
deposited or etched
• Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process

[Link] AP/ECE
 Inverter Cross-section
• Typically use p-type substrate for nMOS
transistors
• Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

[Link] AP/ECE
 Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
• Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap
[Link] AP/ECE
 Inverter Mask Set
• Transistors and wires are defined by masks
• Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

[Link] AP/ECE
 Detailed Mask Views
• Six masks n well

– n-well
– Polysilicon Polysilicon

– n+ diffusion n+ Diffusion

– p+ diffusion p+ Diffusion

– Contact Contact

– Metal
Metal

[Link] AP/ECE
 Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

[Link] AP/ECE
 Oxidation
• Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

[Link] AP/ECE
 Photoresist
• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

[Link] AP/ECE
 Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist

Photoresist
SiO2

p substrate

[Link] AP/ECE
 Etch
• Etch oxide with hydrofluoric acid (HF)
• Only attacks oxide where resist has been
exposed

Photoresist
SiO2

p substrate

[Link] AP/ECE
 Strip Photoresist
• Strip off remaining photoresist
– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step

SiO2

p substrate

[Link] AP/ECE
 n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
• Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si

SiO2

n well

[Link] AP/ECE
 Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of
steps

n well
p substrate

[Link] AP/ECE
 Polysilicon
• Deposit very thin layer of gate oxide
• Chemical Vapor Deposition (CVD) of silicon
layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Polysilicon
Thin gate oxide

n well
p substrate

[Link] AP/ECE
 Polysilicon Patterning
• Use same lithography process to pattern
polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

[Link] AP/ECE
 Self-Aligned Process
• Use oxide and masking to expose where n+
dopants should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-
well contact

n well
p substrate

[Link] AP/ECE
 N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate
[Link] AP/ECE
 N-diffusion cont.
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+

n well
p substrate

[Link] AP/ECE
 N-diffusion cont.
• Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

[Link] AP/ECE
 P-Diffusion
• Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

[Link] AP/ECE
 Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

[Link] AP/ECE
 Metalization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

[Link] AP/ECE
 Layout Design Rules
• Layout design rules describe how small features can be
and how closely they can be packed in a particular
manufacturing process.

• The rules are defined in terms of feature sizes(widths),

separations, and overlaps.

• Industrial design rules are specified in microns. Lambda

based design rules based on a single parameter λ.

• The rules describe the minimum width to avoid breaks

in a line, minimum spacing to avoid shorts between
lines, and the minimum overlap to ensure two layers
completely overlap.
[Link] AP/ECE
Design Rules for layouts with two metal layers in
an n-well process is as follows…

[Link] AP/ECE
Simplified λ based design rules

[Link] AP/ECE
• Inverter with dimensions Labeled
Transistor dimensions are often specified by their
Width/length(W/L) ratio.

[Link] AP/ECE
 Gate Layout
• For many applications, a straight forward layout is good
enough and can be automatically generated or rapidly
built by hand.

• Line of diffusion rule- this style consist of four horizontal

strips: metal ground at the bottom of the cell, n-diffusion,
p-diffusion, and the metal power at the top.

• The power and ground lines are often called supply rails.
Polysilicon lines run vertically to form transistor gates.
Metal wires within the cell connect the transistors
appropriately.

[Link] AP/ECE
• Inverter standard cell layout

[Link] AP/ECE
 Design Rules Background
• Well Rules:
 The n-well is usually a deeper implant than the
source/drain implants, and therefore, it is
necessary for the outside dimension to provide
sufficient clearance between the n-well edge.

 The mask encountered for well specification may

include n-well, p-well, and deep n-well.

 Only one well is specified in a twin-well process

(n-well) and by default the p-well is in areas where
the n-well isn’t.
[Link] AP/ECE
• Transistor Rules:
• CMOS Transistors are generally defined by at least four
physical masks.
1. active, 2. n-select, 3. p-select, 4. polysilicon.

• Active mask defines all areas where either n- or p-type

diffusion is to be placed or where the gates of
transistors are to be placed.

• n-select surrounds active regions where the n-type

diffusion is required.

• p-select surrounds active regions where the p-type

diffusion is required.

• Gate extension-Poly extend beyond the edges of the

active area to avoid shortening by a diffusion path
between source and drain.

[Link] AP/ECE
[Link] AP/ECE
• Contact Rules:
• There are several generally available contacts:
– Metal to p-active(p-diffusion)
– Metal to n-active(n-diffusion)
– Metal to polysilicon
– Metal to well or substrate
• The substrate is divided into well regions, each
isolated well must be tied to appropriate supply
voltage. nwell-must be tied to Vdd and the
substrate or pwell must be tied to GND with well
or substrate contacts.
• Metal makes a poor connection to the lightly
doped substrate or well. Hence, a heavily doped
active region is placed beneath the contact.
• Contacts are normally of uniform size.
[Link] AP/ECE
[Link] AP/ECE
• Metal Rules:
• Metal spacing may vary with the width of the
metal line.
• Spacing rules that are applied to long, closely
spaced parallel metal lines.
• Scribe Line:
• The Scribe line surrounds the completed chip
where it is cut with diamond saw. The
construction of the scribe line varies from
manufacturer to manufacturer.
• It is designed to prevent the entry of contaminants
from the side of the chip.

[Link] AP/ECE
 Technology related CAD issues
Two basic checks have to be completed to ensure that
this description can be turned into a working chip.

• Specified geometric design rules must be obeyed.

• The interrelationship of the mask.

To check these two requirements, two basic CAD tools are

required
1. Design Rule Check(DRC) Program
2. A mask circuit extraction program

[Link] AP/ECE
• Design Rule Check:
Program to determine what we have designed by
examining the interrelationship of the various mask
layers, it may be necessary to determine various logical
between masks.

[Link] AP/ECE
The following Layers will be assumed as inputs
nwell
active
p-select
n-select
poly
poly-contact
active-contact
metal
Typically, useful sublayers are first generated.

[Link] AP/ECE
• To find the transistors, the following rule set is used:

• Typical design rules includes the following

CIRCUIT EXTRACTION:
To determine the electrical connectivity of a mask
database, the following commands are required.

[Link] AP/ECE
• The connections Between the layers can be specified as
follows:

• The active devices are specified in terms of the layers

[Link] AP/ECE
 DC Transfer Characteristics

It relates the output voltage to the input

voltage , assuming the input voltage slow
enough that capacitance have plenty of time
to charge or discharge

• DC Response
• Beta Ratio effects
• Noise Margins
• Pass Transistors [Link] AP/ECE
 DC Response
• DC Response: Vout vs. Vin for a gate
• Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0 VDD
– In between, Vout depends on
Idsp
transistor size and current Vin Vout
Idsn
– By KCL, must settle such that
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
[Link] AP/ECE
 Transistor Operation
• Current depends on region of transistor
behavior
• For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?

[Link] AP/ECE
 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin
Idsp
Vdsn = Vout Vin Vout
Idsn

[Link] AP/ECE
 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0
Idsp
Vdsp = Vout - VDD Vin Vout
Idsn

[Link] AP/ECE
 I-V Characteristics
• Make pMOS is wider than nMOS such that n
= p V gsn5

Idsn Vgsn4

-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

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 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

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 Operating Regions
• Revisit transistor operating regions VDD

Vin Vout

Region nMOS pMOS

A Cutoff Linear
VDD
B Saturation Linear A B

C Saturation Saturation Vout

C
D Linear Saturation
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

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 Beta Ratio
• If p / n  1, switching point will move from
VDD/2
• Called skewed gate
• Other gates: collapse into equivalent inverter
VDD
p
 10
n
Vout 2
1
0.5
p
 0.1
n

0
VDD
Vin
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 Noise Margins
• How much noise can a gate input see before it
does not recognize the input?
Output Characteristics Input Characteristics
VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

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 Logic Levels
• To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic

Vout

Unity Gain Points

VDD
Slope = -1
VOH

 p/ n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

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 Pass Transistors
• Transistors can be used as switches

g=0 Input g = 1 Output

g
s d 0 strong 0
s d g=1 g=1
s d 1 degraded 1

g=0 Input Output

g=0
g s d 0 degraded 0

s d g=1
g=0
s d 1 strong 1

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 Transmission Gates
• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

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 Tristate Inverter
• Tristate inverter- cascading transmission
gate with an inverter.
• EN=0 ,output-tristate condition.
EN=1, o/p= complement
A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A
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