This document introduces the fundamental components of VHDL code: libraries, entity, and architecture. It provides examples of how to write each component. The goal of the experiment is to design, code, simulate, and test a 3-8 decoder circuit using VHDL. Procedures outline designing the decoder truth table, implementing the decoder in VHDL, simulating it, programming an FPGA board, and testing it. Questions for the report ask about the purpose of the entity and architecture, how an entity can have multiple architectures, and writing VHDL code for the 3-8 decoder using a CASE statement.
This document introduces the fundamental components of VHDL code: libraries, entity, and architecture. It provides examples of how to write each component. The goal of the experiment is to design, code, simulate, and test a 3-8 decoder circuit using VHDL. Procedures outline designing the decoder truth table, implementing the decoder in VHDL, simulating it, programming an FPGA board, and testing it. Questions for the report ask about the purpose of the entity and architecture, how an entity can have multiple architectures, and writing VHDL code for the 3-8 decoder using a CASE statement.
This document introduces the fundamental components of VHDL code: libraries, entity, and architecture. It provides examples of how to write each component. The goal of the experiment is to design, code, simulate, and test a 3-8 decoder circuit using VHDL. Procedures outline designing the decoder truth table, implementing the decoder in VHDL, simulating it, programming an FPGA board, and testing it. Questions for the report ask about the purpose of the entity and architecture, how an entity can have multiple architectures, and writing VHDL code for the 3-8 decoder using a CASE statement.
This document introduces the fundamental components of VHDL code: libraries, entity, and architecture. It provides examples of how to write each component. The goal of the experiment is to design, code, simulate, and test a 3-8 decoder circuit using VHDL. Procedures outline designing the decoder truth table, implementing the decoder in VHDL, simulating it, programming an FPGA board, and testing it. Questions for the report ask about the purpose of the entity and architecture, how an entity can have multiple architectures, and writing VHDL code for the 3-8 decoder using a CASE statement.
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Advanced Digital Electronics Laboratory Exp.
3 Experiment 3 Fundamental VHDL Units ( LIBRARY, ENTITY and ARCHITECTURE ) Design Example Decoder Learning Objectives: 1. To introduce the fundamental sections that comprise a piece of VHDL code: LIBRARY declarations, ENTITY, and ARCHITECTURE. 2. To design, synthesize, and simulate the operation of a decoder circuit with VHDL language. 3. After that your design can be downloaded to a Xilinx FPGA. 4. Test the Results Equipment and Materials: 1- Full version of Xilinx ISE 9.2i software installed on your laboratory personal computer. 2- Xilinx Spartan-3E Starter Kit, including download cable and power supply Introduction:
A VHDL code is composed of at least three fundamental sections
1- LIBRARY : Contains a list of all libraries to be used in the design. To declare a LIBRARY two lines of code are needed, one containing the name of the library, and the other a use clause, as shown in the syntax below.
Examples:
2- ENTITY: Specifies the I/O pins of the circuit. Its syntax is shown below.
1 Advanced Digital Electronics Laboratory Exp.3 Example: Let us consider the 2 inputs NAND gate. Its ENTITY can be specified as:
3- -ARCHITECTURE: Contains the VHDL code, which describes how the circuit should behave (function). Its syntax is the following:
Example: Let us consider the NAND gate of above entity.
Procedures: 1. Design the 3–8 Decoder circuit and prepare the truth table. 2. Implement 3–8 Decoder with (VHDL) using Xilinx ISE 9.2i tools for Spartan 3E FPGA board. Follow the same steps as before in previous Experiments to synthesize and obtain a timing diagram after simulation to verify correct outputs. 3. Test it by sliding the programmed switches up and down for ON and OFF. See if the appropriate LEDs for the outputs turn on. The truth table should guide you with your test. 4. Create a UCF (user constraint file) and assign the FPGA pins to the Decoder inputs and outputs. The inputs will be assigned to any switch, and output of Decoder will be assigned to LED’s 0-7. 5. Plug the Spartan 3E board into your computer and turn the board’s power on. Expand the “Generate Programming File” process in the Processes window and double click “Configure Device (iMPACT), and continue as in the previous lab. 6. Record your results ( Truth table, VHDL code, RTL, Timing diagram, UCF file) Report : 1- What does the entity do? 2- What does the architectures do? 3- In VHDL language, a single entity can have multiple architectures, explain that. 4- Write the VHDL code required to implement 3 – 8 Decoder circuit using CASE statement. 2
