CPE 169 EXPERIMENT SIX

Title: BCD-to-7 Segment Decoder Design using VHDL (CPLD)

Time: 180 minutes
Author: December5, 2002 by A. Liddicoat
Updated:
April 30, 2003 by A. Liddicoat
November 15, 2003 by A. Liddicoat
Hardware:
Software:
Components:

Pentium 4 Computer and Digilab XCR Plus Development Board

Xilinx ISE and ModelSim
Xilinx CoolRunner XPLA3 CPLD (on development board)

Purpose
To introduce the student to the hardware description language VHDL, the digital system design
environment of Xilinx ISE, the Xilinx Coolrunner XPLA3 CPLD, and the Digilab XCR Plus
development board. The student will learn how to design, simulate, synthesize, download, and verify
a combinational logic circuit using programmable logic (CPLD). The student will design build and
test a BCD-7 Segment decoder using VHDL and the Xilinx ISE design environment and the Digilent
XCR Development Board.

Introduction
This experiment describes how to develop VHDL-based systems. The student is taken through the design
flow: the initial system specification, writing and simulating VHDL code, synthesizing the VHDL code
into a digital circuit implementation, downloading the circuit configuration into a programmable device
and then verifying the functionality of the circuit using the development board. The student is first asked
to follow a tutorial that takes them through the design flow with a simple combinational circuit, the 3 input NAND function. The VHDL hardware description language and Xilinx ISE VHDL development
environment is used to enter, compile, and simulate the design. After the student simulates the design
using the Xilinx ISE development environment, the VHDL code is synthesized (using CAD tools) into
a digital circuit appropriate for implementation with programmable logic. After synthesizing the design
into a hardware representation it is downloaded into the CoolRunner CPLD (Complex Programmable
Logic Device) on the development board for verification. Take your time following the tutorial and make
sure you understand the design process. After the student has become comfortable with the design flow
and the tutorial, they are asked to design, implement and verify a more difficult digital circuit.

VHDL Hardware Description Language

The Department of Defense, DOD, first developed VHDL as a hardware description language around
1980. VHDL later became an IEEE standard in 1987, and was further revised in 1993. For the purposes of
this introduction, a VHDL design consists of two parts, the entity and its architecture. The entity
describes the "black box" features of the design in terms of its inputs and outputs. It is similar to a
function prototype in software. The architecture contains the design implementation inside the "black
box". The architecture is similar to the software function itself. As this experiment demonstrates, a
functional specification may be entered many different ways since there are many ways in VHDL to
describe the same design. For simple designs, the compiler will simplify the design and generate the same
circuit implementation even if the architecture is coded differently . The designer has a great deal of
flexibility in describing the design of their digital system with VHDL, and can use the form that they feel
most comfortable with. In the next section, you will find an example of VHDL source code with a
description and comments to help you understand the VHDL source code.

VHDL Source Code

1- Everything after a double hyphen is a comment in VHDL.
2- VHDL is case insensitive so you can use upper or lower case or any mixture thereof.
library ieee;

-- The library statement allows access to a pre -made

-- library (in this case the ieee library).

use ieee.std_logic_1164. all;

-- The use statement allows you to use a package within

-- a library for your design. In this case, we are using all
-- of the std_logic_1164 package within the ieee library.

entity <your entity name> is port (

-- All VHDL files need to have an entity declaration. The

-- entity declaration is the black box view of your circuit
-- that declares the inputs and outputs of the circuit.
-- Inputs a,b,c, and d are declared as type std_logic.
-- Std_logic is contained in the ieee library we included above
-- and allows a signal to take on typical logic values such
-- as '0' or '1'.
-- Outputs y and z are declared as type std_logic.

a, b, c, d : in std_logic;

y, z : out std_logic);
end <your entity name>;

-- This ends the entity declaration.

architecture <your architecture name> of <your entity name> is

-- This begins the architecture section of your code, here
-- you will specify the actual functionality of your circuit.
signal sig1, sig2, sig3 : std_logic;

begin

-- The signal declaration is similar to the input and output

-- declarations, except these signals are only visible to this
-- architecture (like local variables). Signals can be thought
-- of as names for internal nodes in your circuit, or as
-- internal variables in a program.
-- Begin starts the architecture description.

sig1 <= a and b;

-- This is a sample concurrent signal assignment equation

-- in VHDL, notice that <= is the assignment operator.
-- The value of a ANDed with b is assigned to sig1.

sig2 <= 1 ;
sig3 <= 0;

-- Assigning constants to signals

[other concurrent signal assignments]

end <your architecture name>

-- Note that at some point you should have your final

-- values assigned to your outputs.

VHDL Design Flow

The design flow starts with a problem statement or specification. Then the VHDL entity and architecture
source code is written to meet the specification. For small designs, the source will be compiled to fit into
a single PLD or CPLD device. VHDL allows for hierarchical designs so for more complicated designs,
source code files may be compiled into separate modules, which may in turn contain other modules or
components . These modules can then be used in the top level source code.
The Xilinx ISE software uses the ModelSim hardware simulator to simulate and display timing diagrams
for the entity (inputs and output signals, as well as signals that are internal to the architecture if required).
These timing diagrams are used to verify the functionality of the design. Simulation is important since we
cannot observe signals inside of the programmable logic device to debug an incorrect design.
The Xilinx ISE software is then used to synthesize (or compile) the VHDL source code into a
configuration file for the programmable logic device. The inputs and outputs for your circuit will be
assigned to pins on the CPLD that are connected to switches and LEDs on the development board. You
must enter the pin assignment into a constraint file for your design. Once your constraint file has been
entered the CPLD configuration file can be downloaded into the CPLD on the development board by
using the IMPACT function of the Xilinx ISE software. After the chip has been programmed, the student
will test the resulting hardware design using the switches to set the circuit inputs to 0s and 1s and
observe the outputs via the LEDs.

BCD to 7-Segment Decoder:

You are to design a Binary Coded Decimal (BCD) to 7 -Segment Decoder and demonstrate it using the
Digilab XCR Plus Development Board. The BCD code uses a 4-bit nibble to represent decimal digits from
0 to 9. The BCD code is equivalent to the 4-bit binary representation for the digits 0-9. Binary codes
greater than 9 are undefined (dont cares). The 7 -Segment display is used to illuminate the decimal digits
from 0-9. Each of the LED bars in the display forms one of the segments. The segments are labeled a-g as
shown below in figure 2 below. The BCD inputs should light the 7-Segment Display as shown below in
Table 1 below.
The switches SW5-SW8 will be used to enter a 4 bit BCD number. The least significant 7 -Segment digit
on the development board will be used to display the decimal equivalent of the BCD number. In the
following sections a description of the sliding switches, the Common Cathode 7-Segment Display and the
associated circuits on the development board are described.

BCD Input Switches

You will use 4 switches on the development board to set the BCD input for the decoder. Use the switches
SW5, SW6, SW7, and SW8 to set the BCD input for the decoder with SW5=a 3, SW6=a2, SW7=a 1, and
SW8=a0. Here a3 is the most significant bit and a0 is the least significant bit. Figure 1 below shows how
each of the switches are wired on the development board. The signals SW1-SW8 are connected to I/O
pins on the CPLD. Therefore, by setting these pins to inputs in the constraint file and assigning them to
the VHDL signal names (a 3-a0) you can use the switches to set the BCD inputs into the decoder.

Vcc
Switch Position
Up

4.7 kO
SWn ? CPLD Pin

Down

n = (1, 2, 3, 4, 5, 6, 7 or 8)

Figure 1: Sliding Switc h circuit on the Development Board

7-Segment Display
The 7-Segment display is used to illuminate the decimal digits from 0 -9. Each of the LED bars in the
display forms one of the segments. The segments are labeled a -g as shown below in figure 2. Applying a
positive voltage across one of the diode segments will cause the LED to light. The development board 7 Segment display circuit is shown in Figure 2. The signals AA-AG and CAT2 are wired to I/O pins on the
CPLD. Your BCD to 7 -Segment decoder should drive these signals to light the proper LED segments
and display the decimal digits 0 -9 when the appropriate BCD value is input into the decoder circuit. The
CAT2 signal drives an active pulldown transistor. The transistor operates as a voltage controlled switch. If
CAT2 has a high voltage then the switch between the LED Cathode and ground is closed. If CAT2 has a
low voltage this switch is open. So in order to light the LEDs in the 7 -Segment display, CAT2=1. There
is another similar transistor for the upper digit that is controlled by the signal CAT1. Since the same
CPLD I/O Pins AA-AG are used for both digits, CAT1 should be low to prevent the upper digit from
lighting, or CAT1=0.

a
f

d
Figure 2: Seven Segment Display and Circuit

AA

AB
820O

AC
820O

CAT2
Off = 0
On = 1

AD
820O

AE
820O

AF
820O

AG
820O

820O

Figure 3: Seven Segment Display Circuit on the Development Board

(AA-AG and CAT2 are driven by CPLD output pins)

BCD to 7-Segment Display Truth Table

The BCD inputs should light the 7-Segment Display as shown in THE 7 -Segment Display Column
of Table 1 below. The output functions AA-AG have been partially filled in for you. You will need to
complete the truth table in procedure 2 below.

Table 1: BCD to 7-Segement Display Coding and Partial Truth Table

0
0
0
0
0
0
0
1
1
1
1
1
1

BCD Code 7-Segment

a3 a2 a1 a0 Display

0
0
0
0
0 1
1
1
1
1 0
0
0
0
1 1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

AA AB AC AD AE AF AG

1 1 1 1 1 1 0
0 1 1 0 0 0 0

Procedure
P1 Getting Started with VHDL for CPLDs tutorial
Perform the Getting Started with VHDL for CPLDs tutorial. You can find the tutorial on the website
listed under the Tutorials link.
P2 BCD to-7 Segment Decoder Design Project

1)

Design the least cost BCD-to-7 Segment Decoder. The cost function for the project is to first minimize the
number of gates needed and second to minimize the total number of gate inputs needed to implement the
function. Document the design procedure in your lab report including all of your design work . The design
work should include completing the partially specified truth table found above. Then you will have to find
a minimum cost Boolean expression for each of the functions AA-AG that drive segments on the 7Segment display. Include the minimum cost Boolean expressions in your lab report. Note any software you
may have used for the design such as (Reduce1, MEV Tutorial ...). Include your own comments on the
design process and discuss how designing the BCD-to-7 Segment Decoder using SSI gates would differ.

2) Enter your design using VHDL and the Xilinx ISE Design Environment. Copy your VHDL
source code to the clipboard and paste it into your lab report. Include your own comments on the
design entry process and discuss how wiring the decoder using SSI gates would differ.

3) Simulate your project. Document how you simulated your design, including any software you
used to help you build it (i.e. Xilinx ISE, ModelSim ...). Also include in your report the
simulation waveforms that you used to validate your design. You can copy the simulation
waveforms to the clipboard by pushing the Alternate-Print_Screen keys simultaneously while
the simulation waveform window is selected and pasting the results into your lab report. Include
your own comments on the simulation process. How does simulation compare to debugging
circuits built with SSI gates.

4) Build the BCD-to-7-Segment Decoder System using the Digilent XCR Development Board.
Include a system schematic with any switches, 7-Segment Displays, Resistors, Transistors, and the
CPLD pins used on the development board. On the schematic, you only need to indicate pin
numbers for the CPLD but not the pin numbers for the other components. Submit a copy of your
VHDL source code. Your VHDL source code should have sufficient comments so that a peer can
understand your design. Include in the report, your own comments on the construction of the
circuit.

5) Test your circuit. To verify your circuit create a truth table that lists all combinations of the BCD
input parameter (a3, a2, a1, and a0) and the corresponding display output . Your report should
include your test results.

Conclusions
Discuss what you have learned from this experiment.

Remember that each student must write an

individual summary and conclusion.