This document provides a summary of D.A. Navaneeth Reddy's qualifications for a VLSI design engineer position. It includes his contact information, education background with degrees in electronics and communication, relevant technical skills in hardware description languages, EDA tools, and programming languages. It also outlines internship experience in physical design using Synopsys tools and coursework covering digital design fundamentals. Project experience is described doing physical implementation of an SoC subsystem from RTL to GDSII layout as well as an academic project on a low power BCD adder design using majority gates.
This document provides a summary of D.A. Navaneeth Reddy's qualifications for a VLSI design engineer position. It includes his contact information, education background with degrees in electronics and communication, relevant technical skills in hardware description languages, EDA tools, and programming languages. It also outlines internship experience in physical design using Synopsys tools and coursework covering digital design fundamentals. Project experience is described doing physical implementation of an SoC subsystem from RTL to GDSII layout as well as an academic project on a low power BCD adder design using majority gates.
This document provides a summary of D.A. Navaneeth Reddy's qualifications for a VLSI design engineer position. It includes his contact information, education background with degrees in electronics and communication, relevant technical skills in hardware description languages, EDA tools, and programming languages. It also outlines internship experience in physical design using Synopsys tools and coursework covering digital design fundamentals. Project experience is described doing physical implementation of an SoC subsystem from RTL to GDSII layout as well as an academic project on a low power BCD adder design using majority gates.
This document provides a summary of D.A. Navaneeth Reddy's qualifications for a VLSI design engineer position. It includes his contact information, education background with degrees in electronics and communication, relevant technical skills in hardware description languages, EDA tools, and programming languages. It also outlines internship experience in physical design using Synopsys tools and coursework covering digital design fundamentals. Project experience is described doing physical implementation of an SoC subsystem from RTL to GDSII layout as well as an academic project on a low power BCD adder design using majority gates.
Physical Design Implementation (RTL netlist to GDS II) of SoC sub- system Physical Design Training
Type of service : Physical Design
Technology/Layer : 8nm/9 metal layer Number of Macros : 40 Complexicity : 52K Standard cells No. of Clock : 8 Frequency : 416 MHz Tool Used : Synopsys IC-Compiler, STAR RC, Prime Time Role Setting initial Floorplan, setting Powerplan to meet the power budget (IR drop analysis), Physical synthesis with timing and congestion driven placement, CTS to optimize clock skew and minimize clock latency and Routing. Also, it includes physical verification steps like DRC,LVS,ERC Also, analyzing timing re- port and fixing timing violations in Pre and Post- layout STA.
ACADEMIC PROJECT:(B.Tech)
Title: Low power BCD Adder by using majority gate.
Majority gate cmos technology has become one of the most attractive approaches for the development of the next generation ultra- dense low-power digital circuits. Total power dissipated in a cmos circuit is sum total of dynamic power, short circuit power and static or leakage power.design for low-power. The ability to reduce all the components of power consumption in cmos circuits during the development of a low power electronic product. Tools used: Tanner Tools.
STRENGTH
Active learning Positive Atitude, Hardworking
DECLARATION
I declare that all the information furnished above is factually correct and true to the best of my knowledge and belief.
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