K. Triveni is seeking employment as a VLSI engineer with skills in advanced digital design and physical design using Cadence tools. They have experience with floorplanning, placement and routing, timing analysis, and physical verification of designs up to 0.13um technology. They completed projects implementing timing-driven layout for blocks meeting timing and power constraints. K. Triveni also has experience with logic synthesis using RTL Compiler to optimize area, timing and power for counter designs up to 0.18um technology.
K. Triveni is seeking employment as a VLSI engineer with skills in advanced digital design and physical design using Cadence tools. They have experience with floorplanning, placement and routing, timing analysis, and physical verification of designs up to 0.13um technology. They completed projects implementing timing-driven layout for blocks meeting timing and power constraints. K. Triveni also has experience with logic synthesis using RTL Compiler to optimize area, timing and power for counter designs up to 0.18um technology.
K. Triveni is seeking employment as a VLSI engineer with skills in advanced digital design and physical design using Cadence tools. They have experience with floorplanning, placement and routing, timing analysis, and physical verification of designs up to 0.13um technology. They completed projects implementing timing-driven layout for blocks meeting timing and power constraints. K. Triveni also has experience with logic synthesis using RTL Compiler to optimize area, timing and power for counter designs up to 0.18um technology.
K. Triveni is seeking employment as a VLSI engineer with skills in advanced digital design and physical design using Cadence tools. They have experience with floorplanning, placement and routing, timing analysis, and physical verification of designs up to 0.13um technology. They completed projects implementing timing-driven layout for blocks meeting timing and power constraints. K. Triveni also has experience with logic synthesis using RTL Compiler to optimize area, timing and power for counter designs up to 0.18um technology.
VLSI enthusiastic having good understanding of Advanced digital design concept seeks employment to be part of the dynamic team that will allow me to further expand on these skills and contribute my best to the company
Professional Training
An Industry Oriented Trainee in VLSI PHYSICAL DESIGN from Institute of Silicon Systems (ISS). Hyderabad (Aug-2018 - Present) .
COURSE OUTLINE:
VLSI Fundamentals, CMOS Basics, Digital Design Floor Planning, Power Planning, Placement and Routing, clock tree synthesis, static timing analysis timing optimization, cross talk analysis, IR Drop Analysis and Physical Verification.
Tools:
Experience in physical design of 130nm and 180nm technologies using Cadence tool
Cadence Innovus–Floor Planning, Place & Route, and clock tree synthesis Tempus –Static Timing Analysis and Crosstalk Analysis Genus- Logic Synthesis Assura – Physical Verification
Performing sanity check, Design import , Floor Plan , Power Plan , Placement ,Trail Route, Power Analysis, RC Extract, Timing Analysis, IPO, CTS, Adding filler cells, Timing Analysis.
LOGIC SYNTHESIS
Project 1: COUNTER_16
Objective: Running Zero and Force Wire Load Model Synthesis by meeting Timing, optimizing Area and Power. Tools: Cadence Encounter RTL Compiler No. of Clocks: 2 Frequency: 200MHz Technology: TSMC 0.18 micron
Responsibilities:
Writing SDC, TCL Scripts, Extracting Timing, Optimizing Area, Timing and Power. Email: kokkera484@gmail.com K. Triveni Mobile: 8008477597
Project 2: COUNTER_32 Objective: Running Zero Wire Load Model Synthesis and to achieve Maximum possible frequency for different VTs. Tools: Cadence Encounter RTL Compiler No. of Clocks: 1 Frequency: 645MHz (RVT), 322MHz (HVT), 645MHz (MVT) Technology: TSMC 0.18 micron
