Skills: Objective: Programming languages: Recent Electrical Engineering graduate with a strong foundation in digital design and a passion for IC Python, System Verilog, C++ design. Seeking an entry-level position in IC design to leverage coursework, projects, and problem-solving skills in a dynamic and challenging environment. Tools: • . Studio, Perl- Code Composer Internship: based Unix System, IoT, ASIC Digital Intern Design Flow, Xilinx Vivado, ModelSim Texas Instruments May 2022 – July 2022 Data Analysis: ▪ Compiled and executed over 30 comprehensive test cases for regression testing on cloud-based Pandas, Shell Scripting, technologies, resulting in a 15% increase in system performance. Selenium, Numpy, Machine ▪ Developed a deep understanding of system environments on Perl-based Unix systems, optimizing learning performance and resolving nearly 12 complex issues. Circuit Design: ▪ Learned techniques of Analog circuits design from Alan Hastings videos and applied them in 5 analog PLL and DAC Architecture, projects to optimize circuit performance. ADC Optimization Education: Languages: Degree Institute Year CGPA / % English(Conversational), Hindi(Native) B.Tech in Electrical and NIT Calicut Kerala 2019 - 23 7.73 Electronics Engineering
Relevant Coursework: 12th Class (CBSE)
JNV Kottayam 2019 93.4 % Kerala ✓ Digital system Design ✓ Nanometer Technology JNV Kaimur 10th Class (CBSE) Bihar 2017 10 ✓ Architecture of Advanced processors ✓ Microelectronics Project Highlights: ✓ Embedded Systems DIGITAL Book Knowledge: A. Digital Traffic Light Controller (Course Project) ✓ Studied "Advanced VLSI ✓ Designed and implemented a digital traffic light controller using Verilog. ✓ Utilized finite state machines for efficient control and timing. Design" by Kang and ✓ Gained experience in RTL design, simulation, and verification. Leblebici, gaining insights into clock domain crossing B. Low-Power Design of a 4-Bit Adder (Course Project) techniques, low-power ✓ Implemented a 4-bit adder with power optimization techniques. design methodologies, and ✓ Reduced power consumption by 20% through clock gating and efficient logic design. signal integrity analysis. ✓ Acquired knowledge in C. UVM Verification of I2C protocol (Passion Project | May 2022) power optimization, ✓ Collaborated with a team of 4 to achieve the verification detail of the I2C protocol ✓ Constructed and successfully verified the I2C protocol using system verilog in EDA synthesis, and timing closure. A. Robust Alarm Clock Verification with Cadence Xcelium in EDA Playground Certificates: ✓ Verified a robust alarm clock design using Cadence Xcelium in EDA Playground. Exhaustively tested all system states to ensure flawless operation under diverse conditions. ✓Co-Author for the IEEE ✓ Proficient in System Verilog, employed its features effectively to create a comprehensive manuscript “Remaining testbench. Achieved extensive code coverage for thorough validation. Useful Life Estimation of Li-Ion Battery Using ML ✓ Contributed to quality assurance by meticulous testing, documenting results, edge cases, and Based Hybrid Model” verification methods on a widely-used EDA platform.
✓Attended webinar on “Applications of formal ANALOG verification “ conducted by IESA A. Precision Frequency Synthesizer for Wireless Communication Applications Passion Project | April 2022 ✓Qualified as Navodaya ✓ Designed and implemented a Precision Frequency Synthesizer Dakshana scholar program ✓ Combines a Phase-Locked Loop (PLL), Analog-to-Digital Converter (ADC), and Digital-to- during 10th Analog Converter (DAC) to generate stable and accurate radio frequencies. ✓ Improved signal-to-noise ratio by 20%, resulting in clearer and more accurate data transmission. ✓ Reduced power consumption by 15% through efficient signal processing, extending device battery life.
