MCP2561/2

High-Speed CAN Transceiver

Features: Description:
• Supports 1 Mb/s Operation The MCP2561/2 is a Microchip Technology Inc. second
• Implements ISO-11898-2 and ISO-11898-5  generation high-speed CAN transceiver. It serves as an
Standard Physical Layer Requirements interface between a CAN protocol controller and the
• Very Low Standby Current (5 µA, typical) physical two-wire CAN bus.
• VIO Supply Pin to Interface Directly to  The device meets the automotive requirements for
CAN Controllers and Microcontrollers with  high-speed (up to 1 Mb/s), low quiescent current,
1.8V to 5.5V I/O electromagnetic compatibility (EMC) and electrostatic
• SPLIT Output Pin to Stabilize Common Mode in discharge (ESD).
Biased Split Termination Schemes
Package Types
• CAN Bus Pins are Disconnected when Device is
Unpowered: MCP2561 MCP2562
- An Unpowered Node or Brown-Out Event will PDIP, SOIC PDIP, SOIC
Not Load the CAN Bus TXD 1 8 STBY TXD 1 8 STBY
• Detection of Ground Fault:
VSS 2 7 CANH VSS 2 7 CANH
- Permanent Dominant Detection on TXD
VDD 3 6 CANL VDD 3 6 CANL
- Permanent Dominant Detection on Bus RXD 4 5 SPLIT RXD 4 5 VIO
• Power-on Reset and Voltage Brown-Out
Protection on VDD Pin
MCP2561 MCP2562
• Protection Against Damage Due to Short-Circuit 3x3 DFN*
3x3 DFN*
Conditions (Positive or Negative Battery Voltage)
TXD 1 8 STBY TXD 1 8 STBY
• Protection Against High-Voltage Transients in
Automotive Environments VSS 2 EP 7 CANH VSS 2 EP 7 CANH
9 9
• Automatic Thermal Shutdown Protection VDD 3 6 CANL VDD 3 6 CANL

• Suitable for 12V and 24V Systems RXD 4 5 SPLIT RXD 4 5 VIO

• Meets or exceeds stringent automotive design

* Includes Exposed Thermal Pad (EP); see Table 1-2.
requirements including “Hardware Requirements
for LIN, CAN and FlexRay Interfaces in Automo-
tive Applications”, Version 1.3, May 2012
• High-Noise Immunity Due to Differential Bus
Implementation
• High Electrostatic Discharge (ESD) Protection on
CANH and CANL, meeting the IEC61000-4-2 up
to ±14 kV
• Available in PDIP-8L, SOIC-8L and 3x3 DFN-8L
• Temperature ranges:
- Extended (E): -40°C to +125°C
- High (H): -40°C to +150°C

MCP2561/2 Family Members

Device Feature Description
MCP2561 Split pin Common mode stabilization
MCP2562 VIO pin Internal level shifter on digital I/O pins
Note: For ordering information, see the “Product Identification System” section on page 27.

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MCP2561/2
Block Diagram
SPLIT(2) VIO(3) VDD

Digital I/O Thermal POR

VDD/2
Supply Protection UVLO

VIO

Permanent
TXD
Dominant Detect

Driver CANH
VIO and
Slope Control
CANL
Mode
STBY
Control

CANH
Wake-Up
LP_RX(1)
Filter
CANL

Receiver
RXD CANH
HS_RX
CANL

VSS
Note 1: There is only one receiver implemented. The receiver can operate in Low-Power or High-Speed mode.
2: Only MCP2561 has the SPLIT pin.
3: Only MCP2562 has the VIO pin. In MCP2561, the supply for the digital I/O is internally connected to VDD.

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 MCP2561/2
1.0 DEVICE OVERVIEW 1.1.1 NORMAL MODE
The MCP2561/2 is a high-speed CAN, fault-tolerant Normal mode is selected by applying a low-level to the
device that serves as the interface between a CAN STBY pin. The driver block is operational and can drive
protocol controller and the physical bus. The the bus pins. The slopes of the output signals on CANH
MCP2561/2 device provides differential transmit and and CANL are optimized to produce minimal
receive capability for the CAN protocol controller, and electromagnetic emissions (EME).
is fully compatible with the ISO-11898-2 and The high-speed differential receiver is active.
ISO-11898-5 standards. It will operate at speeds of up
to 1 Mb/s. 1.1.2 STANDBY MODE
Typically, each node in a CAN system must have a The device may be placed in Standby mode by
device to convert the digital signals generated by a applying a high-level to the STBY pin. In Standby
CAN controller to signals suitable for transmission over mode, the transmitter and the high-speed part of the
the bus cabling (differential output). It also provides a receiver are switched off to minimize power
buffer between the CAN controller and the high-voltage consumption. The low-power receiver and the wake-up
spikes that can be generated on the CAN bus by filter blocks are enabled in order to monitor the bus for
outside sources. activity. The receive pin (RXD) will show a delayed
representation of the CAN bus, due to the wake-up
1.1 Mode Control Block filter.
The CAN controller gets interrupted by a negative edge
The MCP2561/2 supports two modes of operation:
on the RXD pin (dominant state on the CAN bus). The
• Normal CAN controller must put the MCP2561/2 back into
• Standby Normal mode using the STBY pin, in order to enable
high-speed data communication.
These modes are summarized in Table 1-1.
The CAN bus wake-up function requires both supply
voltages, VDD and VIO, to be in valid range.

TABLE 1-1: MODES OF OPERATION

RXD Pin
Mode STBY Pin
LOW HIGH
Normal LOW Bus is dominant Bus is recessive
Standby HIGH Wake-up request is detected No wake-up request detected

1.2 Transmitter Function 1.4 Internal Protection

The CAN bus has two states: Dominant and CANH and CANL are protected against battery short-
Recessive. A Dominant state occurs when the circuits and electrical transients that can occur on the
differential voltage between CANH and CANL is CAN bus. This feature prevents destruction of the
greater than VDIFF(D)(I). A Recessive state occurs transmitter output stage during such a Fault condition.
when the differential voltage is less than VDIFF(R)(I). The device is further protected from excessive current
The Dominant and Recessive states correspond to the loading by thermal shutdown circuitry that disables the
Low and High state of the TXD input pin, respectively. output drivers when the junction temperature exceeds
However, a Dominant state initiated by another CAN a nominal limit of +175°C. All other parts of the chip
node will override a Recessive state on the CAN bus. remain operational, and the chip temperature is low-
ered due to the decreased power dissipation in the
1.3 Receiver Function transmitter outputs. This protection is essential to
protect against bus line short-circuit-induced damage.
In Normal mode, the RXD output pin reflects the differ-
ential bus voltage between CANH and CANL. The Low
and High states of the RXD output pin correspond to the
Dominant and Recessive states of the CAN bus,
respectively.

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MCP2561/2
1.5 Permanent Dominant Detection 1.6 Power-On Reset (POR) and 
The MCP2561/2 device prevents two conditions:
Undervoltage Detection
• Permanent dominant condition on TXD The MCP2561/2 has undervoltage detection on both
• Permanent dominant condition on the bus supply pins: VDD and VIO. Typical undervoltage
thresholds are 1.2V for VIO and 4V for VDD.
In Normal mode, if the MCP2561/2 detects an
extended Low state on the TXD input, it will disable the When the device is powered on, CANH and CANL
CANH and CANL output drivers in order to prevent the remain in a high-impedance state until both VDD and
corruption of data on the CAN bus. The drivers will VIO exceed their undervoltage levels. Once powered
remain disabled until TXD goes High. on, CANH and CANL will enter a high-impedance state
if the voltage level at VDD drops below the undervoltage
In Standby mode, if the MCP2561/2 detects an level, providing voltage brown-out protection during
extended dominant condition on the bus, it will set the normal operation.
RXD pin to Recessive state. This allows the attached
controller to go to Low-Power mode until the dominant In Normal mode, the receiver output is forced to
issue is corrected. RXD is latched High until a Recessive state during an undervoltage condition on
Recessive state is detected on the bus, and the VDD. In Standby mode, the low-power receiver is only
wake-up function is enabled again. enabled when both VDD and VIO supply voltages rise
above their respective undervoltage thresholds. Once
Both conditions have a time-out of 1.25 ms (typical). these threshold voltages are reached, the low-power
This implies a maximum bit time of 69.44 µs receiver is no longer controlled by the POR comparator
(14.4 kHz), allowing up to 18 consecutive dominant bits and remains operational down to about 2.5V on the
on the bus. VDD supply (MCP2561/2). The MCP2562 transfers
data to the RXD pin down to 1.8V on the VIO supply.

1.7 Pin Descriptions

Table 1-2 describes the pinout.

TABLE 1-2: MCP2561/2 PINOUT

MCP2561 MCP2561 MCP2562 MCP2562
Symbol Pin Function
3x3 DFN PDIP, SOIC 3x3 DFN PDIP, SOIC
1 1 1 1 TXD Transmit Data Input
2 2 2 2 VSS Ground
3 3 3 3 VDD Supply Voltage
4 4 4 4 RXD Receive Data Output
5 5 — — SPLIT Common Mode Stabilization – MCP2561 only
— — 5 5 VIO Digital I/O Supply Pin – MCP2562 only
6 6 6 6 CANL CAN Low-Level Voltage I/O
7 7 7 7 CANH CAN High-Level Voltage I/O
8 8 8 8 STBY Standby Mode Input
9 — 9 — EP Exposed Thermal Pad

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 MCP2561/2
1.7.1 TRANSMITTER DATA  1.7.9 STANDBY MODE INPUT PIN (STBY)
INPUT PIN (TXD) This pin selects between Normal or Standby mode. In
The CAN transceiver drives the differential output pins Standby mode, the transmitter, high speed receiver and
CANH and CANL according to TXD. It is usually SPLIT are turned off, only the low power receiver and
connected to the transmitter data output of the CAN wake-up filter are active. STBY is connected to an
controller device. When TXD is Low, CANH and CANL internal MOS pull-up resistor to VDD or VIO, in the
are in the Dominant state. When TXD is High, CANH MCP2561 or MCP2562, respectively. The value of the
and CANL are in the Recessive state, provided that MOS pull-up resistor depends on the supply voltage.
another CAN node is not driving the CAN bus with a Typical values are 660 k for 5V, 1.1 M for 3.3V and
Dominant state. TXD is connected to an internal pull-up 4.4 M for 1.8V
resistor (nominal 33 k) to VDD or VIO, in the MCP2561
or MCP2562, respectively. 1.7.10 EXPOSED THERMAL PAD (EP)
It is recommended to connect this pad to VSS to
1.7.2 GROUND SUPPLY PIN (VSS) enhance electromagnetic immunity and thermal
Ground supply pin. resistance.

1.7.3 SUPPLY VOLTAGE PIN (VDD)

Positive supply voltage pin. Supplies transmitter and
receiver, including the wake-up receiver.

1.7.4 RECEIVER DATA 

OUTPUT PIN (RXD)
RXD is a CMOS-compatible output that drives High or
Low depending on the differential signals on the CANH
and CANL pins, and is usually connected to the
receiver data input of the CAN controller device. RXD is
High when the CAN bus is Recessive, and Low in the
Dominant state. RXD is supplied by VDD or VIO, in the
MCP2561 or MCP2562, respectively.

1.7.5 SPLIT PIN (MCP2561 ONLY)

Reference Voltage Output (defined as VDD/2). The pin
is only active in Normal mode. In Standby mode, or
when VDD is off, SPLIT floats.

1.7.6 VIO PIN (MCP2562 ONLY)

Supply for digital I/O pins. In the MCP2561, the supply
for the digital I/O (TXD, RXD and STBY) is internally
connected to VDD.

1.7.7 CAN LOW PIN (CANL)

The CANL output drives the Low side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANL disconnects from the
bus when MCP2561/2 is not powered.

1.7.8 CAN HIGH PIN (CANH)

The CANH output drives the high-side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANH disconnects from the
bus when MCP2561/2 is not powered.

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MCP2561/2
1.8 Typical Applications

FIGURE 1-1: MCP2561 WITH SPLIT PIN

VBAT
5V LDO
0.1 μF

VDD VDD CANH

CANH
CANTX TXD

MCP2561
60:
PIC® 300:
CANRX RXD SPLIT
MCU 4700 pF
RBX STBY Optional(1) 60: CANL
VSS VSS CANL

Note 1: Optional resistor to allow communication during bus failure (CANL shorted to ground).

FIGURE 1-2: MCP2562 WITH VIO PIN

VBAT
5V LDO

1.8V LDO
0.1 μF 0.1 μF

VDD VIO VDD CANH

CANTX TXD CANH
MCP2562

PIC®
CANRX RXD 120:
MCU
RBX STBY
CANL
VSS Vss CANL

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 MCP2561/2
2.0 ELECTRICAL 2.1.5 DIFFERENTIAL VOLTAGE, VDIFF 
CHARACTERISTICS (OF CAN BUS)
Differential voltage of the two-wire CAN bus, value
2.1 Terms and Definitions VDIFF = VCANH – VCANL.

A number of terms are defined in ISO-11898 that are 2.1.6 INTERNAL CAPACITANCE, CIN 
used to describe the electrical characteristics of a CAN (OF A CAN NODE)
transceiver device. These terms and definitions are
Capacitance seen between CANL (or CANH) and
summarized in this section.
ground during the Recessive state, when the CAN
2.1.1 BUS VOLTAGE node is disconnected from the bus (see Figure 2-1).

VCANL and VCANH denote the voltages of the bus line 2.1.7 INTERNAL RESISTANCE, RIN 
wires CANL and CANH relative to ground of each (OF A CAN NODE)
individual CAN node.
Resistance seen between CANL (or CANH) and
2.1.2 COMMON MODE BUS VOLTAGE ground during the Recessive state, when the CAN
RANGE node is disconnected from the bus (see Figure 2-1).

Boundary voltage levels of VCANL and VCANH with

FIGURE 2-1: PHYSICAL LAYER
respect to ground, for which proper operation will occur,
DEFINITIONS
if up to the maximum number of CAN nodes are
connected to the bus.
ECU
2.1.3 DIFFERENTIAL INTERNAL
CAPACITANCE, CDIFF  RIN
(OF A CAN NODE) CANL
Capacitance seen between CANL and CANH during RDIFF CDIFF
the Recessive state, when the CAN node is RIN
disconnected from the bus (see Figure 2-1). CANH
CIN CIN
2.1.4 DIFFERENTIAL INTERNAL GROUND
RESISTANCE, RDIFF 
(OF A CAN NODE)
Resistance seen between CANL and CANH during the
Recessive state when the CAN node is disconnected
from the bus (see Figure 2-1).

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MCP2561/2
Absolute Maximum Ratings†
VDD .............................................................................................................................................................................7.0V
VIO ..............................................................................................................................................................................7.0V
DC Voltage at TXD, RXD, STBY and VSS .............................................................................................-0.3V to VIO + 0.3V
DC Voltage at CANH, CANL and SPLIT ...................................................................................................... -58V to +58V
Transient Voltage on CANH, CANL (ISO-7637) (Figure 2-5) ................................................................... -150V to +100V
Storage temperature ...............................................................................................................................-55°C to +150°C
Operating ambient temperature ..............................................................................................................-40°C to +150°C
Virtual Junction Temperature, TVJ (IEC60747-1) ....................................................................................-40°C to +190°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection on CANH and CANL pins for MCP2561 (IEC 61000-4-2).............................................................±14 kV
ESD protection on CANH and CANL pins for MCP2562 (IEC 61000-4-2)...............................................................±8 kV
ESD protection on CANH and CANL pins (IEC 801; Human Body Model)..............................................................±8 kV
ESD protection on all other pins (IEC 801; Human Body Model).............................................................................±4 kV
ESD protection on all pins (IEC 801; Machine Model) ............................................................................................±300V
ESD protection on all pins (IEC 801; Charge Device Model) ..................................................................................±750V

† NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.

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 MCP2561/2
2.2 DC Characteristics
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C; 
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60; unless otherwise specified.
Characteristic Sym. Min. Typ. Max. Units Conditions
SUPPLY
VDD Pin
Voltage Range VDD 4.5 — 5.5
Supply Current IDD — 5 10 mA Recessive; VTXD = VDD
— 45 70 Dominant; VTXD = 0V
Standby Current IDDS — 5 15 µA MCP2561
— 5 15 MCP2562; Includes IIO
High Level of the POR  VPORH 3.8 — 4.3 V
Comparator
Low Level of the POR  VPORL 3.4 — 4.0 V
Comparator
Hysteresis of POR  VPORD 0.3 — 0.8 V
Comparator
VIO Pin
Digital Supply Voltage Range VIO 1.8 — 5.5 V
Supply Current on VIO IIO — 4 30 µA Recessive; VTXD = VIO
— 85 500 Dominant; VTXD = 0V
Standby Current IDDS — 0.3 1 µA (Note 1)
Undervoltage detection on VIO VUVD(IO) — 1.2 — V (Note 1)
BUS LINE (CANH; CANL) TRANSMITTER
CANH; CANL:  VO(R) 2.0 0.5VDD 3.0 V VTXD = VDD; No load
Recessive Bus Output Voltage
CANH; CANL:  VO(S) -0.1 0.0 +0.1 V STBY = VTXD = VDD; No load
Bus Output Voltage in Standby
Recessive Output Current IO(R) -5 — +5 mA -24V < VCAN < +24V
CANH: Dominant  VO(D) 2.75 3.50 4.50 V TXD = 0; RL = 50 to 65
Output Voltage
CANL: Dominant  0.50 1.50 2.25 RL = 50 to 65
Output Voltage
Symmetry of Dominant  VO(D)(M) -400 0 +400 mV VTXD = VSS (Note 1)
Output Voltage
(VDD – VCANH – VCANL)
Dominant: Differential  VO(DIFF) 1.5 2.0 3.0 V VTXD = VSS; RL = 50 to 65
Output Voltage Figure 2-2, Figure 2-4
Recessive:  -120 0 12 mV VTXD = VDD
Differential Output Voltage Figure 2-2, Figure 2-4
-500 0 50 mV VTXD = VDD,no load.
Figure 2-2, Figure 2-4
Note 1: Characterized; not 100% tested.
2: Only MCP2562 has VIO pin. For the MCP2561, VIO is internally connected to VDD.
3: -12V to 12V is ensured by characterization, tested from -2V to 7V.

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MCP2561/2
2.2 DC Characteristics (Continued)
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C; 
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60; unless otherwise specified.
Characteristic Sym. Min. Typ. Max. Units Conditions
CANH: Short Circuit  IO(SC) -120 -85 — mA VTXD = VSS; VCANH = 0V;
Output Current CANL: floating
-100 — — mA same as above, but
VDD=5V, TAMB = +25°C (Note 1)
CANL: Short Circuit  — 75 +120 mA VTXD = VSS; VCANL = 18V;
Output Current CANH: floating
— — +100 mA same as above, but
VDD=5V, TAMB = +25°C (Note 1)
BUS LINE (CANH; CANL) RECEIVER
Recessive Differential  VDIFF(R)(I) -1.0 — +0.5 V Normal Mode;
Input Voltage -12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
-1.0 — +0.4 Standby Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
Dominant Differential  VDIFF(D)(I) 0.9 — VDD V Normal Mode;
Input Voltage -12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
1.0 — VDD Standby Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
Differential  VTH(DIFF) 0.5 0.7 0.9 V Normal Mode;
Receiver Threshold -12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
0.4 — 1.15 Standby Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
Differential  VHYS(DIFF) 50 — 200 mV Normal mode, see Figure 2-6,
Input Hysteresis (Note 1)
Common Mode  RIN 10 — 30 k (Note 1)
Input Resistance
Common Mode  RIN(M) -1 0 +1 % VCANH = VCANL, (Note 1)
Resistance Matching
Differential Input  RIN(DIFF) 10 — 100 k (Note 1)
Resistance
Common Mode  CIN(CM) — — 20 pF VTXD = VDD; (Note 1)
Input Capacitance
Differential  CIN(DIFF) — — 10 VTXD = VDD; (Note 1)
Input Capacitance
CANH, CANL:  ILI -5 — +5 µA VDD = VTXD = VSTBY = 0V.
Input Leakage For MCP2562, VIO = 0V.
VCANH = VCANL = 5 V.
Note 1: Characterized; not 100% tested.
2: Only MCP2562 has VIO pin. For the MCP2561, VIO is internally connected to VDD.
3: -12V to 12V is ensured by characterization, tested from -2V to 7V.

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 MCP2561/2
2.2 DC Characteristics (Continued)
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C; 
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60; unless otherwise specified.
Characteristic Sym. Min. Typ. Max. Units Conditions
COMMON MODE STABILIZATION OUTPUT (SPLIT)
Output Voltage Vo 0.3VDD 0.5VDD 0.7VDD V Normal mode; 
ISPLIT = -500 µA to +500 µA
0.45VDD 0.5VDD 0.55VDD V Normal mode; RL  1 M
Leakage Current IL -5 — +5 µA Standby mode; 
VSPLIT = -24V to + 24V 
(ISO 11898: -12V ~ +12V)
DIGITAL INPUT PINS (TXD, STBY)
High-Level Input Voltage VIH 0.7VIO — VIO + 0.3 V
Low-Level Input Voltage VIL -0.3 — 0.3VIO V
High-Level Input Current IIH -1 — +1 µA
TXD: Low-Level Input Current IIL(TXD) -270 -150 -30 µA
STBY: Low-Level Input Current IIL(STBY) -30 — -1 µA
RECEIVE DATA (RXD) OUTPUT
High-Level Output Voltage VOH VDD - 0.4 — — V IOH = -2 mA (MCP2561); typical
-4 mA
VIO - 0.4 — — IOH = -1 mA (MCP2562); typical
-2 mA
Low-Level Output Voltage VOL — — 0.4 V IOL = 4 mA; typical 8 mA
THERMAL SHUTDOWN
Shutdown  TJ(SD) 165 175 185 °C -12V < V(CANH, CANL) < +12V,
Junction Temperature (Note 1)
Shutdown  TJ(HYST) 20 — 30 °C -12V < V(CANH, CANL) < +12V,
Temperature Hysteresis (Note 1)
Note 1: Characterized; not 100% tested.
2: Only MCP2562 has VIO pin. For the MCP2561, VIO is internally connected to VDD.
3: -12V to 12V is ensured by characterization, tested from -2V to 7V.

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MCP2561/2
FIGURE 2-2: PHYSICAL BIT REPRESENTATION AND SIMPLIFIED BIAS IMPLEMENTATION

Normal Mode Standby Mode

CANH
CANH, CANL, SPLIT

SPLIT SPLIT
floating

CANL

Recessive Dominant Recessive

Time

VDD

CANH

VDD/2 Normal RXD

Standby
Mode
CANL

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 MCP2561/2
2.3 AC Characteristics
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C; 
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60; unless otherwise specified.
Param.
Sym. Characteristic Min. Typ. Max. Units Conditions
No.
1 tBIT Bit Time 1 — 69.44 µs
2 fBIT Bit Frequency 14.4 — 1000 kHz
3 tTXD-BUSON Delay TXD Low to Bus Dominant — — 70 ns
4 tTXD-BUSOFF Delay TXD High to Bus Recessive — — 125 ns
5 tBUSON-RXD Delay Bus Dominant to RXD — — 70 ns
6 tBUSOFF-RXD Delay Bus Recessive to RXD — — 110 ns
7 tTXD - RXD Propagation Delay TXD to RXD — — 125 ns Negative edge on TXD
8 — — 235 Positive edge on TXD
9 tFLTR(WAKE) Delay Bus Dominant to RXD  0.5 1 4 µs Standby mode
(Standby mode)
10 tWAKE Delay Standby  5 25 40 µs Negative edge on STBY
to Normal Mode
11 tPDT Permanent Dominant Detect Time — 1.25 — ms TXD = 0V
12 tPDTR Permanent Dominant Timer Reset — 100 — ns The shortest recessive
pulse on TXD or CAN bus
to reset Permanent
Dominant Timer

FIGURE 2-3: TEST LOAD CONDITIONS

Load Condition 1 Load Condition 2

VDD/2

RL

CL CL
Pin Pin
RL = 464 
CL = 50 pF for all digital pins VSS VSS

FIGURE 2-4: TEST CIRCUIT FOR ELECTRICAL CHARACTERISTICS

VDD 0.1 µF

CANH
TXD

SPLIT CAN RL 100 pF

Transceiver
RXD
30 pF CANL
GND STBY

Note: On MCP2562, VIO is connected to VDD.

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MCP2561/2
FIGURE 2-5: TEST CIRCUIT FOR AUTOMOTIVE TRANSIENTS
CANH 1000 pF
TXD

SPLIT CAN Transient

RL
Transceiver Generator
RXD
CANL 1000 pF
GND STBY
Note: On MCP2562, VIO is connected to VDD.

The wave forms of the applied transients shall be in accordance

with ISO-7637, Part 1, test pulses 1, 2, 3a and 3b.

FIGURE 2-6: HYSTERESIS OF THE RECEIVER

RXD (receive data

VOH
output voltage)
VDIFF (r)(i) VDIFF (d)(i)

VOL

VDIFF (h)(i)

0.5 VDIFF (V) 0.9

DS20005167C-page 14  2013-2014 Microchip Technology Inc.

 MCP2561/2
2.4 Timing Diagrams and
Specifications

FIGURE 2-7: TIMING DIAGRAM FOR AC CHARACTERISTICS

VDD
TXD (transmit data
input voltage)
0V

VDIFF (CANH,
CANL differential
voltage)

RXD (receive data

output voltage) 3
5
7 4 6
8

FIGURE 2-8: TIMING DIAGRAM FOR WAKE-UP FROM STANDBY

VSTBY VDD
Input Voltage

0V
VDD/2
VCANH/VCANL

VTXD = VDD 10

FIGURE 2-9: PERMANENT DOMINANT TIMER RESET DETECT

Minimum pulse width until CAN bus goes to dominant after the falling edge

TXD

VDIFF (VCANH-VCANL)
Driver is off

11 12

 2013-2014 Microchip Technology Inc. DS20005167C-page 15

MCP2561/2
2.5 Thermal Specifications
Parameter Symbol Min. Typ. Max. Units Test Conditions
Temperature Ranges
Specified Temperature Range TA -40 — +125 C
-40 — +150
Operating Temperature Range TA -40 — +150 C
Storage Temperature Range TA -65 — +155 C
Thermal Package Resistances
Thermal Resistance, 8L-DFN 3x3 JA — 56.7 — C/W
Thermal Resistance, 8L-PDIP JA — 89.3 — C/W
Thermal Resistance, 8L-SOIC JA — 149.5 — C/W

DS20005167C-page 16  2013-2014 Microchip Technology Inc.

 MCP2561/2
3.0 PACKAGING INFORMATION
3.1 Package Marking Information

8-Lead DFN (3x3 mm) Example:

Part Number Code
MCP2561-E/MF DADR
MCP2561T-E/MF DADR DADR
MCP2561-H/MF DADS 1326
256
MCP2561T-H/MF DADS
MCP2562-E/MF DADU
MCP2562T-E/MF DADU
MCP2562-H/MF DADT
MCP2562T-H/MF DADT

8-Lead PDIP (300 mil) Example:

XXXXXXXX MCP2561 MCP2561

XXXXXNNN E/P e^^256
3
OR
H/P e^^256
3

1307 1307
YYWW
8-Lead PDIP (300 mil) Example:

8-Lead SOIC (150 mil) Example:

MCP2561E MCP2561H
SN e^^1246
3 OR SN e^^1246
3
256 256
NNN

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator (e3)
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2013-2014 Microchip Technology Inc. DS20005167C-page 17

MCP2561/2

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20005167C-page 18  2013-2014 Microchip Technology Inc.

 MCP2561/2

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2013-2014 Microchip Technology Inc. DS20005167C-page 19

MCP2561/2

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20005167C-page 20  2013-2014 Microchip Technology Inc.

 MCP2561/2


 
  
  
 3
&'
!&" &4# *!(!!&
4%&

&#&
&&255***'

'54

NOTE 1
E1

1 2 3

D
E

A A2

A1 L
c

e
b1 eB
b

6&! 7,8.
'!
9'&! 7 7: ;
7"') 
%! 7 <
&  1,

&
&  = = 

##4 4!!   - 
1!&
&   = =

"# &

"# >#& .  - -

##4>#& .   <
:  9&  -< -? 
&
& 9  - 
9# 4!!  <  
6 9#>#& )  ? 
9
* 9#>#& )  < 
:  
*+ 1 = = -

  !"#$%&" '  ()"&'"!&)
&#*&&&# 
 +%&, & !&
- '!
!#.#

&"#'
#%!

& "!
!
#%!

& "!
!!
&$#/ !#
 '!
#&
  .0
1,21!'!
 
&$& "!
**&
"&&
 !


 

  * ,<1

 2013-2014 Microchip Technology Inc. DS20005167C-page 21

MCP2561/2

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20005167C-page 22  2013-2014 Microchip Technology Inc.

 MCP2561/2

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2013-2014 Microchip Technology Inc. DS20005167C-page 23

MCP2561/2


  

!
 ""#$%& !'
 3
&'
!&" &4# *!(!!&
4%&

&#&
&&255***'

'54

DS20005167C-page 24  2013-2014 Microchip Technology Inc.

 MCP2561/2
APPENDIX A: REVISION HISTORY

Revision C (July 2014)

The following is the list of modifications:
1. Added references to ISO-11898-2 throughout
the document.
2. Updated Section 1.1.2 “Standby Mode”.
Described transition from Standby to Normal
mode. Emphasized that wake-up on CAN bus
requires both VDD and VIO.
3. Explained that POR and Brown-out are limited
to VDD pin in Section 1.6 “Power-On Reset
(POR) and Undervoltage Detection”.
4. Updated Section 2.2 “DC Characteristics”.
Clarified RL, added CANH/CANL Short Circuit
specification for 5V and room temperature.
5. Minor typographical corrections.

Revision B (March 2013)

• Updated the MCP2561/2 Family Members table
on page 1.

Revision A (March 2013)

• Original Release of this Document.

 2013-2014 Microchip Technology Inc. DS20005167C-page 25

MCP2561/2
NOTES:

DS20005167C-page 26  2013-2014 Microchip Technology Inc.

 MCP2561/2
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. -X /XX
Examples:
Device Temperature Package a) MCP2561-E/MF: Extended Temperature,
Range 8LD 3x3 DFN package
b) MCP2561T-E/MF: Tape and Reel,
Extended Temperature,
Device: MCP2561: High-Speed CAN Transceiver with SPLIT
8LD 3x3 DFN package
MCP2561T: High-Speed CAN Transceiver with SPLIT
(Tape and Reel) (DFN and SOIC only) c) MCP2561-E/P: Extended Temperature,
MCP2562: High-Speed CAN Transceiver with VIO 8LD PDIP package
MCP2562T: High-Speed CAN Transceiver with VIO d) MCP2561-E/SN: Extended Temperature,
(Tape and Reel) (DFN and SOIC only) 8LD SOIC package
e) MCP2561T-E/SN: Tape and Reel,
Extended Temperature,
Temperature E = -40°C to +125°C (Extended) 8LD SOIC package
Range: H = -40°C to +150°C (High)
a) MCP2561-H/MF: High Temperature,
Package: MF = Plastic Dual Flat, No Lead Package - 3x3x0.9 mm 8LD 3x3 DFN package
Body, 8-lead b) MCP2561T-H/MF: Tape and Reel,
P = Plastic Dual In-Line - 300 mil Body, 8-lead High Temperature,
SN = Plastic Small Outline - Narrow, 3.90 mm Body,  8LD 3x3 DFN package
8-lead c) MCP2561-H/P: High Temperature,
8LD PDIP package
d) MCP2561-H/SN: High Temperature,
8LD SOIC package
e) MCP2561T-H/SN:Tape and Reel,
High Temperature,
8LD SOIC package

 2013-2014 Microchip Technology Inc. DS20005167C-page 27

MCP2561/2
NOTES:

DS20005167C-page 28  2013-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
ensure that your application meets with your specifications.
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
MICROCHIP MAKES NO REPRESENTATIONS OR
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
SST, SST Logo, SuperFlash and UNI/O are registered
IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the
OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-378-5

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures

== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2013-2014 Microchip Technology Inc. DS20005167C-page 29

 Worldwide Sales and Service
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DS20005167C-page 30  2013-2014 Microchip Technology Inc.