1923816

TJA1042
High-speed CAN transceiver with Standby mode

Rev. 8 — 15 January 2015 Product data sheet
1. General description
The TJA1042 high-speed CAN transceiver provides an interface between a Controller
Area Network (CAN) protocol controller and the physical two-wire CAN bus. The
transceiver is designed for high-speed CAN applications in the automotive industry,
providing the differential transmit and receive capability to (a microcontroller with) a CAN
protocol controller.
The TJA1042 belongs to the third generation of high-speed CAN transceivers from NXP
Semiconductors, offering significant improvements over first- and second-generation
devices such as the TJA1040. It offers improved ElectroMagnetic Compatibility (EMC)
and ElectroStatic Discharge (ESD) performance, and also features:
• Ideal passive behavior to the CAN bus when the supply voltage is off
• A very low-current Standby mode with bus wake-up capability
• TJA1042T/3 and TJA1042TK/3 can be interfaced directly to microcontrollers with
supply voltages from 3 V to 5 V
The TJA1042 implements the CAN physical layer as defined in the current ISO11898
standard (ISO11898-2:2003, ISO11898-5:2007). Pending the release of the updated
version of ISO11898-2 including CAN FD, additional timing parameters defining loop
delay symmetry are specified. This implementation enables reliable communication in the
CAN FD fast phase at data rates up to 2 Mbit/s.
These features make the TJA1042 an excellent choice for all types of HS-CAN networks,
in nodes that require a low-power mode with wake-up capability via the CAN bus.
2. Features and benefits
2.1 General
 Fully ISO 11898-2:2003 and ISO 11898-5:2007 compliant
 Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
 Suitable for 12 V and 24 V systems
 Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)
 VIO input on TJA1042T/3 and TJA1042TK/3 allows for direct interfacing with 3 V to 5 V
microcontrollers
 SPLIT voltage output on TJA1042T for stabilizing the recessive bus level
 Available in SO8 package and leadless HVSON8 package (3.0 mm  3.0 mm) with
improved Automated Optical Inspection (AOI) capability
NXP Semiconductors TJA1042
 Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
 AEC-Q100 qualified
2.2 Predictable and fail-safe behavior

 Very low-current Standby mode with host and bus wake-up capability
 Functional behavior predictable under all supply conditions
 Transceiver disengages from the bus when not powered up (zero load)
 Transmit Data (TXD) dominant time-out function
 Bus-dominant time-out function in Standby mode
 Undervoltage detection on pins VCC and VIO
2.3 Protections
 High ESD handling capability on the bus pins (8 kV)
 High voltage robustness on CAN pins (58 V)
 Bus pins protected against transients in automotive environments
 Thermally protected
3. Quick reference data

Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 4.5 - 5.5 V
VIO supply voltage on pin VIO 2.8 - 5.5 V
Vuvd(VCC) undervoltage detection voltage 3.5 - 4.5 V
on pin VCC
Vuvd(VIO) undervoltage detection voltage 1.3 2.0 2.7 V
on pin VIO
ICC supply current Standby mode - 10 15 A
Normal mode; bus recessive 2.5 5 10 mA
Normal mode; bus dominant 20 45 70 mA
IIO supply current on pin VIO Standby mode; VTXD = VIO 5 - 14 A
Normal mode
recessive; VTXD = VIO 15 80 200 A
dominant; VTXD = 0 V - 350 1000 A
VESD electrostatic discharge voltage IEC 61000-4-2 at pins CANH and CANL 8 - +8 kV
VCANH voltage on pin CANH 58 - +58 V
VCANL voltage on pin CANL 58 - +58 V
Tvj virtual junction temperature 40 - +150 C
TJA1042 All information provided in this document is subject to legal disclaimers. © NXP N.V. 2015. All rights reserved.
Product data sheet Rev. 8 — 15 January 2015 2 of 23

4. Ordering information
Table 2. Ordering information
Type number[1] Package
Name Description Version
TJA1042T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
TJA1042T/3 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
TJA1042TK/3 HVSON8 plastic thermal enhanced very thin small outline package; no leads; SOT782-1
8 terminals; body 3  3  0.85 mm
[1] TJA1042T with SPLIT pin; TJA1042T/3 and TJA1042TK/3 with VIO pin.
5. Block diagram
VIO VCC
5 3
VCC TJA1042
TEMPERATURE
PROTECTION
VIO(1) 7
CANH
SLOPE
CONTROL
AND
1 TIME-OUT 6
TXD DRIVER CANL
VIO(1)
MODE 5
8 CONTROL SPLIT SPLIT(1)
STB
4
RXD
MUX
AND
DRIVER
WAKE-UP
FILTER
015aaa017
GND
(1) In a transceiver with a SPLIT pin, the VIO input is internally connected to VCC.
Fig 1. Block diagram

6. Pinning information
6.1 Pinning
terminal 1
TJA1042TK/3
7-$7 7-$7
index area
7;' 67% 7;' 67% TXD 1 8 STB
GND 2 7 CANH
*1' &$1+ *1' &$1+
VCC 3 6 CANL
9&& &$1/ 9&& &$1/ RXD VIO
4 5
5;' 63/,7 5;' 9,2
015aaa239
DDD DDD Transparent top view
a. TJA1042T: SO8 b. TJA1042T/3: SO8 c. TJA1042TK/3: HVSON8

Fig 2. Pin configuration diagrams
6.2 Pin description

Table 3. Pin description
Symbol Pin Description
TXD 1 transmit data input
GND 2[1] ground supply
VCC 3 supply voltage
RXD 4 receive data output; reads out data from the bus lines
SPLIT 5 common-mode stabilization output; in TJA1042T version only
VIO 5 supply voltage for I/O level adapter; in TJA1042T/3 and TJA1042TK/3 versions
only
CANL 6 LOW-level CAN bus line
CANH 7 HIGH-level CAN bus line
STB 8 Standby mode control input
[1] For enhanced thermal and electrical performance, the exposed center pad of the HVSON8 package should
be soldered to board ground.

7. Functional description
The TJA1042 is a HS-CAN stand-alone transceiver with Standby mode. It combines the
functionality of the PCA82C250, PCA82C251 and TJA1040 transceivers with improved
EMC and ESD handling capability and quiescent current performance. Improved slope
control and high DC handling capability on the bus pins provide additional application
flexibility.
The TJA1042 is available in two versions, distinguished only by the function of pin 5:
• The TJA1042T is backwards compatible with the TJA1040 when used with a 5 V
microcontroller, and also covers existing PCA82C250 and PCA82C251 applications
• The TJA1042T/3 and TJA1042TK/3 allow for direct interfacing to microcontrollers with
supply voltages down to 3 V
7.1 Operating modes

The TJA1042 supports two operating modes, Normal and Standby, which are selected via
pin STB. See Table 4 for a description of the operating modes under normal supply
conditions.
Table 4. Operating modes

Mode Pin STB Pin RXD
LOW HIGH
Normal LOW bus dominant bus recessive
Standby HIGH wake-up request no wake-up request
detected detected
7.1.1 Normal mode

A LOW level on pin STB selects Normal mode. In this mode, the transceiver can transmit
and receive data via the bus lines CANH and CANL (see Figure 1 for the block diagram).
The differential receiver converts the analog data on the bus lines into digital data which is
output to pin RXD. The slopes of the output signals on the bus lines are controlled
internally and are optimized in a way that guarantees the lowest possible EME.
7.1.2 Standby mode

A HIGH level on pin STB selects Standby mode. In Standby mode, the transceiver is not
able to transmit or correctly receive data via the bus lines. The transmitter and
Normal-mode receiver blocks are switched off to reduce supply current, and only a
low-power differential receiver monitors the bus lines for activity. The wake-up filter on the
output of the low-power receiver does not latch bus dominant states, but ensures that only
bus dominant and bus recessive states that persist longer than tfltr(wake)bus are reflected on
pin RXD.
In Standby mode, the bus lines are biased to ground to minimize the system supply
current. The low-power receiver is supplied by VIO, and is capable of detecting CAN bus
activity even if VIO is the only supply voltage available. When pin RXD goes LOW to signal
a wake-up request, a transition to Normal mode will not be triggered until STB is forced
LOW.

7.2 Fail-safe features
7.2.1 TXD dominant time-out function

A ‘TXD dominant time-out’ timer is started when pin TXD is set LOW. If the LOW state on
pin TXD persists for longer than tto(dom)TXD, the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD is set to HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 40 kbit/s.
7.2.2 Bus dominant time-out function

In Standby mode a 'bus dominant time-out' timer is started when the CAN bus changes
from recessive to dominant state. If the dominant state on the bus persists for longer than
tto(dom)bus, the RXD pin is reset to HIGH. This function prevents a clamped dominant bus
(due to a bus short-circuit or a failure in one of the other nodes on the network) from
generating a permanent wake-up request. The bus dominant time-out timer is reset when
the CAN bus changes from dominant to recessive state.
7.2.3 Internal biasing of TXD and STB input pins

Pins TXD and STB have internal pull-ups to VIO to ensure a safe, defined state in case
one or both of these pins are left floating. Pull-up currents flow in these pins in all states;
both pins should be held HIGH in Standby mode to minimize standby current.
7.2.4 Undervoltage detection on pins VCC and VIO

Should VCC drop below the VCC undervoltage detection level, Vuvd(VCC), the transceiver
will switch to Standby mode. The logic state of pin STB will be ignored until VCC has
recovered.
Should VIO drop below the VIO undervoltage detection level, Vuvd(VIO), the transceiver will
switch off and disengage from the bus (zero load) until VIO has recovered.
7.2.5 Overtemperature protection

The output drivers are protected against overtemperature conditions. If the virtual junction
temperature exceeds the shutdown junction temperature, Tj(sd), the output drivers will be
disabled until the virtual junction temperature falls below Tj(sd) and TXD becomes
recessive again. Including the TXD condition ensures that output driver oscillation due to
temperature drift is avoided.
7.3 SPLIT output pin and VIO supply pin

Two versions of the TJA1042 are available, only differing in the function of a single pin.
Pin 5 is either a SPLIT output pin or a VIO supply pin.
7.3.1 SPLIT pin

Using the SPLIT pin on the TJA1042T in conjunction with a split termination network (see
Figure 3 and Figure 6) can help to stabilize the recessive voltage level on the bus. This
will reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with
poor bus leakage performance). In Normal mode, pin SPLIT delivers a DC output voltage
of 0.5VCC. In Standby mode or when VCC is off, pin SPLIT is floating. When not used, the
SPLIT pin should be left open.

VCC
TJA1042T
CANH
R 60 Ω
VSPLIT = 0.5 VCC SPLIT
in normal mode;
otherwise floating
R 60 Ω
CANL
GND 015aaa020
Fig 3. Stabilization circuitry and application for version with SPLIT pin
7.3.2 VIO supply pin

Pin VIO on the TTJA1042T/3 and TJA1042TK/3 should be connected to the
microcontroller supply voltage (see Figure 7). This will adjust the signal levels of
pins TXD, RXD and STB to the I/O levels of the microcontroller. Pin VIO also provides the
internal supply voltage for the low-power differential receiver of the transceiver. For
applications running in low-power mode, this allows the bus lines to be monitored for
activity even if there is no supply voltage on pin VCC.
For versions of the TJA1042 without a VIO pin, the VIO input is internally connected to VCC.
This sets the signal levels of pins TXD, RXD and STB to levels compatible with 5 V
microcontrollers.

8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol Parameter Conditions Min Max Unit
Vx voltage on pin x on pins CANH, CANL and SPLIT 58 +58 V
on any other pin 0.3 +7 V
Vtrt transient voltage on pins CANH and CANL [1] 150 +100 V
VESD electrostatic discharge voltage IEC 61000-4-2 (150 pF, 330 ) [2]
at pins CANH and CANL 8 +8 kV

Human Body Model (HBM); 100 pF, 1.5 k [3]
at pins CANH and CANL 8 +8 kV

at any other pin 4 +4 kV
Machine Model (MM); 200 pF, 0.75 H, 10  [4]
at any pin 300 +300 V

Charged Device Model (CDM); field Induced [5]
charge; 4 pF
at corner pins 750 +750 V
at any pin 500 +500 V
Tvj virtual junction temperature [6] 40 +150 C
Tstg storage temperature 55 +150 C
[1] Verified by an external test house to ensure pins CANH and CANL can withstand ISO 7637 part 3 automotive transient test pulses 1, 2a,
3a and 3b.
[2] According to IEC TS 62228 (2007), Section 4.3; DIN EN 61000-4-2.
[3] According to AEC-Q100-002.
[4] According to AEC-Q100-003.
[5] According to AEC-Q100-011 Rev-C1. The classification level is C4B.
[6] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P  Rth(vj-a), where Rth(vj-a) is a
fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
9. Thermal characteristics
Table 6. Thermal characteristics
According to IEC 60747-1.
Symbol Parameter Conditions Value Unit
Rth(vj-a) thermal resistance from virtual junction to ambient SO8 package; in free air 145 K/W
HVSON8 package; in free air 50 K/W

10. Static characteristics

Table 7. Static characteristics
Tvj = 40 C to +150 C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V[1]; RL = 60  unless specified otherwise; All voltages are
defined with respect to ground; Positive currents flow into the IC.[2]
Supply; pin VCC
VCC supply voltage 4.5 - 5.5 V
Vuvd(VCC) undervoltage detection 3.5 - 4.5 V
voltage on pin VCC
ICC supply current Standby mode
TJA1042T; includes IIO; VTXD = VIO - 10 15 A
TJA1042T/3 or TJA1042TK/3 - - 5 A
Normal mode
recessive; VTXD = VIO 2.5 5 10 mA
dominant; VTXD = 0 V 20 45 70 mA
I/O level adapter supply; pin VIO[1]
VIO supply voltage on pin VIO 2.8 - 5.5 V
Vuvd(VIO) undervoltage detection 1.3 2.0 2.7 V
voltage on pin VIO
IIO supply current on pin VIO Standby mode; VTXD = VIO 5 - 14 A
Normal mode
recessive; VTXD = VIO 15 80 200 A
dominant; VTXD = 0 V - 350 1000 A
Standby mode control input; pin STB
VIH HIGH-level input voltage [3] 0.7VIO - VIO + V
0.3
VIL LOW-level input voltage 0.3 - 0.3VIO V
IIH HIGH-level input current VSTB = VIO 1 - +1 A
IIL LOW-level input current VSTB = 0 V 15 - 1 A
CAN transmit data input; pin TXD
VIH HIGH-level input voltage [3] 0.7VIO - VIO + V
0.3
VIL LOW-level input voltage 0.3 - 0.3VIO V
IIH HIGH-level input current VTXD = VIO 5 - +5 A
IIL LOW-level input current VTXD = 0 V 260 150 30 A
Ci input capacitance [4] - 5 10 pF
CAN receive data output; pin RXD
IOH HIGH-level output current VRXD = VIO  0.4 V; VIO = VCC 8 3 1 mA
IOL LOW-level output current VRXD = 0.4 V; bus dominant 2 5 12 mA
Bus lines; pins CANH and CANL
VO(dom) dominant output voltage VTXD = 0 V; t < tto(dom)TXD
pin CANH 2.75 3.5 4.5 V
pin CANL 0.5 1.5 2.25 V

Table 7. Static characteristics …continued

Tvj = 40 C to +150 C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V[1]; RL = 60  unless specified otherwise; All voltages are
defined with respect to ground; Positive currents flow into the IC.[2]
Vdom(TX)sym transmitter dominant voltage Vdom(TX)sym = VCC  VCANH  VCANL 400 - +400 mV
symmetry
VO(dif)bus bus differential output voltage VTXD = 0 V; t < tto(dom)TXD 1.5 - 3 V
VCC = 4.75 V to 5.25 V
RL = 45  to 65 
VTXD = VIO; recessive; no load 50 - +50 mV
VO(rec) recessive output voltage Normal mode; VTXD = VIO; no load 2 0.5VCC 3 V
Standby mode; no load 0.1 - +0.1 V
Vth(RX)dif differential receiver threshold Vcm(CAN) = 30 V to +30 V [5]
voltage Normal mode 0.5 0.7 0.9 V

Standby mode [6] 0.4 0.7 1.15 V
Vhys(RX)dif differential receiver hysteresis Vcm(CAN) = 30 V to +30 V 50 120 200 mV
voltage Normal mode
IO(sc)dom dominant short-circuit output VTXD = 0 V; t < tto(dom)TXD; VCC = 5 V
current pin CANH; VCANH = 0 V 100 70 40 mA
pin CANL; VCANL = 5 V / 40 V 40 70 100 mA
IO(sc)rec recessive short-circuit output Normal mode; VTXD = VIO 5 - +5 mA
current VCANH = VCANL = 27 V to +32 V
IL leakage current VCC = VIO = 0 V or VCC = VIO = shorted 5 - +5 A
to ground via 47 k;
VCANH = VCANL = 5 V
Ri input resistance 9 15 28 k
Ri input resistance deviation between VCANH and VCANL 1 - +1 %
Ri(dif) differential input resistance 19 30 52 k
Ci(cm) common-mode input [4] - - 20 pF
capacitance
Ci(dif) differential input capacitance [4] - - 10 pF
Common mode stabilization output; pin SPLIT; only for TJA1042T
VO output voltage Normal mode 0.3VCC 0.5VCC 0.7VCC V
ISPLIT = 500 A to +500 A
Normal mode; RL = 1 M 0.45VCC 0.5VCC 0.55VCC V
IL leakage current Standby mode 5 - +5 A
VSPLIT = 58 V to +58 V
Temperature detection
Tj(sd) shutdown junction [4] - 190 - C
temperature
[1] Only TJA1042T/3 and TJA1042TK/3 have a VIO pin. With TJA1042T, the VIO input is internally connected to VCC.
[2] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[3] Maximum value assumes VCC < VIO; if VCC > VIO, the maximum value will be VCC + 0.3 V.
[4] Not tested in production; guaranteed by design.
[5] Vcm(CAN) is the common mode voltage of CANH and CANL.

[6] For TJA1042T/3 and TJA1042TK/3: values valid when VIO = 4.5 V to 5.5 V; when VIO = 2.8 V to 4.5 V, values valid when
Vcm(CAN) = 12 V to +12 V.
11. Dynamic characteristics

Table 8. Dynamic characteristics
Tvj = 40 C to +150 C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V[1]; RL = 60  unless specified otherwise. All voltages are
defined with respect to ground. Positive currents flow into the IC.[2]
Transceiver timing; pins CANH, CANL, TXD and RXD; see Figure 4 and Figure 8
td(TXD-busdom) delay time from TXD to bus dominant Normal mode - 65 - ns
td(TXD-busrec) delay time from TXD to bus recessive Normal mode - 90 - ns
td(busdom-RXD) delay time from bus dominant to RXD Normal mode - 60 - ns
td(busrec-RXD) delay time from bus recessive to RXD Normal mode - 65 - ns
tPD(TXD-RXD) propagation delay from TXD to RXD version with SPLIT pin; 60 - 220 ns
Normal mode
versions with VIO pin; 60 - 250 ns
Normal mode
tbit(RXD) bit time on pin RXD tbit(TXD) = 500 ns [3] 400 - 550 ns
tto(dom)TXD TXD dominant time-out time VTXD = 0 V; Normal mode 0.3 2 5 ms
tto(dom)bus bus dominant time-out time Standby mode 0.3 2 5 ms
tfltr(wake)bus bus wake-up filter time version with SPLIT pin 0.5 1 3 s
Standby mode
versions with VIO pin 0.5 1.5 5 s
Standby mode
td(stb-norm) standby to normal mode delay time 7 25 47 s
[1] Only TJA1042T/3 and TJA1042TK/3 have a VIO pin. With TJA1042T, the VIO input is internally connected to VCC.
[2] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[3] See Figure 5.

HIGH
TXD
LOW
CANH
CANL
dominant
0.9 V
VO(dif)(bus)
0.5 V
recessive
HIGH
0.7VIO
RXD
0.3VIO
LOW
td(TXD-busdom) td(TXD-busrec)
td(busdom-RXD) td(busrec-RXD)
tPD(TXD-RXD) tPD(TXD-RXD) 015aaa025
Fig 4. CAN transceiver timing diagram

7;'

[WELW 7;'
WELW 7;'

5;'

WELW 5;'
DDD
Fig 5. Loop delay symmetry timing diagram

12. Application information
12.1 Application diagrams
BAT 5V
VCC
CANH STB VDD

CANH Pxx
SPLIT Pyy MICRO-

TJA1042T
TXD CONTROLLER
TX0
CANL RXD
CANL RX0
GND
GND
015aaa022
Fig 6. Typical application with TJA1042T and a 5 V microcontroller.
BAT 3V
INH
5V
VCC VIO
CANH STB VDD

CANH Pxx
TJA1042T/3 MICRO-
TJA1042TK/3 TXD CONTROLLER
TX0
CANL RXD
CANL RX0
GND
GND 015aaa021
Switching off the 5 V supply in Standby mode (dotted line) is optional.

Fig 7. Typical application with TJA1042T/3 or TJA1042TK/3 and a 3 V microcontroller.
12.2 Application hints

Further information on the application of the TJA1042 can be found in NXP application
hints AH1014 Application Hints - Standalone high speed CAN transceiver
TJA1042/TJA1043/TJA1048/TJA1051.

13. Test information
+5 V
47 μF 100 nF
VIO(1) VCC
TXD CANH
TJA1042 RL 100 pF
SPLIT
RXD CANL
GND STB
15 pF
015aaa024
(1) For versions with a VIO pin (TJA1042T/3 and TJA1042TK/3), the VIO pin is connected to pin VCC.
Fig 8. Timing test circuit for CAN transceiver
13.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.

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15. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering

Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 11) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350  350
< 2.5 235 220
 2.5 220 220
Table 10. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 11.

maximum peak temperature

temperature = MSL limit, damage level
minimum peak temperature

= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level

Fig 11. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.
17. Soldering of HVSON packages

Section 16 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can found in the following application notes:
• AN10365 ‘Surface mount reflow soldering description”

• AN10366 “HVQFN application information”

18. Revision history

Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TJA1042 v.8 20150115 Product data sheet - TJA1042 v.7
Modifications • Section 1: text revised (1st paragraph); paragraph added
• Section 2, Section 7 , Section 7.1.1, Section 7.3.1: text revised
• Section 2.1, Section 2.3: features added
• Table 1: added parameters VIO, Vuvd(VIO) and IIO; measurements conditions changed: VCANH, VCANL
• Figure 2 : pin diagrams updated
• Table 3: Table note 1: text revised
• Table 5: measurements conditions changed: Vx, VESD; table note section revised
• Table 7: parameters in VCC and VIO sections rearranged; measurement conditions changed: IL;
parameter symbol/description changed: IO(sc)dom, IO(sc)rec; Table note 4 revised
• Table 8: parameter tbit(RXD) added; Table note 3 and Figure 5 added
• Figure 8 moved to Section 13 “Test information”
• Section 12.2 “Application hints”: added
• Section 13.1: text updated
• Table 9 and Table 10: header text changed
• Section 19.3: ‘Translations’ disclaimer added
TJA1042 v.1 20090309 Product data sheet - -

19. Legal information
19.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
Draft — The document is a draft version only. The content is still under
authorized or warranted to be suitable for use in life support, life-critical or
internal review and subject to formal approval, which may result in
safety-critical systems or equipment, nor in applications where failure or
modifications or additions. NXP Semiconductors does not give any
malfunction of an NXP Semiconductors product can reasonably be expected
representations or warranties as to the accuracy or completeness of
to result in personal injury, death or severe property or environmental
information included herein and shall have no liability for the consequences of
damage. NXP Semiconductors and its suppliers accept no liability for
use of such information.
inclusion and/or use of NXP Semiconductors products in such equipment or
Short data sheet — A short data sheet is an extract from a full data sheet applications and therefore such inclusion and/or use is at the customer's own
with the same product type number(s) and title. A short data sheet is intended risk.
for quick reference only and should not be relied upon to contain detailed and
Applications — Applications that are described herein for any of these
full information. For detailed and full information see the relevant full data
products are for illustrative purposes only. NXP Semiconductors makes no
sheet, which is available on request via the local NXP Semiconductors sales
representation or warranty that such applications will be suitable for the
office. In case of any inconsistency or conflict with the short data sheet, the
specified use without further testing or modification.
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
Product specification — The information and data provided in a Product and products using NXP Semiconductors products, and NXP Semiconductors
data sheet shall define the specification of the product as agreed between accepts no liability for any assistance with applications or customer product
NXP Semiconductors and its customer, unless NXP Semiconductors and design. It is customer’s sole responsibility to determine whether the NXP
customer have explicitly agreed otherwise in writing. In no event however, Semiconductors product is suitable and fit for the customer’s applications and
shall an agreement be valid in which the NXP Semiconductors product is products planned, as well as for the planned application and use of
deemed to offer functions and qualities beyond those described in the customer’s third party customer(s). Customers should provide appropriate
Product data sheet. design and operating safeguards to minimize the risks associated with their
applications and products.
19.3 Disclaimers NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
Limited warranty and liability — Information in this document is believed to
third party customer(s). Customer is responsible for doing all necessary
be accurate and reliable. However, NXP Semiconductors does not give any
testing for the customer’s applications and products using NXP
representations or warranties, expressed or implied, as to the accuracy or
Semiconductors products in order to avoid a default of the applications and
completeness of such information and shall have no liability for the
the products or of the application or use by customer’s third party
consequences of use of such information. NXP Semiconductors takes no
customer(s). NXP does not accept any liability in this respect.
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors. Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
In no event shall NXP Semiconductors be liable for any indirect, incidental,
damage to the device. Limiting values are stress ratings only and (proper)
punitive, special or consequential damages (including - without limitation - lost
operation of the device at these or any other conditions above those given in
profits, lost savings, business interruption, costs related to the removal or
the Recommended operating conditions section (if present) or the
replacement of any products or rework charges) whether or not such
Characteristics sections of this document is not warranted. Constant or
damages are based on tort (including negligence), warranty, breach of
repeated exposure to limiting values will permanently and irreversibly affect
contract or any other legal theory.
the quality and reliability of the device.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards Terms and conditions of commercial sale — NXP Semiconductors
customer for the products described herein shall be limited in accordance products are sold subject to the general terms and conditions of commercial
with the Terms and conditions of commercial sale of NXP Semiconductors. sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
Right to make changes — NXP Semiconductors reserves the right to make agreement is concluded only the terms and conditions of the respective
changes to information published in this document, including without agreement shall apply. NXP Semiconductors hereby expressly objects to
limitation specifications and product descriptions, at any time and without applying the customer’s general terms and conditions with regard to the
notice. This document supersedes and replaces all information supplied prior purchase of NXP Semiconductors products by customer.
to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or Translations — A non-English (translated) version of a document is for
construed as an offer to sell products that is open for acceptance or the grant, reference only. The English version shall prevail in case of any discrepancy
conveyance or implication of any license under any copyrights, patents or between the translated and English versions.
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
19.4 Trademarks
authorization from competent authorities. Notice: All referenced brands, product names, service names and trademarks
Quick reference data — The Quick reference data is an extract of the are the property of their respective owners.
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
20. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

21. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2 Predictable and fail-safe behavior . . . . . . . . . . 2 20 Contact information . . . . . . . . . . . . . . . . . . . . 22
2.3 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
7.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5
7.1.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7.1.2 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 5
7.2 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 6
7.2.1 TXD dominant time-out function . . . . . . . . . . . . 6
7.2.2 Bus dominant time-out function . . . . . . . . . . . . 6
7.2.3 Internal biasing of TXD and STB input pins . . . 6
7.2.4 Undervoltage detection on pins VCC and VIO . . 6
7.2.5 Overtemperature protection . . . . . . . . . . . . . . . 6
7.3 SPLIT output pin and VIO supply pin . . . . . . . . 6
7.3.1 SPLIT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.3.2 VIO supply pin . . . . . . . . . . . . . . . . . . . . . . . . . . 7
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
9 Thermal characteristics . . . . . . . . . . . . . . . . . . 8
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 11
12 Application information. . . . . . . . . . . . . . . . . . 13
12.1 Application diagrams . . . . . . . . . . . . . . . . . . . 13
12.2 Application hints . . . . . . . . . . . . . . . . . . . . . . . 13
13 Test information . . . . . . . . . . . . . . . . . . . . . . . . 14
13.1 Quality information . . . . . . . . . . . . . . . . . . . . . 14
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
15 Handling information. . . . . . . . . . . . . . . . . . . . 17
16 Soldering of SMD packages . . . . . . . . . . . . . . 17
16.1 Introduction to soldering . . . . . . . . . . . . . . . . . 17
16.2 Wave and reflow soldering . . . . . . . . . . . . . . . 17
16.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17
16.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18
17 Soldering of HVSON packages. . . . . . . . . . . . 19
18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20
19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP N.V. 2015. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 January 2015
Document identifier: TJA1042

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TJA1042

High-speed CAN transceiver with Standby mode

2. Features and benefits

2.2 Predictable and fail-safe behavior

3. Quick reference data

Product data sheet Rev. 8 — 15 January 2015 2 of 23

Product data sheet Rev. 8 — 15 January 2015 3 of 23

a. TJA1042T: SO8 b. TJA1042T/3: SO8 c. TJA1042TK/3: HVSON8

6.2 Pin description

Product data sheet Rev. 8 — 15 January 2015 4 of 23

7.1 Operating modes

Table 4. Operating modes

7.1.1 Normal mode

7.1.2 Standby mode

Product data sheet Rev. 8 — 15 January 2015 5 of 23

7.2 Fail-safe features

7.2.1 TXD dominant time-out function

7.2.2 Bus dominant time-out function

7.2.3 Internal biasing of TXD and STB input pins

7.2.4 Undervoltage detection on pins VCC and VIO

7.2.5 Overtemperature protection

7.3 SPLIT output pin and VIO supply pin

7.3.1 SPLIT pin

Product data sheet Rev. 8 — 15 January 2015 6 of 23

7.3.2 VIO supply pin

Product data sheet Rev. 8 — 15 January 2015 7 of 23

at pins CANH and CANL 8 +8 kV

at pins CANH and CANL 8 +8 kV

at any pin 300 +300 V

Product data sheet Rev. 8 — 15 January 2015 8 of 23

10. Static characteristics

Product data sheet Rev. 8 — 15 January 2015 9 of 23

Table 7. Static characteristics …continued

voltage Normal mode 0.5 0.7 0.9 V

Product data sheet Rev. 8 — 15 January 2015 10 of 23

11. Dynamic characteristics

Product data sheet Rev. 8 — 15 January 2015 11 of 23

tPD(TXD-RXD) tPD(TXD-RXD) 015aaa025

Fig 4. CAN transceiver timing diagram

Fig 5. Loop delay symmetry timing diagram

Product data sheet Rev. 8 — 15 January 2015 12 of 23

12. Application information

12.1 Application diagrams

CANH STB VDD

SPLIT Pyy MICRO-

Fig 6. Typical application with TJA1042T and a 5 V microcontroller.

CANH STB VDD

Switching off the 5 V supply in Standby mode (dotted line) is optional.

12.2 Application hints

Product data sheet Rev. 8 — 15 January 2015 13 of 23

13. Test information

13.1 Quality information

Product data sheet Rev. 8 — 15 January 2015 14 of 23

14. Package outline

287/,1( 5()(5(1&(6 (8523($1

Fig 9. Package outline SOT96-1 (SO8)

Product data sheet Rev. 8 — 15 January 2015 15 of 23

8QLW  $ $ E F ' 'K ( (K H H . / Y Z \ \

2XWOLQH 5HIHUHQFHV (XURSHDQ

8QLW $ $ E F ' 'K ( (K H H . / Y Z \ \