TCAN1044-Q1 Automotive Fault-Protected CAN FD Transceiver: 1 Features 3 Description

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TCAN1044-Q1, TCAN1044V-Q1
SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019
TCAN1044-Q1 Automotive Fault-Protected CAN FD Transceiver

1 Features 3 Description
1• AEC-Q100: Qualified for automotive applications The TCAN1044-Q1 is a high speed controller area
network (CAN) transceiver that meets the physical
– Temperature grade 1: –40°C to 125°C TA layer requirements of the ISO 11898-2:2016 high-
• Meets the requirements of ISO 11898-2:2016 and speed CAN specification.
ISO 11898-5:2007 physical layer standards
The TCAN1044-Q1 transceiver supports both
• Support of classical CAN and optimized CAN FD classical CAN and CAN FD networks up to 8
performance at 2, 5, and 8 Mbps megabits per second (Mbps). The TCAN1044-Q1
– Short and symmetrical propagation delays and includes internal logic level translation via the VIO
fast loop times for enhanced timing margin terminal to allow for interfacing the transceiver IOs
directly to 1.8-V, 2.5-V, 3.3-V, or 5-V logic IOs. The
– Higher data rates in loaded CAN networks
transceiver has a low-power standby mode which
• IO voltage range supports 1.7 V to 5.5 V supports remote wake-up via the ISO 11898-2:2016
– Support for 1.8-V, 2.5-V, 3.3-V, and 5-V defined wake-up pattern (WUP). The TCAN1044-Q1
applications transceiver also includes many protection and
diagnostic features including thermal-shutdown
• Receiver common mode input voltage: ±12 V
(TSD), TXD-dominant time-out (DTO), supply under-
• Protection features: voltage detection, and bus fault protection up to
– Bus fault protection: ±58 V ±58 V.
– Under-voltage protection
Device Information(1)
– TXD-dominant time-out (DTO)
PART NUMBER PACKAGE BODY SIZE (NOM)
– Data rates down to 9.2 kbps SOT (8) 2.90 mm x 1.60 mm
– Thermal-shutdown protection (TSD) TCAN1044x-Q1 VSON (8) 3.00 mm x 3.00 mm
• Operating modes: SOIC (8) 4.90 mm x 3.91 mm
– Normal mode (1) For all available packages, see the orderable addendum at
– Low power standby mode supporting remote the end of the data sheet.
wake-up request
Simplified Block Diagram
• Optimized behavior when unpowered
NC or VIO VCC
– Bus and logic pins are high impedance (no
5 3
load to operating bus or application)
– Hot-plug capable: power up/down glitch free
operation on bus and RXD output
VCC or VIO
• Junction temperatures from: –40°C to 150°C TSD 7 CANH
• Available in SOIC (8), SOT23 (8) packages

(2.9 mm x 1.60 mm) and leadless VSON (8) TXD 1
Dominant
time-out
packages (3.0 mm x 3.0 mm) with improved 6 CANL
automated optical inspection (AOI) capability VCC or VIO
2 Applications STB 8 Mode Sele ct
• Automotive and Transportation

UVP
– Body control modules
– Automotive gateway VCC or VIO
– Advanced driver assistance system (ADAS) 4 Log ic Output MUX

RXD
– Infotainment WUP Mon itor
Low Power Rece iver
GND
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ....................................... 15
2 Applications ........................................................... 1 8.3 Feature Description................................................. 16
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 20
4 Revision History..................................................... 2 9 Application and Implementation ........................ 23
9.1 Application Information............................................ 23
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 23
6 Specifications......................................................... 4
9.3 System Examples ................................................... 26
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4 10 Power Supply Recommendations ..................... 26
6.3 ESD Ratings.............................................................. 4 11 Layout................................................................... 27
6.4 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 27
6.5 Thermal Characteristics ............................................ 5 11.2 Layout Example .................................................... 27
6.6 Supply Characteristics .............................................. 5 12 Device and Documentation Support ................. 28
6.7 Dissipation Ratings ................................................... 5 12.1 Documentation Support ........................................ 28
6.8 Electrical Characteristics........................................... 6 12.2 Receiving Notification of Documentation Updates 28
6.9 Switching Characteristics .......................................... 7 12.3 Support Resources ............................................... 28
6.10 Typical Characteristics ............................................ 9 12.4 Trademarks ........................................................... 28
7 Parameter Measurement Information ................ 10 12.5 Electrostatic Discharge Caution ............................ 28
12.6 Glossary ................................................................ 28
8 Detailed Description ............................................ 14
8.1 Overview ................................................................. 14 13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2019) to Revision A Page
• First public release of the data sheet .................................................................................................................................... 1

• Added SAE j2962-2 ESD........................................................................................................................................................ 4
• Changed foortnote to Tested according to IEC 62228-3:2019 CAN Transceivers, Section 6.3; standard pulses
parameters defined in ISO 7637-2 (2011).............................................................................................................................. 4
2 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TCAN1044-Q1 TCAN1044V-Q1

www.ti.com SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019
5 Pin Configuration and Functions
DDF Package TCAN1044(V)-Q1

8-Pin SOT D Package TCAN1044(V)-Q1
Top View 8-Pin SOIC
Top View
TX D 1 8 STB
TX D 1 8 STB
GND 2 7 CA NH
GND 2 7 CA NH
VCC 3 6 CA NL
VCC 3 6 CA NL
RX D 4 5 NC, VIO
RX D 4 5 NC, VIO
No t to scale
No t to scale
DRB Package TCAN1044(V)-Q1

8-Pin VSON
Top View
TXD 1 8 STB
GND 2 7 CANH
Thermal
Pad
VCC 3 6 CANL
RXD 4 5 NC,VIO
Not to scale
Pin Functions
Pins
Type Description
Name No.
TXD 1 Digital Input CAN transmit data input
GND 2 GND Ground connection
VCC 3 Supply 5-V supply voltage
RXD 4 Digital Output CAN receive data output, tri-state when powered off
NC — No Connect (not internally connected); Devices without VIO
5
VIO Supply IO supply voltage
CANL 6 Bus IO Low-level CAN bus input/output line
CANH 7 Bus IO High-level CAN bus input/output line
STB 8 Digital Input Standby input for mode control, integrated pull up
Electrically connected to GND, connect the thermal pad to the printed circuit board
Thermal Pad (VSON only) —
(PCB) ground plane for thermal relief
Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 3

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
VCC Supply voltage –0.3 6 V
VIO Supply voltage IO level shifter –0.3 6 V
VBUS CAN Bus IO voltage CANH and CANL –58 58 V
VDIFF Max differential voltage between CANH and CANL –45 45 V
VLogic_Input Logic input terminal voltage –0.3 6 V
VRXD RXD output terminal voltage range –0.3 6 V
IO(RXD) RXD output current –8 8 mA
TJ Operating virtual junction temperature range –40 150 °C
TSTG Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential IO bus voltages, are with respect to ground terminal.
6.2 ESD Ratings

VALUE UNIT
HBM classification level 3A for
±3000 V
all pins
Human-body model (HBM), per AEC Q100-002 (1)
Electrostatic HBM classififation level 3B for
VESD ±10000 V
discharge global pins CANH & CANL
Charged-device model (CDM), per AEC Q100-011
±750 V
CDM classification level C5 for all pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings

VALUE UNIT
SAE J2962-2 per ISO 10650
±8000 V
System Level Electro-Static Discharge Powered Contact Discharge
VESD CAN bus terminals (CANH, CANL) to GND
(ESD) (1) SAE J2962-2 per ISO 10650
±15000 V
Powered Air Discharge
Pulse 1 –100 V
Pulse 2a 75 V
ISO 7637 ISO Pulse Transients (2) CAN bus terminals (CANH, CANL)
VTran Pulse 3a –150 V
Pulse 3b 100 V
ISO 7637 Slow transients pulse (3) CAN bus terminals (CANH, CANL) to GND DCC slow transient pulse ±85 V
(1) Results given here are specific to the SAE J2962-2 Communication Transceivers Qualification Requirements - CAN. Testing performed
by OEM approved independent 3rd party, EMC report available upon request.
(2) Tested according to IEC 62228-3:2019 CAN Transcievers, Section 6.3; standard pulses parameters defined in ISO 7637-2 (2011)
(3) Tested according to ISO 7637-3 (2017); Electrical transient transmission by capacitive and inductive coupling via lines other than supply
lines
6.4 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIO Supply voltage for IO level shifter 1.7 5.5 V
IOH(RXD) RXD terminal high level output current –2 mA
IOL(RXD) RXD terminal low level output current 2 mA
TA Operating ambient temperature –40 125 ℃

6.5 Thermal Characteristics

TCAN1044x-Q1
THERMAL METRIC (1) UNIT
D (SOIC) DDF (SOT) DRB (VSON)
RΘJA Junction-to-ambient thermal resistance 128.1 119.9 49.9 ℃/W
RΘJC(top) Junction-to-case (top) thermal resistance 68.3 61.8 58.2 ℃/W
RΘJB Junction-to-board thermal resistance 71.6 39.7 23.9 ℃/W
ΨJT Junction-to-top characterization parameter 19.7 2.1 1.7 ℃/W
ΨJB Junction-to-board characterization parameter 70.8 39.5 23.8 ℃/W
RΘJC(bot) Junction-to-case (bottom) thermal resistance - – 6.4 ℃/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Supply Characteristics

Over recommended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
See Figure 5,TXD = 0 V, STB = 0 V, RL =
45 70 mA
60 Ω, CL = open
Dominant
See Figure 5, TXD = 0 V, STB = 0 V, RL
49 80 mA
= 50 Ω, CL = open
Supply current normal
ICC See Figure 5, TXD = VCC, STB = 0 V, RL
mode Recessive 4.5 7.5 mA
= 50 Ω, CL = open, RCM = open
See Figure 5, TXD = 0 V, STB = 0 V,
Dominant with
CANH = CANL = ±25 V, RL = open, CL = 130 mA
bus fault
open
TXD = STB = VIO
Supply current standby mode
ICC RL = 50 Ω, CL = open 0.2 1 µA
Devices with VIO
See Figure 5
TXD = STB = VCC
Supply current standby mode
ICC RL = 50 Ω, CL = open 14.5 µA
Devices without VIO
See Figure 5
IO supply current normal TXD = 0 V, STB= 0 V
IIO Dominant 125 300 µA
mode RXD floating
IO supply current normal TXD = 0 V, STB = 0 V
IIO Recessive 25 48 µA
mode RXD floating
TXD = 0 V, STB = VIO
IIO IO supply current standby mode 8.5 13.5 µA
RXD floating
UVVCC Rising under voltage detection on VCC for protected mode 4.2 4.4 V
UVVCC Falling under voltage detection on VCC for protected mode 3.5 4 4.25 V
UVVIO Rising under voltage detection on VIO (Devices with VIO) 1.56 1.65 V
UVVIO Falling under voltage detection on VIO (Devices with VIO) 1.4 1.51 1.59 V
6.7 Dissipation Ratings

VCC = 5 V, VIO = 1.8 V, TJ= 27°C, RL = 60Ω,
TXD input = 250 kHz 50% duty cycle 110 mW
squarewave, CL_RXD = 15 pF
VCC = 5 V, VIO = 3.3 V, TJ= 27°C, RL = 60Ω,
TXD input = 250 kHz 50% duty cycle 110 mW
Average power dissipation VCC = 5 V, VIO = 5 V, TJ= 27°C, RL = 60Ω, TXD

PD input = 250 kHz 50% duty cycle squarewave, 110 mW
Normal mode CL_RXD = 15 pF
VCC = 5.5 V, VIO = 1.8 V, TA= 125°C, RL =
60Ω, TXD input = 2.5 MHz 50% duty cycle 120 mW
VCC = 5.5 V, VIO = 3.3 V, TA= 125°C, RL =
60Ω, TXD input = 2.5 MHz 50% duty cycle 120 mW
Average power dissipation VCC = 5.5 V, VIO = 5 V, TA= 125°C, RL = 60Ω,

PD TXD input = 2.5 MHz 50% duty cycle 120 mW
Normal mode squarewave, CL_RXD = 15 pF

Dissipation Ratings (continued)

TTSD Thermal shutdown temperature 192
°C
TTSD_HYS Thermal shutdown hysteresis 10
6.8 Electrical Characteristics

Over recomended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
Driver Electrical Characteristics
CANH See Figure 6 and Figure 14, TXD = 0 V, 2.75 4.5 V
Dominant output voltage
VO(DOM) STB = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open,
normal mode CANL 0.5 2.25 V
RCM = open
See Figure 6 and Figure 14, TXD = VIO,
Recessive output voltage
VO(REC) CANH and CANL STB = 0 V, RL = open (no load), RCM = 2 0.5 VCC 3 V
normal mode
open
Driver symmetry See Figure 6 and Figure 18, STB = 0 V, RL

VSYM = 60 Ω, CSPLIT = 4.7 nF, CL = open, RCM = 0.9 1.1 V/V
(VO(CANH) + VO(CANL))/VCC open, TXD = 250 kHz, 1 MHz, 2.5 MHz
DC output symmetry See Figure 6 and Figure 14, STB = 0 V, RL
VSYM_DC –400 400 mV
(VCC - VO(CANH) - VO(CANL)) = 60 Ω, CL = open
See Figure 6 and Figure 14, TXD = 0 V,
1.5 3 V
STB = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open
Differential output voltage
normal mode See Figure 6 and Figure 14, TXD = 0 V,
VOD(DOM) CANH - CANL 1.4 3.3 V
STB = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open
Dominant
See Figure 6 and Figure 14, TXD = 0 V,
1.5 5 V
STB = 0 V, RL = 2240 Ω, CL = open
See Figure 6 and Figure 14, TXD = VIO,
Differential output voltage –120 12 mV
STB = 0 V, RL = 60 Ω, CL = open
VOD(REC) normal mode CANH - CANL
Recessive See Figure 6 and Figure 14, TXD = VIO,
–50 50 mV
STB = 0 V, RL = open, CL = open
CANH -0.1 0.1 V
Bus output voltage See Figure 6 and Figure 14, STB = VIO, RL
VO(STB) CANL -0.1 0.1 V
standby mode = open (no load), RCM = open
CANH - CANL -0.2 0.2 V
See Figure 11 and Figure 14, STB = 0 V,
V(CANH) = -15 V to 40 V, CANL = open, –115 mA
Short-circuit steady-state output current, TXD = 0 V
IOS(SS_DOM)
dominant, normal mode See Figure 11 and Figure 14, STB = 0 V,
V(CAN_L) = -15 V to 40 V, CANH = open, 115 mA
TXD = 0 V
See Figure 11 and Figure 14, STB = 0 V,
Short-circuit steady-state output current,
IOS(SS_REC) –27 V ≤ VBUS ≤ 32 V, –5 5 mA
recessive, normal mode
Where VBUS = CANH = CANL, TXD = VIO
Receiver Electrical Characteristics
See Figure 7, Table 1, and Table 7
VIT Input threshold voltage normal mode 500 900 mV
STB = 0 V, -12 V ≤ VCM ≤ 12 V
See Figure 7, Table 1, and Table 7
VIT(STB) Input threshold standby mode 400 1150 mV
STB = VIO, -12 V ≤ VCM ≤ 12 V
Normal mode dominant state differential input See Figure 7, Table 1, and Table 7
VDOM 0.9 9 V
voltage range STB = 0 V, -12 V ≤ VCM ≤ 12 V
Normal mode recessive state differential input See Figure 7, Table 1, and Table 7
VREC -4 0.5 V
voltage range STB = 0 V, -12 V ≤ VCM ≤ 12 V
Standby mode dominant state differential input See Figure 7, Table 1, and Table 7
VDOM(STB) 1.15 9 V
voltage range STB = VIO, -12 V ≤ VCM ≤ 12 V
Standby mode recessive state differential input See Figure 7, Table 1, and Table 7
VREC(STB) -4 0.4 V
voltage range STB = VIO, -12 V ≤ VCM ≤ 12 V
Hysteresis voltage for input threshold normal See Figure 7, Table 1, and Table 7
VHYS 100 mV
mode STB = 0 V, -12 V ≤ VCM ≤ 12 V
Common mode range normal and standby
VCM See Figure 7 and Table 7 –12 12 V
modes
ILKG(IOFF) Unpowered bus input leakage current CANH = CANL = 5 V, VCC = VIO = GND 5 µA

Electrical Characteristics (continued)

CI Input capacitance to ground (CANH or CANL) 20 pF
TXD = VIO (1)
CID Differential input capacitance 10 pF
RID Differential input resistance 40 90 kΩ
TXD = VIO (1)
Single ended input resistance STB = 0 V, -12 V ≤ VCM ≤ 12 V
RIN 20 45 kΩ
(CANH or CANL)
Input resistance matching
RIN(M) V(CAN_H) = V(CAN_L) = 5 V –1 1 %
[1 – (RIN(CANH) / RIN(CANL))] × 100 %
TXD Terminal (CAN Transmit Data Input)
VIH High-level input voltage Devices without VIO 0.7 VCC V
VIH High-level input voltage Devices with VIO 0.7 VIO V
VIL Low-level input voltage Devices without VIO 0.3 VCC V
VIL Low-level input voltage Devices with VIO 0.3 VIO V
IIH High-level input leakage current TXD = VCC = VIO = 5.5 V –2.5 0 1 µA
IIL Low-level input leakage current TXD = 0 V, VCC= VIO = 5.5 V –200 -100 –20 µA
ILKG(OFF) Unpowered leakage current TXD = 5.5 V, VCC= VIO = 0 V –1 0 1 µA
CI Input Capacitance 6 5 pF
VIN = 0.4×sin(2×π×2×10 ×t)+2.5 V
RXD Terminal (CAN Receive Data Output)
Devices without VIO
VOH High-level input voltage 0.8 VCC V
See Figure 7, IO = –2 mA
Devices with VIO
VOH High-level input voltage 0.8 VIO V
See Figure 7, IO = –2 mA
Devices without VIO
VOL Low-level input voltage 0.2 VCC V
See Figure 7, IO = 2 mA
Devices with VIO
VOL Low-level input voltage 0.2 VIO V
See Figure 7, IO = 2 mA
ILKG(OFF) Unpowered leakage current RXD = 5.5 V, VCC= VIO = 0 V –1 0 1 µA
STB Terminal (Standby Mode Input)
VIH High-level input voltage Devices without VIO 0.7 VCC V
VIH High-level input voltage Devices with VIO 0.7 VIO V
VIL Low-level input voltage Devices without VIO 0.3 VCC V
VIL Low-level input voltage Devices with VIO 0.3 VIO V
IIH High-level input leakage current STB VCC = VIO = STB = 5.5 V –2 2 µA
IIL Low-level input leakage current STB VCC = VIO = 5.5 V, STB = 0 V –20 –2 µA
ILKG(OFF) Unpowered leakage current STB = 5.5V, VCC= VIO = 0 V –1 0 1 µA
(1) VIO = VCC in non-V variants of device
6.9 Switching Characteristics

Device Switching Characteristics
See Figure 8, normal mode, VIO = 2.8 V
to 5.5 V, RL = 60 Ω, CL = 100 pF, CL(RXD) 125 210 ns
Total loop delay, driver input (TXD) to receiver = 15 pF
tPROP(LOOP1)
output (RXD), recessive to dominant
See Figure 8, normal mode, VIO = 1.7 V,
165 255 ns
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
See Figure 8, normal mode, VIO = 2.8 V
to 5.5 V, RL = 60 Ω, CL = 100 pF, CL(RXD) 150 210 ns
Total loop delay, driver input (TXD) to receiver = 15 pF
tPROP(LOOP2)
output (RXD), dominant to recessive
See Figure 8, normal mode, VIO = 1.7 V,
180 255 ns
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
Mode change time, from normal to standby or from
tMODE See Figure 9 20 µs
standby to normal
tWK_FILTER Filter time for a valid wake-up pattern See Figure 16 0.5 1.8 µs

Switching Characteristics (continued)

tWK_TIMEOUT Bus wake-up timeout value See Figure 16 0.8 6 ms
Driver Switching Characteristics
Propagation delay time, high TXD to driver
tpHR 80 ns
recessive (dominant to recessive)
Propagation delay time, low TXD to driver
tpLD 70 ns
dominant (recessive to dominant) See Figure 6, STB = 0 V, RL = 60 Ω, CL
= 100 pF, RCM = open
tsk(p) Pulse skew (|tpHR - tpLD|) 20 ns
tR Differential output signal rise time 30 ns
tF Differential output signal fall time 50 ns
See Figure 10, RL = 60 Ω, CL = 100 pF,
tTXD_DTO Dominant timeout 1.2 4.0 ms
STB = 0 V
Receiver Switching Characteristics
Propagation delay time, bus recessive input to
tpRH 90 ns
high output (dominant to recessive)
Propagation delay time, bus dominant input to low See Figure 7
tpDL STB = 0 V, 65 ns
output (recessive to dominant)
CL(RXD) = 15 pF
tR RXD output signal rise time 10 ns
tF RXD output signal fall time 10 ns
FD Timing Characteristics
Bit time on CAN bus output pins with tBIT(TXD) =
tBIT(BUS) 450 530 ns
500 ns
Bit time on CAN bus output pins with tBIT(TXD) = See Figure 8, STB = 0 V, RL = 60 Ω, CL
tBIT(BUS) = 100 pF, CL(RXD) = 15 pF 155 210 ns
200 ns
STB = 0 V
tBIT(RXD) Bit time on RXD output pins with tBIT(TXD) = 500 ns 400 550 ns
tBIT(RXD) Bit time on RXD output pins with tBIT(TXD) = 200 ns 120 220 ns
tREC Receiver timing symmetry with tBIT(TXD) = 500 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF -50 20 ns
tREC Receiver timing symmetry with tBIT(TXD) = 200 ns ΔtREC = tBIT(RXD) - tBIT(BUS) -45 15 ns

6.10 Typical Characteristics
4 3
3.5
2.5
2
2.5
VOD(DOM) (V)
VOD(DOM) (V)
2 1.5
1.5
1
0.5
0.5
0 0
-40 -25 -10 5 20 35 50 65 80 95 110 125 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5
Temperature (qC) VOD( VCC (V) VOD(
VCC = 5 V VIO = 3.3 V RL = 60 Ω Temp = 25°C RL = 60 Ω
Figure 1. VOD(DOM) vs Temperature Figure 2. VOD(DOM) vs VCC

1 15
0.9
0.8 13
0.7
0.6 11
ICC (PA)
IIO (PA)
0.5
0.4 9
0.3
0.2 7
0.1
0 5
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (qC) D_IC Temperature (qC) D_II
VCC = 5 V VIO = 3.3 V RL = 60 Ω VCC = 5 V VIO = 3.3 V RL = 60 Ω
Figure 3. ICC Standby vs Temperature Figure 4. IIO Standby vs Temperature

7 Parameter Measurement Information
CANH
TXD
RL CL
CANL
Figure 5. ICC Test Circuit
RCM
CANH
TXD 50% 50%

TXD
RL CL VOD VCM VCC
VO(CANH) tpLD tpHR
CANL 90% 0V
RCM
0.9V
VO(CANL) VOD
10% 0.5V
tR tF
Figure 6. Driver Test Circuit and Measurement
CANH 1.5V
0.9V
IO VID
RXD 0.5V
0V
VID
tpDL
tpRH
CL_RXD VO VOH
CANL 90%
VO(RXD)
50%
10%
VOL
tR tF
Figure 7. Receiver Test Circuit and Measurement

Parameter Measurement Information (continued)

Table 1. Receiver Differential Input Voltage Threshold Test (See Figure 7)
Input Output
VCANH VCANL |VID| RXD
-11.5 V -12.5 V 1000 mV
12.5 V 11.5 V 1000 mV
L VOL
-8.55 V -9.45 V 900 mV
9.45 V 8.55 V 900 mV
-8.25 V -9.25 V 500 mV
9.25 V 8.25 V 500 mV
-11.8 V -12.2 V 400 mV H VOH
12.2 V 11.8 V 400 mV
Open Open X
TXD
VI
70%
tLOOP2
30% 30%
CANH
0V
TXD 5 x tBIT(TXD) tBIT(TXD)

VI RL CL
CANL
STB tBIT(BUS)
0V
900mV
RXD 500mV
VDIFF
VO CL_RXD
RXD
VOH
70%
30%
tBIT(RXD) VOL
tLOOP1
Figure 8. Transmitter and Receiver Timing Test Circuit and Measurement

CANH
VIH
TXD CL
0V RL
STB 50%
CANL
STB
VI
0V
tMODE
RXD
VOH
VO CL_RXD
RXD 50%
VOL
Figure 9. tMODE Test Circuit and Measurement
CANH VIH
TXD
TXD
RL CL VOD 0V
VOD(D)
CANL
0.9V
VOD
0.5V
0V
tTXD_DTO
Figure 10. TXD Dominant Timeout Test Circuit and Measurement

IOS 200 s
CANH
TXD
IOS VBUS
CANL VBUS VBUS

0V
or
0V
VBUS
VBUS
Figure 11. Driver Short-Circuit Current Test and Measurement

8 Detailed Description
8.1 Overview
The TCAN1044-Q1 meets or exceeds the specifications of the ISO 11898-2:2016 high speed CAN (Controller
Area Network) physical layer standard. The device has been certified to the requirements of ISO 11898-2:2016
and ISO 11898-5:2007 physical layer requirements according to the GIFT/ICT high speed CAN test specification.
The transceiver provides a number of different protection features making it ideal for the stringent automotive
system requirements while also supporting CAN FD data rates up to 8 Mbps.
The TCAN1044-Q1 conforms to the following CAN standards:
• CAN Transceiver Physical Layer Standards
– ISO 11898-2:2016 High speed medium access unit
– ISO 11898-5:2007 High speed medium access unit with low-power mode
– SAE J2284-1: High Speed CAN (HSC) for Vehicle Applications at 125 kbps
– SAE J2284-4: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 2 Mbps
– SAE J2284-5: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 5 Mbps
– ARINC 825-4 General Standardization of CAN (Controller Area Network) Bus Protocol For Airborne Use
– VeLIO (Vehicle LAN Interoperability and Optimization) CAN and CAN-FD Transceiver Requirements
• EMC requirements:
– SAE J2962-2 Communication Transceivers Qualification Requirements – CAN
• Conformance Test requirements:
– ISO 16845-2 Road vehicles – Controller area network (CAN) conformance test plan Part 2: High-speed
medium access unit conformance test plan

8.2 Functional Block Diagram

NC or VIO VCC
5 3
VCC or VIO
TSD 7 CANH
Dominant
TXD 1
time-out
6 CANL
VCC or VIO
STB 8 Mode Sele ct
UVP
VCC or VIO
RXD 4 Log ic Output MUX
WUP Mon itor
Low Power Rece iver
GND
Figure 12. Block Diagram

8.3 Feature Description

8.3.1 Pin Description
8.3.1.1 TXD
TXD is the logic-level signal, referenced to either VCC or VIO from a CAN controller to the device.
8.3.1.2 GND
GND is the ground pin of the transceiver, it must be connected to the PCB ground.
8.3.1.3 VCC
VCC provides the 5-V nominal power supply to the CAN transceiver.
8.3.1.4 RXD
RXD is the logic-level signal, referenced to either VCC or VIO, from the TCAN1044-Q1 to a CAN controller. This
pin is only driven once VIO is present.
When a wake event takes place RXD is driven low.
8.3.1.5 VIO
The VIO pin provides the digital IO voltage to match the CAN controller voltage thus avoiding the requirement for
a level shifter. It supports voltages from 1.7 V to 5.5 V providing the widest range of controller support.
8.3.1.6 CANH and CANL

These are the CAN high and CAN low differential bus pins. These pins are connected to the CAN transceiver
and the low-voltage WUP CAN receiver.
8.3.1.7 STB (Standby)

The STB pin is an input pin used for mode control of the transceiver. The STB pin can be supplied from either
the system processor or from a static system voltage source. If normal mode is the only intended mode of
operation than the STB pin can be tied directly to GND.
8.3.2 CAN Bus States

The CAN bus has two logical states during operation: recessive and dominant. See Figure 13 and Figure 14.
A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and
RXD pins. A recessive bus state occurs when the bus is biased to VCC/2 via the high-resistance internal input
resistors (RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins.
A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a
dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than
the differential voltage of a single driver.
The TCAN1044-Q1 transceiver implements a low-power standby (STB) mode which enables a third bus state
where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver. See
Figure 13 and Figure 14.

Feature Description (continued)
Normal Mode Standby Mode
CANH
Typical Bus Voltage
VDIFF
VDIFF
CANL
Recessive Dominant Recessive Time, t
Figure 13. Bus States
CANH
2.5V
A
RXD
Bias
Unit
B
GND
CANL
A. Normal Mode
B. Standby Mode
Figure 14. Simplified Recessive Common Mode Bias Unit and Receiver
8.3.3 TXD Dominant Timeout (DTO)

During normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local node
from blocking network communication in the event of a hardware or software failure where TXD is held dominant
longer than the timeout period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising
edge is seen before the timeout period of the circuit, tTXD_DTO, the CAN driver is disabled. This frees the bus for
communication between other nodes on the network. The CAN driver is reactivated when a recessive signal is
seen on the TXD pin, thus clearing the dominant time out. The receiver remains active and biased to VCC/2 and
the RXD output reflects the activity on the CAN bus during the TXD DTO fault.
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data
rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the
worst case, where five successive dominant bits are followed immediately by an error frame. The minimum
transmitted data rate may be calculated using Equation 1.
Minimum Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps (1)

TXD fault stuck dominant: example PCB failure or bad software Fault is repaired & transmission capability
restored
TXD (driver) tTXD_DTO

Driver disabled freeing bus for other nodes
Normal CAN communication %XV ZRXOG EH ³VWXFN GRPLQDQW´ EORFNLQJ FRPPXQLFDWLRQ IRU WKH ZKROH QHWZRUN EXW 7;' '72
prevents this and frees the bus for communication after the time tTXD_DTO.
CAN Bus Signal tTXD_DTO
Communication from other bus node(s) Communication from repaired node
RXD (receiver)
Communication from local node Communication from other bus node(s) Communication from repaired local node
Figure 15. Example Timing Diagram for TXD Dominant Timeout
8.3.4 CAN Bus Short Circuit Current Limiting

The TCAN1044-Q1 has several protection features that limit the short circuit current when a CAN bus line is
shorted. These include CAN driver current limiting in the dominant and recessive states and TXD dominant state
timeout which prevents permanently having the higher short circuit current of a dominant state in case of a
system fault. During CAN communication the bus switches between the dominant and recessive states, thus the
short circuit current may be viewed as either the current during each bus state or as a DC average current.
When selecting termination resistors or a common mode choke for the CAN design the average power rating,
IOS(AVG), should be used. The percentage dominant is limited by the TXD DTO and the CAN protocol which has
forced state changes and recessive bits due to bit stuffing, control fields, and interframe space. These ensure
there is a minimum amount of recessive time on the bus even if the data field contains a high percentage of
dominant bits.
The average short circuit current of the bus depends on the ratio of recessive to dominant bits and their
respective short circuit currents. The average short circuit current may be calculated using Equation 2.
IOS(AVG) = % Transmit x [(% REC_Bits x IOS(SS)_REC) + (% DOM_Bits x IOS(SS)_DOM)] + [% Receive x IOS(SS)_REC] (2)
Where:
• IOS(AVG) is the average short circuit current
• % Transmit is the percentage the node is transmitting CAN messages
• % Receive is the percentage the node is receiving CAN messages
• % REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• % DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current
This short circuit current and the possible fault cases of the network should be taken into consideration when
sizing the power supply used to generate the transceivers VCC supply.


8.3.5 Thermal Shutdown (TSD)
If the junction temperature of the TCAN1044-Q1 exceeds the thermal shutdown threshold, TTSD, the device turns
off the CAN driver circuitry and blocks the TXD to bus transmission path. The shutdown condition is cleared
when the junction temperature of the device drops below TTSD. The CAN bus pins are biased to VCC/2 during a
TSD fault and the receiver to RXD path remains operational. If the fault condition that caused the TSD fault is still
present, the junction temperature may rise again and the device enters a TSD fault again. The TCAN1044-Q1
TSD circuit includes hysteresis which prevents the CAN driver output from oscillating during a TSD fault. If there
is prolonged exposure to a TSD fault condition the device reliability could be affected.
8.3.6 Undervoltage Lockout

The supply pins, VCC and VIO, have undervoltage detection that places the device into a protected state. This
protects the bus during an undervoltage event on either supply pin.
Table 2. Undervoltage Lockout - TCAN1044-Q1

VCC Device State Bus RXD Pin
> UVVCC Normal Per TXD Mirrors Bus
< UVVCC Protected High Impedance High Impedance
Table 3. Undervoltage Lockout - TCAN1044-Q1V

VCC VIO Device State Bus RXD Pin
> UVVCC > UVVIO Normal Per TXD Mirrors bus
STB = VIO: Standby mode Biased to GND VIO: Remote wake request (1)
< UVVCC > UVVIO
STB = GND: Protected mode High impedance Recessive
> UVVCC < UVVIO Protected High impedance High impedance
< UVVCC < UVVIO Protected High impedance High impedance
(1) See Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
Once an undervoltage condition is cleared and the supply has returned to a valid level the TCAN1044-Q1
transitions to normal mode after the tMODE time has expired. The host controller should not attempt to send or
receive messages until the tMODE time has expired.
8.3.7 Unpowered Device

The TCAN1044-Q1 is designed to be an ideal passive or no load to the CAN bus if the device is unpowered. The
bus pins were designed to have low leakage currents when the device is unpowered, so they do not load the
bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains
operational.
The logic pins also have low leakage currents when the device is unpowered, so they do not load other circuits
which may remain powered.

8.3.8 Floating pins

The TCAN1044-Q1 has internal pull-ups on critical pins which place the device into known states if the pin floats.
This internal bias should not be relied upon by design though, especially in noisy environments, but instead
should be considered a failsafe protection feature.
When a CAN controller supporting open drain outputs are used an adequate external pull-up resistor must be
used to ensure that the TXD output of the CAN controller maintains adequate bit timing to the input of the CAN
transceiver. See Table 4 for details on pin bias conditions.
Table 4. Pin Bias

Pin Pull-up or Pull-down Comment
Weakly biases TXD towards recessive to prevent bus blockage or
TXD Pull-up
TXD DTO triggering
Weakly biases STB towards low-power standby mode to prevent
STB Pull-up
excessive system power
8.4 Device Functional Modes

8.4.1 Operating Modes
The TCAN1044-Q1 has two main operating modes; normal mode and standby mode. Operating mode selection
is made by applying a high or low level to the STB pin on the TCAN1044 device.
Table 5. Operating Modes

STB Device Mode Driver Receiver RXD Pin
High (recessive) until valid WUP
Low current standby mode with Low-power receiver and bus
High Disabled is received
bus wake-up monitor enable
See section 8.3.3.1
Low Normal Mode Enabled Enabled Mirrors bus state
8.4.2 Normal Mode

This is the normal operating mode of the TCAN1044-Q1. The CAN driver and receiver are fully operational and
CAN communication is bi-directional. The driver is translating a digital input on the TXD input to a differential
output on the CANH and CANL bus pins. The receiver is translating the differential signal from CANH and CANL
to a digital output on the RXD output.
8.4.3 Standby Mode

This is the low-power mode of the TCAN1044-Q1. The CAN driver and main receiver are switched off and bi-
directional CAN communication is not possible. The low-power receiver and bus monitor circuits are enabled to
allow for RXD wake-up requests via the CAN bus. A wake-up request is output to RXD as shown in Figure 16.
The local CAN protocol controller should monitor RXD for transitions (high-to-low) and reactivate the device to
normal mode by pulling the STB pin low. The CAN bus pins are weakly pulled to GND in this mode; see
Figure 13 and Figure 14.
In standby mode, only the VIO supply is required therefore the VCC may be switched off for additional system
level current savings.
8.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
The TCAN1044-Q1 supports a remote wake-up request that is used to indicate to the host controller that the bus
is active and the node should return to normal operation.
The device uses the multiple filtered dominant wake-up pattern (WUP) from the ISO 11898-2:2016 standard to
qualify bus activity. Once a valid WUP has been received, the wake request is indicated to the controller by a
falling edge and low period corresponding to a filtered dominant on the RXD output of the TCAN1044-Q1.

The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second
filtered dominant pulse. The first filtered dominant initiates the WUP, and the bus monitor then waits on a filtered
recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received the bus monitor
is waiting for a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon
reception of the second filtered dominant the bus monitor recognizes the WUP and drives the RXD output low
every time an additional filtered dominant signal is received from the bus.
For a dominant or recessive to be considered filtered, the bus must be in that state for more than the tWK_FILTER
time. Due to variability in tWK_FILTER the following scenarios are applicable. Bus state times less than
tWK_FILTER(MIN) are never detected as part of a WUP and thus no wake request is generated. Bus state times
between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP and a wake-up request may be
generated. Bus state times greater than tWK_FILTER(MAX) are always detected as part of a WUP, and thus a wake
request is always generated. See Figure 16 for the timing diagram of the wake-up pattern.
The pattern and tWK_FILTER time used for the WUP prevents noise and bus stuck dominant faults from causing
false wake-up requests while allowing any valid message to initiate a wake-up request.
The ISO 11898-2:2016 standard has defined times for a short and long wake up filter time. The tWK_FILTER timing
for the device has been picked to be within the minimum and maximum values of both filter ranges. This timing
has been chosen such that a single bit time at 500 kbps, or two back to back bit times at 1 Mbps triggers the
filter in either bus state. Any CAN frame at 500 kbps or less would contain a valid WUP.
For an additional layer of robustness and to prevent false wake-ups, the device implement a wake-up timeout
feature. For a remote wake-up event to successfully occur, the entire WUP must be received within the timeout
value t ≤ tWK_TIMEOUT. If not, the internal logic is reset and the transceiver remains in its current state without
waking up. The full pattern must then be transmitted again, conforming to the constraints mentioned in this
section. See Figure 16 for the timing diagram of the wake up pattern with wake timeout feature.
Bus Wake via RXD
Wake Up Pattern (WUP) received in t < tWK_Timeout
Request
Filtered Waiting for Filtered Waiting for Filtered

Dominant Filtered Recessive Filtered Dominant
Recessive Dominant
Bus
Bus VDiff
• tWK_FILTER • tWK_FILTER • tWK_FILTER • tWK_FILTER
RXD Filtered Dominant RXD Output
Bus Wake Via RXD Requests
Figure 16. Wake-Up Pattern (WUP) with tWK_TIMEOUT

8.4.4 Driver and Receiver Function

The digital logic input and output levels for the TCAN1044-Q1 are CMOS levels with respect to either VCC for 5 V
systems or VIO for compatibility with MCUs having 1.8 V, 2.5 V, 3.3 V, or 5 V systems.
Table 6. Driver Function Table

Bus Outputs
Device Mode TXD Input (1) Driven Bus State (2)
CANH CANL
Low High Low Dominant
Normal
High or open Hi-Z Hi-Z Biased recessive
Weak pull-down to
Standby X Hi-Z Hi-Z
ground
(1) X = irrelevant
(2) For bus state and bias see Figure 13 and Figure 14
Table 7. Receiver Function Table Normal and Standby Mode

CAN Differential Inputs
Device Mode Bus State RXD Pin
VID = VCANH – VCANL
VID ≥ 0.9 V Dominant Low
Normal 0.5 V < VID < 0.9 V Undefined Undefined
VID ≤ 0.5 V Recessive High
VID ≥ 1.15 V Dominant High
Low if a remote wake event
Standby 0.4 V < VID < 1.15 V Undefined
occurred
VID ≤ 0.4 V Recessive See Figure 16
Any Open (VID ≈ 0 V) Open High

9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application

The TCAN1044-Q1 transceiver can be used in applications with a host controller or FPGA that includes the link
layer portion of the CAN protocol. Figure 17 shows a typical application configuration for 5 V controller
applications. The bus termination is shown for illustrative purposes.
VIN VIN VOUT
5V Voltage
Regulator VCC
(e.g. TPSxxxx) VDD 3 CANH
7
Port x STB 8
CAN FD Controller TCAN1044V
RXD RXD 4
CANL
TXD TXD 1 6
5 2
NC GND Optional:
Terminating
Node Optional:
Filtering,
Transient and
ESD
Figure 17. Transceiver Application Using 5 V IO Connections
9.2.1 Design Requirements
9.2.1.1 CAN Termination

Termination may be a single 120-Ω resistor at each end of the bus, either on the cable or in a terminating node.
If filtering and stabilization of the common mode voltage of the bus is desired then split termination may be used,
see Figure 18. Split termination improves the electromagnetic emissions behavior of the network by filtering
higher-frequency common-mode noise that may be present on the differential signal lines.

Typical Application (continued)
Standard Termination Split Termination
CANH CANH
RTERM/2
CAN CAN
Transceiver RTERM Transceiver
CSPLIT
RTERM/2
CANL CANL
Figure 18. CAN Bus Termination Concepts
9.2.2 Detailed Design Procedures
9.2.2.1 Bus Loading, Length and Number of Nodes

A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus.
A high number of nodes requires a transceiver with high input impedance such as the TCAN1044-Q1.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading of
the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE J2284,
SAE J1939, and NMEA 2000.
A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the driver
differential output is specified with a bus load that can range from 50 Ω to 65 Ω where the differential output must
be greater than 1.5 V. The TCAN1044-Q1 family is specified to meet the 1.5-V requirement down to 50 Ω and is
specified to meet 1.4-V differential output at 45Ω bus load. The differential input resistance of the TCAN1044-Q1
is a minimum of 40 kΩ. If 100 TCAN1044-Q1 transceivers are in parallel on a bus, this is equivalent to a 400-Ω
differential load in parallel with the nominal 60 Ω bus termination which gives a total bus load of approximately 52
Ω. Therefore, the TCAN1044-Q1 family theoretically supports over 100 transceivers on a single bus segment.
However, for CAN network design margin must be given for signal loss across the system and cabling, parasitic
loadings, timing, network imbalances, ground offsets and signal integrity thus a practical maximum number of
nodes is often lower. Bus length may also be extended beyond 40 meters by careful system design and data rate
tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km with changes in
the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility
the CAN network system designer must take the responsibility of good network design to ensure robust network
operation.

Typical Application (continued)
Node n
(with termination)
Node 1 Node 2 Node 3
MCU or DSP
MCU or DSP MCU or DSP MCU or DSP
CAN Controller
CAN Controller CAN Controller CAN Controller
TCAN1044V-Q1
TCAN1044-Q1 TCAN1042-Q1 TCAN1043-Q1
RTERM
RTERM
Figure 19. Typical CAN Bus
9.2.3 Application Curves
VCC = 5 V VIO = 3.3 V RL = 60 Ω VCC = 5 V VIO = 3.3 V RL = 60 Ω
Figure 20. tPROP(LOOP1) Figure 21. tPROP(LOOP2)

9.3 System Examples

The TCAN1044-Q1 CAN transceiver is typically used in applications with a host controller or FPGA that includes
the link layer portion of the CAN protocol. A 1.8 V, 2.5 V, or 3.3 V application is shown in Figure 22. The bus
termination is shown for illustrative purposes.
VIN VIN VOUT
5V Voltage
Regulator VCC
(e.g. TPSxxxx) VDD 3 CANH
7
Port x STB 8
CAN FD Controller TCAN1044V
VIN VOUT
RXD RXD 4
CANL
1.8 V / 2.5 V / 3.3 V TXD 1 6
TXD 5 2
Regulator
(e.g. TPSxxxx) VIO GND
Optional:
Terminating
Node Optional:
Filtering,
Transient and
ESD
Figure 22. Typical Transceiver Application Using 1.8 V, 2.5 V, 3.3 V IO Connections
10 Power Supply Recommendations

The TCAN1044-Q1 transceiver is designed to operate with a main VCC input voltage supply range between 4.5 V
and 5.5 V. The TCAN1044-Q1V implements an IO level shifting supply input, VIO, designed for a range between
1.8 V and 5.5 V. Both supply inputs must be well regulated. A decoupling capacitance, typically 100 nF, should
be placed near the CAN transceiver's main VCC supply pin in addition to bypass capacitors. A decoupling
capacitor, typically 100 nF, should be placed near the CAN transceiver's VIO supply pin in addition to bypass
capacitors.

11 Layout
Robust and reliable CAN node design may require special layout techniques depending on the application and
automotive design requirements. Since transient disturbances have high frequency content and a wide
bandwidth, high-frequency layout techniques should be applied during PCB design.
11.1 Layout Guidelines

• Place the protection and filtering circuitry close to the bus connector, J1, to prevent transients, ESD, and
noise from propagating onto the board. This layout example shows a optional transient voltage suppression
(TVS) diode, D1, which may be implemented if the system-level requirements exceed the specified rating of
the transceiver. This example also shows optional bus filter capacitors C4 and C5.
• Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
• Use VCC and GND planes to provide low inductance. Note that high frequency current follows the path of
least impedance and not the path of least resistance.
• Decoupling capacitors should be placed as close as possible to the supply pins VCC and VIO of transceiver.
• Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize trace and via inductance.
• This layout example shows how split termination could be implemented on the CAN node. The termination is
split into two resistors, R6 and R7, with the center or split tap of the termination connected to ground via
capacitor C3. Split termination provides common mode filtering for the bus. See CAN Termination, CAN Bus
Short Circuit Current Limiting, and Equation 2 for information on termination concepts and power ratings
needed for the termination resistor(s).
• To limit current of digital lines series resistors may be used. Examples are R2, R3 and R4.
• Pin 1 is shown for the TXD input of the device with R1 as an optional pull-up resistor. If an open drain host
controller is used this is mandatory to ensure the bit timing into the device is met.
• Pin 8 is shown with R4 assuming the mode pin STB, is used. If the device is used in normal mode only, R4 is
not needed and the pads of C4 could be used for the pull down resistor R5 to GND.
11.2 Layout Example
STB
R4
VCC or VIO R1 GND

R5
TXD R2
GND
C4
GND R6
U1
D1
U1
J1
C3
TCAN1044(V)
C1
C2
VCC R7
C5
GND
RXD R3 VIO
C7
C6
GND
Figure 23. Layout Example

12 Device and Documentation Support
12.1 Documentation Support

12.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 8. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
TCAN1044-Q1 Click here Click here Click here Click here Click here
TCAN1044V-Q1 Click here Click here Click here Click here Click here
12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 7-Mar-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TCAN1044DRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1044
TCAN1044DRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1044
TCAN1044VDDFRQ1 ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 26SF
TCAN1044VDRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1044V
TCAN1044VDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1044V
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TCAN1044V-Q1 :
• Catalog: TCAN1044V
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCAN1044DRBRQ1 SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q1
TCAN1044DRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TCAN1044VDDFRQ1 SOT- DDF 8 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
23-THIN
TCAN1044VDRBRQ1 SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q1
TCAN1044VDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TCAN1044DRBRQ1 SON DRB 8 3000 367.0 367.0 35.0
TCAN1044DRQ1 SOIC D 8 2500 853.0 449.0 35.0
TCAN1044VDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0
TCAN1044VDRBRQ1 SON DRB 8 3000 367.0 367.0 35.0
TCAN1044VDRQ1 SOIC D 8 2500 853.0 449.0 35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDF0008A SCALE 4.000
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
C
2.95 SEATING PLANE
TYP
2.65
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
2.95
2.85 2X
NOTE 3 1.95
4
5
0.4
8X
0.2
1.65 0.1 C A B
B 1.1 MAX
1.55
0.20
TYP
0.08
SEE DETAIL A
0.25
GAGE PLANE
0.1
0 -8 0.6 0.0
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A SOT-23 - 1.1 mm max height
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP (2.6)
LAND PATTERN EXAMPLE

SCALE:15X
SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A SOT-23 - 1.1 mm max height
8X (1.05) SYMM
(R0.05) TYP
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRB0008J VSON - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
B 3.1
2.9 A
PIN 1 INDEX AREA

3.1
2.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1 MAX C
SEATING PLANE
0.05 0.08 C
0.00
1.75
1.55
(0.2) TYP
6X 0.65 (0.19)
4 5
9 SYMM
2.5 1.95
2.3
1
8
8X 0.36
0.26
PIN 1 ID
(OPTIONAL) SYMM 0.1 C A B
0.05 C
8X 0.5
0.3
4225036/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
(2.8)
(1.65)
8X (0.6) SYMM
8X (0.31)
1
8
6X (0.65)
SYMM 9
(1.95) (2.4)
(0.95)
(R0.05) TYP
4
5
(Ø 0.2) VIA
TYP (0.575)

EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX 0.07 MIN

ALL AROUND SOLDER MASK
ALL AROUND OPENING
METAL
EXPOSED METAL
EXPOSED METAL SOLDER MASK

OPENING METAL
NON- SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS 4225036/A 06/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
(2.8)
2X
(1.51)
8X (0.6) SYMM
8X (0.31)
1
8
2X
6X (0.65) (1.06)
SYMM
(1.95)
(0.63)
9
(R0.05) TYP
4
5
METAL
TYP

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED COVERAGE BY AREA
SCALE: 20X
4225036/A 06/2019
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated

TCAN1044-Q1 Automotive Fault-Protected CAN FD Transceiver: 1 Features 3 Description

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SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019

TCAN1044-Q1 Automotive Fault-Protected CAN FD Transceiver

• Available in SOIC (8), SOT23 (8) packages

automated optical inspection (AOI) capability VCC or VIO

2 Applications STB 8 Mode Sele ct

• Automotive and Transportation

– Advanced driver assistance system (ADAS) 4 Log ic Output MUX

Low Power Rece iver

SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com

Changes from Original (August 2019) to Revision A Page

• First public release of the data sheet .................................................................................................................................... 1

2 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: TCAN1044-Q1 TCAN1044V-Q1

www.ti.com SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019

5 Pin Configuration and Functions

DDF Package TCAN1044(V)-Q1

DRB Package TCAN1044(V)-Q1

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 3

SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com

6.2 ESD Ratings

6.3 ESD Ratings

6.4 Recommended Operating Conditions

4 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: TCAN1044-Q1 TCAN1044V-Q1

www.ti.com SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019

6.5 Thermal Characteristics

6.6 Supply Characteristics

6.7 Dissipation Ratings

Average power dissipation VCC = 5 V, VIO = 5 V, TJ= 27°C, RL = 60Ω, TXD

Average power dissipation VCC = 5.5 V, VIO = 5 V, TA= 125°C, RL = 60Ω,

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 5

SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com

Dissipation Ratings (continued)

6.8 Electrical Characteristics

Driver symmetry See Figure 6 and Figure 18, STB = 0 V, RL

6 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: TCAN1044-Q1 TCAN1044V-Q1

www.ti.com SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019

Electrical Characteristics (continued)

(1) VIO = VCC in non-V variants of device

6.9 Switching Characteristics

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 7

SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com

Switching Characteristics (continued)

8 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: TCAN1044-Q1 TCAN1044V-Q1

www.ti.com SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019

6.10 Typical Characteristics

VCC = 5 V VIO = 3.3 V RL = 60 Ω Temp = 25°C RL = 60 Ω

Figure 1. VOD(DOM) vs Temperature Figure 2. VOD(DOM) vs VCC

VCC = 5 V VIO = 3.3 V RL = 60 Ω VCC = 5 V VIO = 3.3 V RL = 60 Ω

Figure 3. ICC Standby vs Temperature Figure 4. IIO Standby vs Temperature

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 9

SLLSF17A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com

7 Parameter Measurement Information