CHAPTER-1

1. INTRODUCTION
1.1 Aim of the Project The aim of the project is FPGA implementation of Hierarchical Matched Filter on WCDMA systems. FPGA means Field Programmable Gate Arrays. The use of FPGA results in the reconfigurable nature of the system. The logic of the system can be modified by using FPGA. FPGA can produce high speed. Where as in ASIC the logic cannot be modified since they have fixed logic assigned to them. By this way ASIC is only used for single logic where as FPGA is used for multiple logics one after the other. Since FPGA is reprogrammable. 1.2 Background and motivation: In various standard forms, Third generation (3G) cellular systems are currently utilized .Among them, the types that are based on direct-sequence code-division multiple-access (DS-CDMA) technology, are IS-2000 [8] (North America) and Wideband CodeDivision-Multiple-Access [2], [8] (W-CDMA) (Europe and Japan). When compared to the second generation cellular systems, 3G will provide high data rate services with improved service quality. One of the major differences between these two is IS-2000 supports synchronous asynchronous base base stations stations. whereas W-CDMA allows depends unique on cell W-CDMA

identification using 512 scrambling codes [17], [16]. One of the most popular wireless communication systems are the Direct sequence spread spectrum (DSSS) systems, which are used for W-LAN, IS-95 and WCDMA because of low power density and resistance to multi path fading [9],[10].In these DSSS systems, code acquisition is obtained by using matched filters (MFs), as they provide high reliability and fast synchronization.

In a CDMA cellular system, the process of the mobile station searching for a cell and achieving code and time synchronization to its downlink scrambling code is referred to as cell search. The synchronization process in W-CDMA can thus be viewed as the five stage process of 1) Slot synchronization 2) Frame synchronization and scrambling code group identification 3) Scrambling code identification 4) Frequency acquisition 5) Cell identification. The frame structure is shown below figure 1.1
One frame (10ms)

One slot (0.67ms)

P-SCH

Power=P1

0.067ms
S-SCH

Power=P2

CPICH Power P3

1.1 Frame structure of UMTS

From the above figure 1.1,three channels will be present in the first three steps of the cell search procedure. In which the first channel known as Primary Synchronization channel (P-SCH) consists of 256 chips of the 2560 timing candidates present in the system. The second channel known as Secondary Synchronization

channel(S-SCH) consists of 15 P-SCHs and the third channel is known as CPICH consists of 960 candidates of which each S-SCH consists 64 scrambling codes(64*15=960). The combined goal of the first three stages is to deliver a reliable code- and time-candidate to the Frequency acquisition stage (stage 4) with low delay and low complexity. [16] The proposed work is implementing a hierarchical matched filter. This work is done to reduce the memory elements from 256 to 16. By this filter we can achieve high speed and low power since it is implemented using a Hybrid firm of Finite Impulse Response Filter. In this process maximum scrambling codes are accessible. 1.3 Objective: The thesis work focuses on the development of a reliable Hierarchical Matched Filter for WCDMA system to be used in the mobile station. The hierarchical matched filter should have following objectives: The objective lies in producing the maximum output for the respective input of the system. The filter should be applicable to wide range of scrambling codes, so that every call obtained from the mobile station can be identified. The filter should be easy to implement in any WCDMA systems. Review of other Hierarchical Matched Filters: In this Hierarchical Matched Filter design, the first matched filter receives the input data serially from the Base Station. Correlation over X1 (16 chip accumulation) is done before correlation is performed with X2(16 symbol accumulation). After 16 clock cycles, if the shift register 1 is filled the code is matched with the code applied to the taps of the matched filter. PSC sequence is represented by the tap coefficients in the matched filter which is same for all BSs. If the tap coefficients and the data match the

result of the shift register is high. In the same way for the shift register 2 present in the Hierarchical matched filter [11]. In this Hierarchical Matched Filter design, the correlation process is replaced by 2s complement addition/subtraction process. In this process after 16 clock cycles the 16 taps in the first stage are filled and the output of the first stage having 16-bits is given as the input to the second stage, whose output is obtained after 256 clock cycles. The final output mainly depends on the configuration bit of the hierarchical filter.If the configuration bit is zero the output of the FIR is given to the next stage, otherwise if the configuration bit is one the over sampled data is obtained at the final output. In this way the hierarchical matched filter operates in this circuit. 1.4 Thesis Outline: The remaining of the thesis is organized as follows Chapter 2: This chapter mainly builds up the evolution of the third generation systems from the analog form and it also gives the literature survey done for the project. Chapter 3: This chapter mainly gives the details of the third generation systems, CDMA design issues, WCDMA overview, specifications, and the description of the specifications Chapter 4: This chapter mainly gives the details of the architecture design units present in the system Chapter 5: This chapter gives the description of the design summary, wave forms and routing details. Chapter 6: This chapter gives the details of the concluding remarks and the future scope of the system.

CHAPTER-2

2. EVOLUTION OF THIRD GENERATION

The mobile radio communication industry was limited to the armed services, commercial and public organizations using private systems, and marine and aircraft communication before 1980s. Portable telephones were the first public mobile telephone introduced with in a limited range of single base station covering a small geography. 2.1 The Pioneer Phase (1921-1947): The pioneer experiments in land mobile communications were carried out in the early 1920s in Detroit. One way broadcasts were made to receivers in mobile police cars. Many problems were encountered in the design of reliable mobile receivers. In 1928 a Purdue University student was able to develop a receiver based on a super-heterodyne design that operated with reasonable success in the mobile environment. In the early 1930s mobile transmitters were developed, and the first two way mobile system was placed in operation by the Bayonne, New Jersey, police department. By 1934 there were 194 municipal police radio systems and 58 police radio stations serving more than 5000 police cars. Up to the early the early 1930s all mobile radio systems in operation used amplitude modulation (AM). In the late 1930s the Connecticut police department implemented the first two way frequency modulation (FM) mobile systems, which are resistant to the peculiar propagation problems. 2.2 The Initial Commercial Phase (1946-1968): The end of Second World War saw the expansion of mobile telephone serving to the commercial arena. Demand was strong, and the beginning of chronic spectrum congestion was soon

apparent. Technological improvements were oriented towards two principal goals: reducing of transmission bandwidth by channel splitting and introducing of automatic trunking or multiplexing systems. In 1949 the FCC officially recognized mobile radio as a new class of service. The number of users exploded from a few thousands in1940 to 86,000 by 1948 and about 1.4 million by 1963. FCC granted a license to the American Telephone and Telegraph Company (AT & T) to operate in ST. Louis. This system used three channels at 150 MHz. these channels were based on FM and utilized wide area architecture. A single powerful transmitter provided coverage to an area up to 50 miles or more from the base station. The first systems used operators to manually patch radio calls to the land telephones network. The original FM mobile telephone channels required 120 kHz of RF bandwidth to transmit 3-kHz voice band signals. By 1950 the FCC decided to split the original channels into 60 kHz channels. The FCC authorized 12 new mobile telephone channels in the ultrahigh frequency (UHF) band in1956.a bandwidth of 50khz was specified for these channels .by the early 1960s FM receiver technology has advanced and the channel bandwidth was reduced again to 30kHz. Other important technological developments after World WarII were the invention and application of automatic trunking or multiplexing of radio systems [5]. 2.3 Cellular, Wireless, Mobile, and Personal Communications Systems (1947-2010): 2.3.1 First Generation (1G) mobiles: In the early 1980s the first generation mobiles are invented and are based on analog cellular technology: 1G systems are based mainly on two systems: the American AMPS (Advanced Mobile Phone Service/System) and the Scandinavian NMT system (Nordic

Mobile Telephone). Although these systems were incompatible these analog systems provide important features: 1. A cellular structure for communication between the base station and mobile. 2. Frequency reuse amongst the cells. 3. Handover between cells as a mobile passes from one to the other. 4. Full duplex communications. 5. Roaming across the system. 6. Dedicated control channels for setting up calls. The transmission quality of these systems is left much to be desired. 2.3.2 Second Generation (2G) mobiles: Second generation systems were introduced of the 20 century. 2.3.2.1 GSM: GSM (Global System for Mobile Communication) was the first digital protocol and system. Due to its improved speech quality with a uniform international standard and also the usage of single number around the world, GSM became popular. The standardization work started by the CCITT and continued by ETSI, led to the GSM standard in 1991.GSM uses TDMA (Time Division Multiple Access) in its air interface. On the RF air interface GSM uses GMSK (Gaussian Modulated Shift Keying) technique. 2.3.2.2 TDMA: Other digital cellular systems similar to GSM were implemented in the early 1990s. In the United States, TDMA IS136 (Interim Standard-136) was introduced in the 1994 and was utilized till now. This was an easy transition from AMPS to TDMA IS136, resulting in a tripling of network capacity. PDC (Personal Digital Cellular) is a TDMA variant that was developed uniquely in Japan. 2.3.2.3 CDMA, IS-95A: Spread spectrum communications principles are used by Code Division Multiple Access (CDMA) technology. A system of digital coding provides access to the system rather than TDMA. The original CDMA standard for mobile in the late 80s

networks was completed in 1993 and is called Interim Standards 95A (IS-95A). CDMA-IS95A also referred as cdmaOne. Have ten times the capacity of 1G AMPS and supports up to 22 voice channels and data rates of up to 14.4 kbps, interspersed in a 1.25 MHz frequency band. 2.3.3 Interim Generation (2.5G): In order to accommodate the growing demand for Internet applications, it was found that the circuit-switched infra-structure needed to migrate to a packet-switched infra-structure. 2.3.3.1 GPRS (Global Radio Packet Services): GPRS was initially released in 1997 and was specified to create a sound foundation for packet switching in GSM networks. GPRS networks offer high data rates for mobile users by dynamically allocating multiple channels. GPRS is the first step in enhancing the GSM core network in preparation for UMTS (Universal Mobile Telecommunications Services). 2.3.3.2 CDMA, IS-95B: CDMA, IS-95B give subscribers new packet-switched data services at speeds up to 64 kbps in addition to the existing voice services. 2.3.4 Third Generation (3G) mobiles: In effort to coordinate worldwide migration to 3G mobile networks, evaluated 1999. The most important IMT-2000 proposals were UMTS (Universal Mobile Telecommunication System), cdma2000 (as the IS-95 successor), and EDGE. TS-CDMA (Time Synchronous CDMA) is a 3G specification that is being considered in China. A 3G network supports data services at transmission rates greater than 144kbps in mobile environment and greater than 2Mbps in fixed environment [20]. the and ITU (International Telecommunications proposals as Union) IMTaccepted17 different

2000(International Mobile Telecommunication 2000) standards in

2.4 Comparison of Various generations: Comparison of various generations of mobile communications systems shown in Table 2.1. Table 2.1 Comparison of various generations Generatio n First Forms Analog Type 1)AMPS 2)NMTS Second Digital 1)GSM 2)TDMA 3)CDMA, Interim Digital IS-95A 1)GPRS 2)CDMA, Third Digital IS-95B 1)EDGE 2)CDMA200 0 3)WCDMA 5MHz 144kbps for mobile fixed environmen trespectivel y 2.5 Spread Spectrum: The term spread spectrum (SS) has been used in a wide variety of military and commercial systems. In spread spectrum systems each information signal requires significantly more radio frequency (RF) bandwidth than a conventional modulated signal. Spread spectrum is a technique whereby the modulated waveform is modulated (spread) a second time in such a way as to generate an expanded-bandwidth signal that does not significantly interfere with other signals. Bandwidth expansion is achieved by a second and 2 Mbps for 1.25MHz 64kbps Frequency band Frequency among the 14.4kbps cells 1.25MHz Data rates <10kbps

modulation means, a means that is independent of the information message. It is useful in improving interference rejection, code division multiplexing for code division multiple access(CDMA),low density power spectra for signal hiding, high-resolution ranging, secure communications, anti-jam capability , increased capacity and spectral efficiency in some mobilecellular personal communications system (PCS) applications , degradation of performance as the number of simultaneous users of an RF channel increases , lower cost of implementation and readily available IC components Direct-Sequence Spread Spectrum: The digital binary base band information, d(t) also known as non return to zero (NRZ) data , having a source bit rate of fb =1/ Tb , is phase shift key (PSK) modulated in the first modulator. To illustrate the fundamental concepts, we assume a simple unfiltered, constantenvelope binary PSK modulation. The modulated binary PSK signal s(t) is in figure 2.1 s(t)= 2P d(t)cos t s IF (2.1) From equation 2.1, d (t) is an unfiltered binary signal having two states +1 or -1, IF is the carrier frequency, and Ps is the corresponding carrier power. The DS-SS transmitter is shown below figure 2.1 Transmitter antenna s(t)= Base band d (t) Information rate PSK modulator IF carrier A cosIFt RF frequency Spreading synthesizer signal function g (t) PN-generator 10 Up converter (U/C) Power amplifier

Figure 2.1 DS-SS transmitter with PSK modulation with spreading. The spreading signal g(t) is a pseudo noise (PN) signal having a chip rate of fc =1/ Tc . The binary PSK (BPSK) modulated DS-SS is given by v(t)= g(t)s(t) 2P g(t)d(t)co t = s s 0 (2.2) The intermediate frequency (IF) signal is up converted by an RF synthesizer to the desired transmission frequency. In this 0 corresponds to the IF frequency IF or to the up converted RF RF . The spread spectrum signal g(t)s(t) is up converted to the desired RF frequency as shown in equation 2.2. The up conversion and the down conversion process is a practical requirement in most system applications. The combined received signal r (t) is given by M r(t)= g (t) (t)+ I(t)+ n(t) s i i i =1 (2.3) From equation 2.3, M is the number of simultaneous users, g (t) is the spreading function or PN code of the i- th i transmitter/receiver pair. s i (t) is the modulated signal, I (t) is interference (deliberate or self-noise), and n(t) is AWGN.The DS-SS receiver is shown in below figure 2.2. Down converter (D/C) BPF RF frequency Despreading synthesizer signal (PN)

LNA BPF

PSK Demodulator

BB Data out Figure 2.2 DS-SS receiver with PSK demodulation with despreading. 11

From the receiver end of figure 2.2, the intended user will have a synchronized gi (t) dispreading function, which is the same PN sequence as that of the corresponding transmitter. The despreading signal is PSK modulated. In the basic treatment of spread-spectrum systems, binary PSK modulation/demodulation is assumed. Other modulation methods such as MSK, GMSK, GFSK, 4FM, FBPSK, and FQPSK have also been implemented in spreadspectrum systems. If the chosen set of PN spreading waveforms is not crosscorrelated, then after despreading only the desired modulated waveform s i (t) remains. All other waveforms are not correlated and are effectively spread over a much wider bandwidth than that of the final demodulated bandwidth. Processing gain, G p or process gain is the relation of output and input signal-to-noise (S/N) or signal-to-interference (S/I) ratio. Thus processing gain G p is defined by G = (S/N) : (S/N) p 0 i The process gain available is frequently estimated by the following rule: BW BW BW RF RF RF G =processing gain= = = p BW R f mod info b (2.4) BW RF is the RF bandwidth and

As shown in equation 2.4,

BW mod is the modulated signal bandwidth. This bandwidth equals R f info = b = bit rate of the base band signal if the spectral efficiency

is 1b/s/Hz [5]. 12

PN sequence I channel Base band filter

r 90

r (t)

D PN sequence Q channel

Base band filter Oscillator

Figure 2.3 Modulator and scrambler of offset QPSK quadrature modulated cross correlated CDMA systems Form the above figure 2.3, PN sequence is applied to the modulo 2 adder and the in phase is applied to the filter which is previously mixed with the receiver signal, this signal is correlated with the oscillator and the similar process occur at the quadrature signal but at the correlator the signal is shifted by 90, so that the original signal is obtained by the combination of the two signals 2.6 Digital Filter: A digital filter is a circuit or algorithm used to generate the desired digital data from the filter input signal spectrum. Digital filter is mainly a difference equation with frequency response, system function. Digital filters are of two types having finite impulse response and infinite impulse response respectively. An N tap direct form Digital Matched filter is expressed as follows

13

n 2 y[k]= c x[k i] i i=0 Input

(2.5)

D H0 H1

D H2

D Hm-2 Hm-1

Output

Figure 2.4 Direct form FIR filter

From the above Figure 2.4, the value of H represents the value of c in equation 2.5,which is the reference coefficient. The output value of the equation2.4 is obtained by multiplying the reference coefficient with the previous sample input and summing the entire data. An N tap Digital Matched filter in the Transposed form is expressed as follows. the figure of transpose form is shown in figure y[k]= v [k] n v [k] = c x[k]+ v [k 1],1< i n i n 1 i 1 v [k]= c x[k] 1 n 1 (2.6) Input Hm-2 D D Hm-1

H0 D Output

H1 D

H2

Figure 2.5 Transpose form FIR filter From the above figure 2.5 vi [k] represents the intermediate values of the output y[k].Based on the results of equations 2.6, the H signal is represented by the c signals in the equation. Primarily

14

the output of the transpose form is equal to the input voltage. The intermediate values depend on the reference coefficients and the intermediate inputs present in the system. Hybrid form is mainly the combination of the direct form FIR and the transpose form FIR. Hybrid form is of two types i) Hybrid form-1 ii) Hybrid form-2 Hybrid form-1: Hybrid form-1 is formed when the FIR mainly consists of the direct form FIR filter and the minor part is compensated by the transposed form FIR .The figure for Hybrid form 1 is shown in 2.6 Input D H1 H2 D Output Figure 2.6 Hybrid form-1 FIR filter D D Hm-2 D Hm-1

D H0

From the figure 2.6, data samples are transmitted into the FIR filter in which the three multiples are only transpose form based on the formula (N-1)/n, where N is the total number of coefficients and n is the number of taps. Hybrid form-2: Hybrid form-2 is formed when the FIR mainly consists of the transpose form FIR filter and the minor part is compensated by the direct form FIR. The Hybrid form II is shown in figure 2.7

Input

D H0 D H1 D H2 D

D Hm-2 D Hm-1

Output

15

Figure 2.7 Hybrid form-2 FIR filter From the figure 2.7, data samples are transmitted into the FIR filter in which the three multiples are only transpose form based on the formula (N-1)-(N-1)/n, where N is the total number of coefficients and n is the number of taps. 2.7 Literature report: Third generation (3G) cellular systems are currently being standardized in various standardization bodies. Among the 3G cellular systems considered, IS-2000 and (Wide band Code Division Multiple Access (W-CDMA) are both based on direct sequence code division multiple access (DS-CDMA) technology [15]. WCDMA is a form of wideband Direct Sequence Code Division Multiple Access (DS-CDMA) system, which means that the user information bits (symbols) are spread over a wide frequency bandwidth by multiplying the user data bits with a spreading code sequence of chips [11]. WCDMA permits continuous transmission from many users to the same base station on the same carrier frequency at the same time. In WCDMA, a common sequence of 256 chips called the Primary Synchronization Channel (P-SCH) is transmitted periodically by all cells to assist the terminal to locate the slot boundary, which then leads to cell identification following the multi-stage cell search procedure. The cell (base station) in WCDMA is identified by its downlink scrambling code. There are 512 primary downlink scrambling codes grouped into 64 code groups, each with 8 member codes. These codes are based on length 218 - 1 Gold sequences truncated to length 38400, which corresponds to one frame of chips occupying a 10 msec interval at a chip rate of 3.84 Mchips/sec[15]. A three-step hierarchical cell search process has been introduced in the Universal Mobile Telecommunications Systems

16

(UMTS)

standard

that

is

supported These

by include

several the

auxiliary Primary

synchronization

channels.

Synchronization Channel (P-SCH), the Secondary Synchronization Channel (S-SCH), and the Common Pilot Channel (CPICH). Stage 1 performs slot synchronization, Stage 2 performs frame synchronization and scrambling code group identification, and Stage 3 acquires the cell-specific scrambling code . The performance of cell search impacts the perceived switchon delay (initial search), stand-by time (idle mode search), and link quality (active mode search), and thus is important to MS design. . The decision based on observation may be unreliable when the signal to noise ratio is low and fading is severe [15]. In Universal Mobile Telecommunications Systems (UMTS) matched filter is used to detect the initial synchronization sequence of 256 chip periods, common to all users. In this matching filter the 256 chip is divided in to two stages having 16 registers each. The correlated output at the first stage is given to the second stage. In this way, after 256 clock cycles the output at the second stage is obtained. In the matched filter, the correlation is done by the adder/ subtractor circuit. In UMTS, the minimum high and low periods are determined by what is termed a "chip rate, currently specified at 3.84 MHz, though this frequency is adjustable to 2 times and 4 times this rate in the future. 2.8 CDMA design issues 2.8.1 Band width: An important design goal for all the third generation proposals is to limit spectral emission to a 5MHz dual-sided band. There are several reasons for choosing this bandwidth.

17

The main targets of third generation systems are achieved within 5MHz bandwidth with reasonable coverage with data rates of 144kbps and 384kbps. Limited spectrum allocation is due to the lack of spectrum calls; hence the system is deployed with existing frequency bands. When compared to narrower bandwidths, the 5MHz bandwidth improves the receivers ability to resolve multi path increasing diversity and improving performance. 2.8.2 Chip rate: Chip rate depends mainly on pulse shaping, spectral deployment scenarios, desired maximum data rate and dual-mode terminal implementation. Backward compatibility with GSM and PDC has been selected while selecting WCDMA chip rate. Minimum channel separation for non over lapping carriers is given by f min = 4.096(1+ .22) = 4.99712MHz 2.8.3 Multirate: Multirate design means multiplexing different connections with different quality of service requirements in a exible and spectrum efficient way. Multiple services belonging to the same session can be either cod multiplexed or time multiplexed. The time multiplexed can reduce the peak to average power transmissions by avoiding multi code paths. Parallel services are provided separately to treat channel coding or interleaving. 2.8.4 Spreading and modulation solutions: The spreading modulation can be either balanced or dual channel QPSK. In balanced QPSK the same data is split into I and Q channel, while in the dual channel QPSK, spreading the symbol along the I and Q channels are independent of each other. In the forward link, QPSK data modulation is used in order to preserve the code channels and allow the use of same orthogonal

18

codes. While in the reverse link, BPSK and the balanced QPSK modulations are used with the same orthogonal codes. 2.8.5 Coherent detection in the reverse link: Compared to the non-coherent detection used by the second generation CDMA systems, the performance improves by 3db while using coherent detection in the reverse link. A pilot signal is required for coherent detection. 2.8.6 Fast Power Control in Forward Link: The impact of the fast power control in the forward link is twofold; it improves the performance in a fading multi path channel. It increases the multi user interference variance within the cell since the orthogonality between users is not perfect due to multi path fading 2.8.7 Additional pilot channel in the forward link for beam forming: An additional pilot channel on the forward link that can be assigned to a mobile or to a group of mobiles enables deployment of adaptive antennas for beam forming .since the pilot channel used for channel estimation need to go through the same path as data signal. 2.8.8 Seamless Inter frequency Handover: For third generation systems, Hierarchical cell structures (HCS), constructed by overlaying macro cells on top of the smaller micro or pico cells have been proposed to achieve high capacity. The cell belongs to different cell layers with be in different frequencies and thus an inter frequency handover is required. Different methods have been proposed to obtain multiple carrier measurements. 2.8.9 Multi user Detection: It is easier to apply multi user detection in a short spreading code since cross-correlation do-not change every symbol with long spreading codes. In the sense, CDMA schemes will all use long

19

spreading codes. Due to complexity, MUD is best suited in the reversed link. Therefore a simpler interference suppression scheme could be used in the mobile station.

2.8.10 Transmit Diversity: The forward link performance can be improved in many cases by using transmit diversity. For direct spread CDMA schemes, this can be performed by splitting the data stream and spreading the two streams using orthogonal sequences or switching the entire data stream between two antennas. For multi carrier CDMA, the different carriers can be mapped into different antennas [4]. 2.9 Advantages of CDMA for cellular networks: 2.9.1 Frequency diversity: Because the transmission is spread out over a large bandwidth, frequently-dependent transmission impairments, such as noise bursts and selective fading have a less effect on the signal. 2.9.2 Multi path resistance: In addition to the ability of DS-SS to overcome multi-path fading by frequently diversity, the chipping codes used for CDMA not only exhibit low cross correlation but also low autocorrelation. Therefore, a version of the signal that is delayed by more than one chip interval doesnt not interfere with the dominant signal as it is interfered other multi path environments. 2.9.3 Privacy: Because spread spectrum is obtained by the use of noiselike signals, where each user has a unique code, privacy is inherent. 2.9.4 Graceful degradation: With FDMA or TDMA, a fixed number of users can access the system simultaneously. However, with CDMA, as more users access the system simultaneously, the noise level and hence the error rate increases; only the system simultaneously, the noise level and

20

hence the error rate increases; only gradually does the system degrade to the point of an unacceptable error rate [15].

Chapter-3

3. WIDE BAND CODE DIVISION MULTIPLE ACCESS

3.1 Disadvantages of second generation: Second generation systems IS-136 and the global system for mobile communications (GSM) are based on time division multiplexing (TDMA) and IS-95 in U.S is based on code division multiplexing (CDMA).This 2G technologies suffered a number of limitations that included: 1. Non-interoperability between the standards. 2. The subscribers demands for faster non voice services with its low bit rate, while on move could not be met. So, the Third generation systems (3G) have evolved to solve the problems that have occurred in (2G) by promising global roaming, high data rates and multimedia applications .3G services which are W-CDMA and IS-2000 based on the direct sequence spread spectrum technology. 3.2 Performance of direct sequence spread spectrum: One of the advantages of spread-spectrum (SS) systems is the ability of these systems to reject interference than otherwise might prohibit useful communications. Thermal Noise not Rejected by Spread-Spectrum Techniques Let us assume a simple case where an unfiltered hard-limited BPSK modulator has instantaneous signal state changes between +1 and -1 at a rate of fc = 1/T c .in the overall spread spectrum, the

21

base band data signal d (t) is twice multiplied by the spreading despreading PN sequence g (t).Since g2[t]=1, as 1 2 =1 and (-1) 2 =1, there is no effect on the received despread output signal. The thermal noise or AWGN is introduced in the receiver part of the channel by a low noise amplifier and down converter subsystems. AWGN is a wide-bandwidth noise, and its probability density function is approximately Gaussian. Polarity reversal has no impact on the power spectral density or the probability density function of the AWGN .Hence we conclude the spreading-despreading operation doesnt affect the signal and doesnt affect the spectral and probability density function. So the probability of error P e , performance of the spread spectrum systems in an AWGN-controlled E channel, is the same as the BER=f ( b N ) performance of the 0 modulated demodulated system, without spread-spectrum. BER= P e =erfc/2 From equation 3.1, C=Average power of received carrier E b =C T b =Average energy of received carrier N o =Noise density E b =Unit bit duration Narrowband interference Rejection Interference Rejection: A coherent BPSK has been designed at the University of California, UC Davis. The PSK modulation has no filters; it is an infinitebandwidth or unfiltered BFSK transmitter. The demodulator has a very simple postdemodulation roofing filter to remove the second and higher order carrier product from the base band signal. In this a fourth order Butterworth low pass filter having 30kHz is used. Eb N0 (3.1)

22

Wideband

interference

Rejection:

Wideband

interference

reduction has a physical mechanism similar to that for narrow band interference. The desired signal is spread in the transmitter and is despread in the receiver. Thus the total desired signal energy is reduced, that is collapsed, to the bandwidth of the demodulated bandwidth. This spectral collapsing occurs only for the desired signal, since the transmitted PN sequence gk (t)is correlated in the receiver by the same sequence. The wideband interference is by multiplication with an independent gL (t) PN spreading signal. In the receiver the gk (t). gL (t) product has a very wideband spectrum. It is filtered by the relatively narrowband demodulator filter, thus only an fraction of the wideband interference reaches the demodulator output [5] 3.3 WCDMA system overview: 3.3.1: IMT 2000: The main feature of this system is its ability to perform file transfers over packet data connections capable of providing 144kbps for high mobility, 384kbps for restricted mobility and 2Mbps in an indoor office environment. IMT 2000 employs a quantitative billing system by volume of data transmitted, and can holds bill amounts lower when sending email messages than in circuit switching. It may also be said to be a communication service fit for cellular mobiles, capable of immediately resuming data transmission when radio signals are interrupted. 9.6kbps would be sufficient for data volumes of short messages. 3.3.2: Frequency of IMT-2000: At WARC (current WRC: World Radio Conference) held in 1992, it was agreed to use 230 MHz as the frequency band of IMT-2000. The band varies from (1,885~2.025MHz/2,110~2,200MHz). In Japan and Europe, the two 60MHz bands of 1920~1980MHz and 2,110~2,170MHz are allocated. In the U.S., it is presumed that 23

the 1.9MHz band, currently allocated for PCS, will be used. The allocation of frequency varies form country to country depending on their unique conditions. PCS: Personal Communication Service. A personal mobile communication service is operating in the U.S.A at1.9GHz band. WRC-2000 subscribers by held the in 2000 year proposed a additional result, the frequency 800MHz (2,500~ allocations, agreeing on the future demand forecast of 200 million 2010.As (806~960MHz), 1.7GHz(1,710~1,885MHz) and 2.5GHz 3rd Generation

2,690MHz) bands were added for new frequency allocation. 3.3.3 WCDMA vs. cdma2000: The cellular

transmission speed of maximum 2Mbps requires a 5MHz frequency band. In the U.S.A., however, circumstances surrounding the radio frequency administration did not permit a new allocation, lead to the introduction of cdma2000. cdma2000 also known as MC (Multi-carrier) CDMA, since the down stream 3,75MHz composed of the three 1,25MHz bands from cdmaOne. According to the introduction of 1x MC, which achieves the frequency of 144Kbps in one frequency band alone, makes cost reduction and quick service area expansion possible. cdma2000 using 3 frequency bands are referred to as 3x, and the type using only one frequency as 1x. MC-CDMA, 1xMC, 1x are the technologies of cdma2000. 1x MC services with a bandwidth of 64kbps uplink and 144kbps downlink are placed in the metropolitan areas since 2002[19].the below table gives the comparison of WCDMA ,1xCDMA2000 and 3xCDMA2000

Table 3.1 Comparison of WCDMA, 1xCDMA2000 and 3 x CDMA2000

24

Access

WCDMA Direct spread

1x cdma2000 Multi carrier 1.2288Mcps Sync Common pilot Simple

3x cdma2000 Multi carrier 1.2288Mcps Sync Common pilot Simple

method Chip rate 3.84Mcps Inter BTS Async/Sync Sync Pilot Common pilot

structure RF resource Simple managemen t MS design Data speed Simple ~2Mbps

Simple ~144kbps

Simple ~2Mbps

(5MHz/carrier) (1.25MHz/carrier) (1.25MHz/carrierx3) 3.4 WCDMA Overview The RF interface In older analog FDMA systems, the user occupies one channel for transmit and one channel to receive the duration of phone call. These transmitter and receiver channels are busy until a call has been completed. TDMA systems improve their capacity by subdividing their bandwidth into time slots .In this way multiple users can use the same duplex pair simultaneously. But compared to FDMA and TDMA, CDMA and WCDMA use a much broader bandwidth by dividing the users into codes. All users transmit at the same time and multiple users share the same frequency carrier. Frequency reuse: Frequencies are only duplicated with a certain pattern in traditional cellular systems where frequency reuse is used. This reduces the likelihood of interference between two neighboring cell sites using the same channel. When same frequency is used, CDMA and WCDMA take a different approach. In the case of CDMA, a Pseudo Noise (PN) offset separates the forward links from each other rather than frequencies. In the similar way, Scrambling Codes separates the forward links from each other in the WCDMA.

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3.5 WCDMA specifications: In CDMA mobile communications, data are modulated by unique digital codes called PN (Pseudorandom noise) and spread before transmitted. The PN waveform is digital codes sampling values 1 at random and the signal speed if referred to as Chip Rate and is denoted as cps. The chip rate in cdmaOne is 1.23Mcps and it means that the phase of the data or control signals (9.6K or 14.4Kbps) shifts 1,230,000 times per second. cdmaOne are in them selves digital data and are shown in 1s and 0s. The phase is unchanged if the value of the PN sequence and signal value are the same. The phase is shifted by 180, if the value of the PN sequence and the signal are opposite in sign. Error control is done by channel bit and automatic retransmit request. By using random bit sampling and channel bit as part of spreading the spectrum, WCDMA benefits from the merits of spread spectrum in addition to codification merits derived from the use of channel bits. The below table 3.2 gives the specifications of WCDMA Table 3.2 WCDMA (IMT-DS) SPECIFICATIONS Multiple Access Method Duplexing Method Inter-cell Synchronization Bandwidth Chip rate Carrier spacing Frame length units Data Modulation Multi-rate concept Maximum data rate Channel coding DS-CDMA (DS: Direct Spread) FDD/TDD(Frequency Division Duplex/Time Division Duplex) Asynchronous 5MHz 3.84 Mcps Flexible with 100/200 KHz carrier raster 5/10/20 Downlink: QPSK, Uplink: BPSK Variable spreading factor and/or multi-code 2 Mbps (indoor)/384kbps(mobile) Channel coding(R=1/3 or ,k=9) Turbo code for high data rate

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W-CDMA signal spreading: Unlike TDMA, RF channel allows utilizes the entire bandwidth present in the W-CDMA systems .In this system, code channels separation is accomplished by digital coding individual channels, not by frequency separation. The carrier frequency and the code identify the channel in this process. WCDMA specifications allow 3.84MHz for a signal bandwidth. We take a user data rate of 9.6kbps per channel .At a data rate of 9.6kbps, the data would normally need approximately 10 kHz of spectrum .the data is then spread which is running at a rate of 3.84Mbps code rate. The resulting spreading codes are called chips and the resulting transmitted spread rate is 3.84Mcps. Spreading code in WCDMA: In WCDMA, spreading codes are added in two steps, one channelization codes with repeated cycles of symbol lengths, and the other scrambling code with lengths with cycles much longer than the symbol length. The spread signal and correlation in the WCDMA is shown in figure 3.1

Encoding, interleavin g

Digi tal filte

r BPF BPF

Deinterleave , decode

(OVSF) Scrambling Carrier

(OVSF) Scrambling Carrier

Figure 3.1 Signal Spread and Correlation in the WCDMA base Station In the above figure 3.1 BPF represents a band pass filter, D is the data in the WCDMA system the scrambling code is correlated with the carrier which is again correlated with the signal that is encode and interleaved. The obtained signal is passed through a band pass filter of 3.84MHz bandwidth. The obtained signal at the mobile station is passed through another BPF which of the same

27

band with to obtain the data signal which also includes noise signal. And the process is similar to the process occurred at the base station in the mobile station .But digital filter is added to gain the maximum signal at the mobile station.

3.6 Channels and codes: In WCDMA, each user is identified by a unique code which consists of scrambling code and an OVSF (Orthogonal Variable Spreading Factor). The scrambling code is mixed prior to the output of a base station or an output of a subscribers mobile unit. Each base station sector is identified by a unique scrambling code and may also be transmitting multiple code channels (other mobile units) at the same time. 3.7 Orthogonal Coding, Spreading and Correlation: W-CDMA uses a variable length code (4 to 512). The length of the code is known as spreading factor. Any mobile phone that tries to demodulate the received signal from the transmitter using the wrong orthogonal code would interrupt the information as noise. The OVSF codes can be reused by each base station and mobile station within the same location. Scrambling codes are not orthogonal and are a source of interference. 3.8 Coding: Two binary sequences of equal length are said to be orthogonal, if their result in an ex-or operation .Resulting in an equal number of 1 and 0 bits in the output. 3.9 Spreading:

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Orthogonal codes are used to spread a user data sequence, as a digital voice or actual data. Spreading can be explained in two steps: 1st step: Channelization Code: Variable Rate Spreading 2nd step: Scrambling code Fixed Rate Spreading (3,840 Kchips) Function of spreading code (Down link): In downlinks, scrambling codes are used to identify cells, and channelization codes to identify mobiles. Function of spreading code (Up link): In uplinks, scrambling codes are used to identify mobiles, and channelization codes are used to identify channels within the mobiles [20]. 3.10 Pseudo-Noise Sequences Definitions and System Requirements The major task of the pseudo noise (PN) sequences used in wireless digital or personal communications SS-CDMA systems are the following: 1. Spreading the bandwidth of the modulated signal to the largest transmission bandwidth. 2. Distinguishing between the different user signals utilizing the same transmission bandwidth in a multiple access. The sequences need special correlation properties, to meet these properties. Autocorrelation R a ( ) , in general is defined by the integral R

( ) = a

f(t)f(t )dt

(3.2) It is a measure of a similarity between a signal f (t) and a second time shifted replica of itself. The autocorrelation function is

29

a plot of autocorrelation over all shifts (t-) of the f (t) signals as shown in equation 3.2. Cross-correlation R c ( ) , is defined as the correlation between two different signals f (t) and g (t) and is given by R f(t)g(t )dt

( ) = c

(3.3)

In the known wireless communications systems, the spreading signals are binary digital PN codes. Autocorrelation and cross correlation of code sequences are obtained by computing the number of agreements (A) minutes the number of disagreements (D), when the codes are compared bit by bit for every discrete shift in the field of interestas shown in equation 3.3. The single sharp peak in the autocorrelation function at the time shift =0 is a desired property and supports an easy receiver synchronization. If the sequence is repeated on a periodic manner after N-chips, we get a pseudo-noise (PN) or pseudo random typed of sequence. For these PN sequences, we obtain a periodic autocorrelation function. Theoretically, a zero cross-correlation is maintained by every set of orthogonal spreading signals .However, in practical wireless systems one has to design for easy, coherent generation of the PN sequences, on both the transmitter and the receiver sides. The best-known, best-described PN sequences are maximallength sequences (m-sequences) .they are suited for singleuser spread spectrum systems and were widely used in military applications. Because of the cross correlation demands, Gold sequences, Kasami-sequences, or Walsh sequences are more interesting for cellular or personal communication CDMA systems. Some times they are combined with m- sequences. 3.10.1 m-sequences:

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In this maximum length linear codes or maximum length shift register sequences are described, since these codes are still of importance in digital communications and in spread spectrum and ranging systems. The hardware implementation of a PN-sequence generator and corresponding correlator or matched-data filter receiver is shown in figure. The generator contains type D flip-flops and is connected so that each data input except D 0 is the Q output of the preceding flip-flop. Note all Q flip-flop outputs need to be connected to the parity generator. The number of flip-flops L and the selection of which flip-flop outputs are connected to the parity generator determine the length and the characteristics of the generated PN sequences. The parity generator provides an output logic 0 when an even number of inputs are at logic 0 and generates logic 1 output when an odd number of inputs are at logic 1 state. Sequence length: For maximum-length linear codes, it is always possible to find a set of connections from flip-flop outputs to the parity generator that will yield a maximal length sequence of L= 2N 1 . Balance property: there are exactly 2L - 1 1 zeros and 2L - 1 ones in period of maximal-length sequence. The Pseudo random generator is shown in figure 3.2 Parity generator

D0

D1

D2

Dn-1

Clock Figure 3.2 Pseudo random generator

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From the above figure 3.2, the Pseudo random generator consists of a parity generator and D-FF , the parity bit is given to the first flip flop and the remaining are connected in series ,whose output are given to the parity generator to check the parity from the generated sequence. Independent sequences: one possible logic design connection is illustrated in table .there are many possible connections to the parity generator, which have small correlation to one another. The upper bound S of the numbers of independent sequences is given by S L 1 N Table 3.3 Sequence length L and number of m-sequences S of maximal length pseudo noise (PN) codes or pseudo random binary sequences (PRBS) Number stages N of Sequence length 2N 1 7 15 31 63 127 255 511 1023 2047 4095 8191 16383 32767 S=Number of L= m-sequences D0 for L= 2N 1 in figure Q Q 1 2 Q Q 2 3 Q Q 2 4 Q Q 4 5 Q Q 5 6 Q Q Q Q 1 2 3 7 Q Q 4 8 Q Q 6 9 Q Q 8 10 Q Q Q Q 1 9 10 11 Q Q Q Q 0 12 10 11 Q Q Q Q 1 12 13 11 Q Q 13 14

3 4 5 6 7 8 9 10 11 12 13 14 15

2 2 6 6 18 16 48 60 176 144 630 756 1800

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3.10.2 Gold sequences: In contrast to simple m-sequences, Gold sequences are suitable for multi-user CDMA systems. They offer a large number of sequence sets with good cross correlation properties between the single sequences. The Gold sequences are generated by modulo-2 addition of two m-sequences clocked by the same chip-clock. The most significant key in the Gold sequence design is that only special pairs of m-sequences deliver the desired correlation properties. Since both m-sequences have equal length L and use the same clock, the created Gold sequence is of length L as well however, it is no longer maximal. Let n be the number of stages in each m-sequence generator. The gold sequence length L= 2N 1 .

msequence generator-1 Clock fc Gold sequence

msequence generator-2 Figure 3.3 Gold Sequence Generator Let us look at the possible number of different Gold-sequences created with a two m-sequence generator setup. It can be shown from figure 3.3 that for any shift in the initial conditions between two m-sequences a new Gold sequence is generated. Since each msequence is of length L, the number of different shifts between the two m-sequences is available. Thus a Gold-sequence is generator combining two different m-sequences can create a number of different L= 2n 1 Gold sequences [5].

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3.11 Spreading Codes: WCDMA employs long spreading codes. In the forward link, cell separation and in the reverse link user separation is done using different spreading codes. In the forward link Gold codes of length 218are truncated to form cycles of 2 16 times 10ms frames. A special short code is used to minimize the cell search time. The synchronization channel of WCDMA is masked with an orthogonal short Gold code of 256 length.

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CHAPTER-4 4. DETAILS OF THE ARCHITECTURE 4.1 Hierarchical matched filter The proposed architecture of formed by the transposed hierarchical matched filter hybrid structure(Hybrid shown in figure 4.1 is composed of two matched filters which are dominant ).Since the structure is transpose structure dominant ,major number of taps will of in this structure and the remaining will have some direct form present in them. The first matched filter consists of an 8-bit sample, 16-bit reference, 16-bit previous value, system clock, reset, and an over sampling circuitry. In the matched filter the data samples are applied parallel to the all the 16 taps which are connected in series .But after every 3 taps the input is delayed and applied to the next tap. In this way the applied data and the previous data are applied to the tap ,in which the output is given as the previous input value to next tap .If the reset value is 1 then all taps are initialized to zeros otherwise the output of the operation is obtained[1]. Over sampling is a process in which single phase data can be converted into poly phase data. In this we perform 4 times over sampling so as to obtain four phases. The second matched filter consists of a 16-bit input which is the output of the first matched filter, 16-bit previous value, 16-bit reference which is same for the first matched filter (MF), the clock frequency applied is 1/16 times the clock frequency given to the first matched filter and a reset pulse as shown in figure 4.1. In this the data samples operate in the same way as that of the 8-bit data operation in the first matched filter, reference bits are controlled by the reset by which they are applied. The maximum value is obtained after 256 clock cycles. This gives a saving of 240 memory

35

cells than the traditional Matched filter [1].

36

Input

Clock Tap1 Tap2 Tap3 Tap4 Tap16

Reset

Tap1

Tap2

Tap3

Tap4

O/P
Tap16

Cnf C2 C16 Clock/16

C1

C3

C4

PSC Register
C1 C2 C3 C4

C16

Figure 4.1: Hierarchical structure in Hybrid form

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4.2 Matched filter tap: The matched filter tap shown in figure 4.2 of the hierarchical filter mainly consists of an add/sub circuit, multiplexer, 16 bit multiplexer, shift register and an over sampling circuit. The add/sub circuit consists of a input (8/16) and a 16-bit previous output which are used to perform addition /subtraction by using reference bit as carry input which is controlled by reset input with reference as input. Configuration bit is also used as the controlling input. The entire operation in the tap takes place in 2s complement form. The input value of the adder/sub varies between -128 to 127 since it is applied in two complement form, the input is converted into the 2complement form by passing the 8/16 bits through the individual 8/16 xor gates which mainly depend on the values third input given to the adder/subtractor. The output data of the adder/subtractor is passed through the mux which is controlled by reference data. The entire data is given to the output directly or after over sampling which perform (4 times over sampling) to produce a 16 bit over sampled data, this is given to the output. These two data are supplied to another multiplexer which depends on the configuration bit .if the configuration bit is 1 the data is over sampled . If the configuration bit is 0 the summation output is given to the matched filter output .the maximum value of the filter is obtained after 256 clock cycles when maximum input is applied to it [1].

38

Reset

0
Reference

0 1

Input data

0 1
Previous input
Clock

0
Shift register

1 0

0
Result of the tap

Over sampling

Configuration Figure 4.2 Matchedflag filter

tap 4.3 Addition/subtraction circuit: The adder/subtractor design mainly consists of three inputs, of which two are vectors, one is the normal input and the other is previous input .the third input given is a control input for performing the addition/subtraction operation. The design mainly consists of a 16-bit full adder and 16 input xor gates are present in the process. If the input c value is zero then the xor gates depends on the previous input values, so the output is the addition of the two inputs. If the c value is one then the xor gates depends on the inverse of the previous input values, so the output is the difference of the two inputs. In this way the design operation is controlled by the value c. 4.4 Over sampling design:

39

In over sampling design, the circuit mainly consists of over sampling circuit and a counter. In over sampling circuit each input bit is sampled 4times the original width and the output of the circuit are given to the counter. In this the output of the counter for every clock pulse is taken and given as the output of the circuit. 4.5 Shift registers: Shift registers are mainly of four types: 1) Serial in Serial out Shift registers 2) Parallel in Parallel out Shift registers 3) Serial in parallel out Shift registers 4) Parallel in serial out Shift registers In this design, we use parallel in parallel out shift registers. Since the input provided should be delayed by clock cycle. This process is done to induce the direct form of the finite impulse response (FIR) filters so that we can do our operations .By providing the delay element we can have the advantage of accessing through all the scrambling codes and the time taken for accessing will be minimum. 4.6 Counters: A counter is mainly used to generate different bit patterns for different clock cycles. The change in bit pattern occurs with an increment of one in the output. The counter can be useful in providing the outputs as clocks to the designs. Frequency divider: Frequency divider is similar to a counter, but in clock divider the initial clock is given as the main input and remaining alterations are done automatically. The frequency of the next output is divided into half the frequency of the previous output. In this way, the clock frequency is doubled for the output when compared to the previous output.

40

4.7 16-bit full adder: Full adder is constructed by using 16 individual full adders. In this the full adders are connected in cascade to forward the carry generated by the full adder so that we can generate the sum of the 16-bit full adder 4.8 16-bit D-flip-flop: In this circuit the D flip-flops are connected in parallel to input the 16 input at a time when the clock pulse is applied at a time instead of 16 clock pulses. In this way we transmit 16-bit data at time in 16-bit D-Flip-Flop. 4.9 Linear Feedback Shift Register : In LFSR, the data is shifted serially bit by bit and the intermediate bits will undergo the process of modulo 2 addition so that the bit pattern will change continuously. The output and the periodicity mainly depends on the alignment of taps in the LFSR. By the arrangement of taps the LFSR can be periodic or aperiodic LFSR.

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CHAPTER-5 5. RESULTS AND DISCUSSIONS 5.1 Schematics of Hierarchical matched filter 5.1.1 RTL Schematic: The RTL Schematic of Hierarchical matched filter is shown in figure 5.1

Figure 5.1 RTL schematic of Hierarchical matched filter

From the above figure 5.1, RTL schematic mainly consists of basically four modules, hierarchical matched filter stage 1, stage 2, LFSR and clock divider modules. In this the first stage HMF is supplied with 8-bit sample, previous input, reference input, reset and system clock. In the second stage the 8-bit data is replaced by 16-bit data and the clock is provided the clock divider. The clock divider is mainly used to generate a clock pulse of 16 times the system Clock pulse. In this way, after every 16 cycles data is provided to the second matched filter. The reference signal is provided by the fourth module and will operate when data is 1. 5.1.2 TECHNOLOGY Schematic: 42

The technology Schematic of Hierarchical matched filter is shown in figure 5.2

Figure 5.2 Technology schematic of Hierarchical matched filter The design connections are based on Look Up Tables as shown in figure 5.2. Where as the xilinx virtex is based on LUTS. The above technology schematic shows an effective architecture for speed and area constraints.

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5.1.3 Design Summary of Hierarchical Matched Filter using virtex 2pro device xc2vp30-7ff896: Logic utilization, logic distribution, logic slices, LUT count, IOBs Flip Flops, JTAG count, gate count and timing summary of HMF in Xilinx FPGA are shown in detail in table 5.1 Table 5.1Design summary of Hierarchical matched filter Logic utilization Slices Slice registers 4 input LUTs Logic Distribution Occupied slices Related logic containing slices Unrelated logic containing slices Total number of LUTs Number of Bonded IOBs IOBs Flip Flops Number of PPC405s Number of GCLKs Number of GTs Number of GT10s Total gate count JTAG gate count Timing Summary Speed grade Minimum period Maximum frequency Used 502 716 942 688 688 0 942 45 8 0 2 0 0 14,936 2,160 Available 13696 27392 27392 13696 646 646 27392 556 2 16 8 0 Utilization 3% 2% 3% 5% 100% 0% 3% 8% 0% 12% 0% 0%

-7 3.631ns 275.402MHz

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5.1.3 Design Summary of Hierarchical Matched Filter using virtex 2pro device xc2vp30-7ff896 after Chip Scope pro 9.1i : Logic utilization, logic distribution, loic slices, LUT count, IOBs Flip Flops, JTAG count, gate count, RAM, BSCAN, RPMS and timing summary of HMF in Xilinx FPGA are shown in table 5.2. Table 5.2 Design summary for Hierarchical matched filter with Chip scope pro 9.1i Logic Utilization Slices Slice registers 4 input LUTs Logic Distribution Occupied slices Related logic containing slices Unrelated logic containing slices Total number of 4 input LUTs Number used as logic Number used as a route-thru Number used as Shift registers Number of Bonded IOBs IOBs Flip Flops Number of PPC405s Number of Block RAMs Number of GCLKs Number of BSCANs Number of GTs Number of GT10s Number of RPM Macros Total gate count JTAG gate count Used 502 1092 1155 1064 1064 0 1336 1155 50 131 45 28 0 2 2 1 0 0 17 159,621 2,160 556 2 136 16 1 8 0 8% 0% 1% 12% 100% 0% 0% Available 13696 27392 27392 13696 1064 1046 27392 Utilization 8% 3% 4% 7% 100% 0% 4%

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From the above given two design summaries, the summary obtained using chip scope pro gives the details of the memory elements in which the slices are stored. It also gives the details of the shift registers which are used by the filter to shift the data and also the data flip-flops in the system. These shift registers will be increased with increase in data shifting. The timing summary gives the details of the minimum period of clock and also the maximum frequency.

Figure 5.5 Behavioral Simulation waveform of Hierarchical matched filter

Figure 5.6 Post Place and Route Simulation waveform of Hierarchical matched filter

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Consider an input sample of 8-bit data having value 127 which is supplied to all the taps present in the first stage, the previous data is supplied to the first filter consists of all zeros and the reference signal is generated by the Linear Feedback Shift Register (LFSR) which varies at every individual clock pulse. First all the internal signals are reset by giving a high signal to it. After the circuit is reset, the first matched filter is given 16 clock pulses which results in a 16-bit value of 2032 at the output of the first matched filter. This value is given as input signal to the second matched filter and the output is obtained after 256 clock pulses which mainly depend on the configuration bit of the circuit. If the configuration bit is zero, FIR output is obtained or over sampled data at the output is obtained when the configuration bit is 1. The data in the LFSR is generated when the data input is high. The behavioral output is obtained at 5250 ns, where as the post simulation output is obtained at 5290ns. The behavioral output is obtained by giving a delay of 100ns at the beginning which is followed by the 256 cycles of 20ns clock pulse which is reset in the first pulse. The total timing value results in 100+ (20 x 256) + 20=5240ns .System delay of 10ns is added which gives 5250ns.The output of the circuit mainly depends on the 8-bit data sample. The reference code is obtained by the Linear Feedback Shift Register (LFSR) by assigning the value of d=1.

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5.2 PLACEMENT, ROUTING AND POWER ANALYSIS OF THE HIERARCHICAL MATCHED FILTER The Floor planning of HMF in virtex-2 pro devices is shown in the figure 5.7. In the virtex devices the pins are present in the form of banks. The xc2vp30-7ff896 device consists of 7 Banks. The pins in the bank are assigned by adding the user constraints file (UCF) to the source.

Figure 5.7 Placement of assigned pins on xc2vp30-7ff896 device on floor plan editor In the above figure 5.7 the assignment of carry chains on the required device.

48

The pins will be assigned in the order of their given pin numbers. The routing is shown in figure 5.8

Figure 5.8 Routing of the placed assigned pins on xc2vp30-7ff896 device From the figure 5.8,each shaded portion indicates a carry chain present in the circuit. In this circuit there are 32 carry chains with each chain constituting of 16 cycles in the circuit. The above figure shows the routing that takes place between the assigned pins which are already placed on the device. It gives the details of the wiring delay that occurs due to the routing of the pins on the required device. The above figure 5.8 gives the carry chains that are routed or connected in the circuit.

49

The array routing is shown in figure 5.9

Figure 5.9 Floor plan editor for routing of the Hierarchical matched filter From the above figure 5.9, gives the details of the amount of the area occupied by the circuit on the device and the amount of area efficiently utilized by the circuit .in this the area is efficiently utilized by placing the pins nearer are moved apart and the pins farther are moved closer to them so that efficient area can be utilized.

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5.3 FILTER

POWER

REPORT

OF

HIERARCHICAL

MATCHED

From the below table 5.3, the current consumption is maximum when the voltage is minimum which results in large power consumption compared to the current consumption at auxiliary voltage, where the power consumption is minimum .So to have a minimum power consumption the voltage is maintained at quiescent value. Table 5.3 XPOWER REPORT for hierarchical matched filter Power Summary Total estimated power Vccint 1.5V Vccaux 2.5V Vcco25 2.5V Quiescent Vccint 1.5V Quiescent Vccaux 2.5V Quiescent Vcco25 2.5V Thermal Summary Estimated junction temperature Ambient temperature Case temperature Theta J-A 25C 25C 0 C/W I(mA) P(mW) 103 75 25 3 75 25 3

50 10 1 50 10 1 temperature 25C

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CHAPTER-6

6. CONCLUSION AND FUTURE SCOPE OF THE PROJECT This project is used in the WCDMA systems for achieving maximum output after 256 clock cycles; this output mainly depends on the input given to the system. The duration of the time required for the 256 cycles depends on the system clock applied to the Hierarchical matched filter. The VLSI architecture of HMF is designed using VerilogHDL and is implemented using Xilinx ISE navigator and modelsim using virtex-2pro device In future, the filter can be implemented by changing the architecture of the FIR in the system. Since implementing of the hierarchical filter by hybrid form is performed, this can also be implemented by using the adaptive filter architecture, IIR filter architecture .In this filter higher data rates and area reduction can be achieved by increasing the order of the filter and reducing the length of scrambling codes. Increasing in the clock frequency results in large data rates.

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REFERENCES [1] Dr. Aziz A. Hussain Abdul and Dr. Karim A-R. Kadhim Abdul, Hierarchical Matched Filter Based on FPGA for Mobile Systems, Baghdad, Iraq. [2] Dahlman. E, Beming.P, Knutsson. J, Ovesj. F, Persson.M, and Roobol.C, WCDMAthe radio interface for future mobile multimedia communications, IEEE Trans. Veh. Technol., vol. 47, pp. 11051118, Nov. 1998. [3] Fast cell search algorithm in DS-CDMA mobile using long spreading codes, in Proc. IEEE 1997 Veh. Technol. Conf., Phoenix, AZ, May 1997, pp. 14301434. [4] Gray D Steven, Tero Ojanpera, An Overview of cdma2000, WCDMA, and EDGE, Nokia Research centre [5] Dr. Feher Kamilo, Wireless Digital communications: Modulation and Spread Spectrum techniques, Prentice-Hall, pp. 1-7. [6] Higuchi.K, Sawahashi.M, and Adachi.F, Fast cell search algorithm using long code masking in DS-CDMA asynchronous cellular system, Tech. Rep. IEICE, pp. 5762, Jan. 1997. [7] Moon Kyou Song, and Vijay K. Bhargava, Performance Analysis of Cell Search in WCDMA Systems over Rayleigh Fading Channels, IEEE transaction on vehicular technology, vol 51, no.4, July 2002 [8] Ojanper.T and Prasad.R, An overview of air interface multiple access for IMT-2000/UMTS, IEEE Commun.Mag., vol. 36, pp. 8295, Sept.1998. [9] Peterson R. L, Ziemer R. E, and Borth D. E, Introduction to Spread Spectrum Communications. Englewood Cliffs, NJ: PrenticeHall, 1995.

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[10] Rappaport S. S and Grieco D. M.,Spread spectrum signal acquisition: method and technology, IEEE Communication Magazine. vol. 22, pp. 6-21, June 1984. [11] Shailendra Mishra, Performance Enhancements to the WCDMA Cell Search Algorithms, journal of Information technology and applications, vol. 1, no 2, September 2006, pp 59-78. [12] Stuber G. L, Mark J. W, and Blake I. F, Sequential estimation using bit estimation techniques, Inform. Sci., vol. 32, pp. 217-229, 1984. [13]Sung-Won Lee and In-Cheol Park, Low-Power Hybrid Structure of Digital Matched Filters for Direct Sequence Spread Spectrum Systems, Department of Electrical Engineering and Computer Science, KAIST [14] Ward R. B and Yiu K. P,Acquisition of pseudo-noise signal by recursion aided sequential estimation, IEEE Trans. Communication., vol. 25, pp. 778-784, Aug. 1977 [15] William Stallings, Wireless Communications and Networks, second edition, Prentice-Hall of India Private Limited 2008 [16]Yi-Pin Eric Wang, and Tony Ottosson, Cell Search in W-CDMA, IEEE journal on selected areas in communications, vol 18, no. 8, August 2000 [17] 3rd Generation Partnership Project, Spreading and modulation (FDD), 3GPP Tech. Spec., TS 25.213, V3.0.0, Oct. 1999. [18]3rd Generation Partnership Project, Physical channels and mapping of transport channels onto physical channels (FDD), 3GPP Tech. Spec., TS 25.211, V3.0.0, Oct. 1999. [19] WCDMA system Overview [20]WCDMA/UMTS wireless networks by Tektronix technical brief.

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