VLSI architecture

An introduction to neural networks and neural information processing is provided. Neurocomputers are discussed, focusing on how their design exploits the architectural properties of VLSI circuits. General-purpose and special-purpose neurocomputer developments throughout the world are examined. As illustration, and to put European developments in perspective, some of the important projects in the United States and Japan are described. European research is then discussed in greater detail.>

In this paper, we introduced new methods in implementing ultra-fast-efficient BCH decoder that frequently used in many applications. A Reformulated inversionless-Berlekamp-Massey algorithm is adopted in order to eliminate the finite-field inverter and to reduce the hardware complexity. Furthermore, we proposed a Direct reformulated-inversionless Berlekamp-Massey algorithm (DriBM). While in the Chien Search stage, the Constant-Factor Multiplication-Free Matrix transform is also introduced

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture

The development of mobile multimedia devices follows the platform-based design methodology in which IP cores are the building blocks. In the context of mobile devices there is a concern of battery lifetime which leads to the need of energy-efficient IP cores. This paper presents an energy-efficient FDCT/IDCT configurable IP core. Synthesis for 90 nm resulted in 50 MHz as maximum

Digital television/terrestrial multimedia broadcasting (DTMB) was announced as the Chinese digital television terrestrial broadcasting (DTTB) standard in August, 2006. It adopts TDS-OFDM (time-domain synchronous-orthogonal frequency division multiplexing) as the baseline modulation technology. There is not pilot information in order to avoid reduction of channel throughput. It uses pseudo-noise (PN) sequence as guard interval (GI) and the training sequence for both multi- and single-carrier block transmissions which makes the synchronization faster than CP-OFDM (cyclic prefix-orthogonal frequency division multiplexing) systems. It can resist the inter-symbol interference (ISI) and can be used for channel estimation and synchronization. In this paper, a full-mode channel estimation scheme for DTMB demodulator is developed. This method utilizes the PN sequence to obtain channel estimation and equalization both in three kinds of frame head (FH) mode as well as in single and multi-carrier modulation transmission mode. To implement on hardware realization, interference cancellation is predigested, then equalization and filter for channel impulse response are optimized. A low cost VLSI architecture for channel estimation and equalization is proposed which works effectually and achieves low complexity as well. Computational simulation results show that the proposed scheme has little BER loss in performance.

This paper presents a VLSI architecture specifically designed as a video/communication controller to support emerging applications in the area of video/data communications. The controller is a parallel architecture consisting of three (3) processing modules, a shared memory with four (4) banks and two (2) input/output modules and operating at the transfer speed of 622 Mbits/sec. The processing modules and memory banks communicate through a low cost interconnection scheme able though to perform at system's required data transfer rate. The entire system constitutes a component which can accommodate a switching system as an intelligent buffer with real time processing and multiplexing capabilities. The component performs operations on fixed and/or variable length packets of data on a stream basis. The architecture embeds both the processing and the memory modules, thus producing a “system on a chip” solution.

This paper discusses the programmable and dedicated approaches for real-time video processing applications. Various VLSI architecture including the design examples of both approaches are reviewed. Finally, discussions of several practical designs in real-time video processing applications are then considered in VLSI architectures to provide significant guidelines to VLSI designers for any further real-time video processing design works.