The previous chapter discussed various steps of high-level synthesis (HLS) which are used for des... more The previous chapter discussed various steps of high-level synthesis (HLS) which are used for design exploration of digital integrated circuits. It then discussed specific methods for dynamic power dissipation optimization as well as synthesis of hardware-trojan free digital integrated circuits. The methods relied on various bio-inspired algorithms for design space exploration. As complementary material of the previous chapter, this chapter presents HLS methods for leakage-optimal digital integrated circuit design exploration. Specifically, a paradigm shift approach is presented in which the complete HLS flow is performed without use of any electronic design automation (EDA) tool. All the associated tasks such as modeling, characterization, and optimization , are performed using non-EDA tools and hence this is called the " SPICEless " approach. For a specific objective of nanoelectronic digital integrated circuits, gate-leakage power dissipation is targeted.
During the last four decades, VLSI technology growth has been driven by miniaturization that redu... more During the last four decades, VLSI technology growth has been driven by miniaturization that reduces cost per transistor, power consumption per transistor, with higher packing density and reduced cost of operation. However, the small transistor size leads to very high electric fields across the gate oxide which causes the difficult problem of gate oxide leakage. This problem is mitigated by high-κ/metal-gate technology, in which the gate material is copper (going back to metal from polysilicon) and the gate oxide material is a not silicon dioxide. At the same time, explosive growth of mobile portable electronics has been the driver for many scientific, engineering, and technological breakthroughs in the last few decades. Mobile electronics in particular, such as smart mobile phones, spend most of their operational time in waiting for a call or similar event. However, during these wait states leakage power dissipation has been a major issue since it drains the battery continuously. The industry has explored various solutions to reduce the OFF state leakage and multiple gate devices emerged as a solution to this problem. Double gate FinFET technology is considered as a solution to reduce OFF state leakage while having faster ON and OFF transitions and low-power dissipation. This chapter discusses these devices and presents logic libraries which can be used in the digital synthesis of large integrated circuits using such devices through electronic design automation (EDA) tools.
With the explosive growth of internet technology, easy transfer of digital multimedia is feasible... more With the explosive growth of internet technology, easy transfer of digital multimedia is feasible. However, this kind of convenience with which authorized users can access information, turns out to be a mixed blessing due to information piracy. The emerging field of Digital Rights Management (DRM) systems addresses issues related to the intellectual property rights of digital content. In this paper, an object-oriented (OO) DRM system, called "Imaging System with Watermarking and Attack Resilience" (ISWAR), is presented that generates and authenticates color images with embedded mechanisms for protection against infringement of ownership rights as well as security attacks. In addition to the methods, in the object-oriented sense, for performing traditional encryption and decryption, the system implements methods for visible and invisible watermarking. This paper presents one visible and one invisible watermarking algorithm that have been integrated in the system. The qualitative and quantitative results obtained for these two watermarking algorithms with several benchmark images indicate that high-quality watermarked images are produced by the algorithms. With the help of experimental results it is demonstrated that the presented invisible watermarking techniques are resilient to the well known benchmark attacks and hence a fail-safe method for providing constant protection to ownership rights.
... 191 6.5.2 Time-and Resource-Constrained Scheduling Algorithms . . ... The fractions indicate ... more ... 191 6.5.2 Time-and Resource-Constrained Scheduling Algorithms . . ... The fractions indicate the probabilities that the indicated node will be at logic level “1” .... 77 3.23 A NAND implementation of a half-adder. ... 83 4.2 Mobile platform power breakdown ..... ...
The previous chapter discussed various steps of high-level synthesis (HLS) which are used for des... more The previous chapter discussed various steps of high-level synthesis (HLS) which are used for design exploration of digital integrated circuits. It then discussed specific methods for dynamic power dissipation optimization as well as synthesis of hardware-trojan free digital integrated circuits. The methods relied on various bio-inspired algorithms for design space exploration. As complementary material of the previous chapter, this chapter presents HLS methods for leakage-optimal digital integrated circuit design exploration. Specifically, a paradigm shift approach is presented in which the complete HLS flow is performed without use of any electronic design automation (EDA) tool. All the associated tasks such as modeling, characterization, and optimization , are performed using non-EDA tools and hence this is called the " SPICEless " approach. For a specific objective of nanoelectronic digital integrated circuits, gate-leakage power dissipation is targeted.
During the last four decades, VLSI technology growth has been driven by miniaturization that redu... more During the last four decades, VLSI technology growth has been driven by miniaturization that reduces cost per transistor, power consumption per transistor, with higher packing density and reduced cost of operation. However, the small transistor size leads to very high electric fields across the gate oxide which causes the difficult problem of gate oxide leakage. This problem is mitigated by high-κ/metal-gate technology, in which the gate material is copper (going back to metal from polysilicon) and the gate oxide material is a not silicon dioxide. At the same time, explosive growth of mobile portable electronics has been the driver for many scientific, engineering, and technological breakthroughs in the last few decades. Mobile electronics in particular, such as smart mobile phones, spend most of their operational time in waiting for a call or similar event. However, during these wait states leakage power dissipation has been a major issue since it drains the battery continuously. The industry has explored various solutions to reduce the OFF state leakage and multiple gate devices emerged as a solution to this problem. Double gate FinFET technology is considered as a solution to reduce OFF state leakage while having faster ON and OFF transitions and low-power dissipation. This chapter discusses these devices and presents logic libraries which can be used in the digital synthesis of large integrated circuits using such devices through electronic design automation (EDA) tools.
With the explosive growth of internet technology, easy transfer of digital multimedia is feasible... more With the explosive growth of internet technology, easy transfer of digital multimedia is feasible. However, this kind of convenience with which authorized users can access information, turns out to be a mixed blessing due to information piracy. The emerging field of Digital Rights Management (DRM) systems addresses issues related to the intellectual property rights of digital content. In this paper, an object-oriented (OO) DRM system, called "Imaging System with Watermarking and Attack Resilience" (ISWAR), is presented that generates and authenticates color images with embedded mechanisms for protection against infringement of ownership rights as well as security attacks. In addition to the methods, in the object-oriented sense, for performing traditional encryption and decryption, the system implements methods for visible and invisible watermarking. This paper presents one visible and one invisible watermarking algorithm that have been integrated in the system. The qualitative and quantitative results obtained for these two watermarking algorithms with several benchmark images indicate that high-quality watermarked images are produced by the algorithms. With the help of experimental results it is demonstrated that the presented invisible watermarking techniques are resilient to the well known benchmark attacks and hence a fail-safe method for providing constant protection to ownership rights.
... 191 6.5.2 Time-and Resource-Constrained Scheduling Algorithms . . ... The fractions indicate ... more ... 191 6.5.2 Time-and Resource-Constrained Scheduling Algorithms . . ... The fractions indicate the probabilities that the indicated node will be at logic level “1” .... 77 3.23 A NAND implementation of a half-adder. ... 83 4.2 Mobile platform power breakdown ..... ...
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