Peter De Heyn
Ghent University, Information Technology (INTEC), Graduate Student
We demonstrate a microbump flip-chip integrated 14nm-FinFET CMOS-Silicon Photonics (SiPh) technology platform enabling ultra-low power Optical I/O transceivers with 1.6Tb/s/mm2 bandwidth density. The transmitter combines a differential... more
We demonstrate a microbump flip-chip integrated 14nm-FinFET CMOS-Silicon Photonics (SiPh) technology platform enabling ultra-low power Optical I/O transceivers with 1.6Tb/s/mm2 bandwidth density. The transmitter combines a differential FinFET driver with a Si ring modulator, enabling 40Gb/s NRZ optical modulation at 154fJ/bit dynamic power consumption in a 0.015mm2 footprint. The receiver combines a FinFET trans-impedance amplifier (TIA) with a Ge photodiode, enabling 40Gb/s NRZ photodetection with −10.3dBm sensitivity at 75fJ/bit power consumption, in a 0.01mm2 footprint. High-quality data transmission and reception is demonstrated in a loop-back experiment at 1330nm wavelength over standard single mode fiber (SMF) with 2dB link margin. Finally, a 4×40Gb/s, 0.1mm2 wavelength-division multiplexing (WDM) transmitter with integrated thermal control is demonstrated, enabling Optical I/O scaling substantially beyond 100Gb/s per fiber.
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We present O-band Si ring modulators with up to 58pm/V electro-optic and 610pm/mW thermo-optic modulation efficiencies and >24GHz modulation bandwidth, enabling a hybrid CMOS-SiPho transceiver with error-free operation at 40Gbps... more
We present O-band Si ring modulators with up to 58pm/V electro-optic and 610pm/mW thermo-optic modulation efficiencies and >24GHz modulation bandwidth, enabling a hybrid CMOS-SiPho transceiver with error-free operation at 40Gbps NRZ with <4pJ/bit link energy.
Research Interests: Optoelectronics and Cmos
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A 16-channel spatial-division multiplexed transceiver is demonstrated using a multicore fiber coupled to a dense array of co-integrated 56Gb/s GeSi electro-absorption modulators and photodetectors, realizing 896Gb/s aggregate... more
A 16-channel spatial-division multiplexed transceiver is demonstrated using a multicore fiber coupled to a dense array of co-integrated 56Gb/s GeSi electro-absorption modulators and photodetectors, realizing 896Gb/s aggregate bi-directional bandwidth in 1.47mm2 silicon footprint.
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Silicon photonics interposers enable low power, high bandwidth signal transfer between CMOS chips. Optical wave guides transfer the optical signal that carries the information. Optical modulator and detectors realize the optical to... more
Silicon photonics interposers enable low power, high bandwidth signal transfer between CMOS chips. Optical wave guides transfer the optical signal that carries the information. Optical modulator and detectors realize the optical to electrical signal transfer and vice versa. These components could be facing ESD stress during assembly. This work presents an in-depth study the self-protecting capabilities of these components and provides an ESD protection solution to increase the ESD robustness.
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ABSTRACT Silicon photonics (SiPh) has been identified as a prime technology targeting cost-effective short-range optical links [1]. Wavelength-division multiplexing (WDM) is an attractive approach for enabling high aggregate transceiver... more
ABSTRACT Silicon photonics (SiPh) has been identified as a prime technology targeting cost-effective short-range optical links [1]. Wavelength-division multiplexing (WDM) is an attractive approach for enabling high aggregate transceiver bandwidth without increasing the number of optical fibers used in the link. Ring-based optical modulators and wavelength-selective filters are attractive devices for scalable WDM SiPh transceivers owing to their compact footprint and moderate power required for thermal tuning. In this paper, we report on a thermally controlled ring-based flip-chip integrated CMOS-SiPh transceiver with 4 channels operating at 20Gb/s.
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Packaging and assembly challenges for photonic chips still need to be addressed in order to enable rapid deployment in mass-market production. Integration and assembly solutions that not only enable ease of packaging but also allow a... more
Packaging and assembly challenges for photonic chips still need to be addressed in order to enable rapid deployment in mass-market production. Integration and assembly solutions that not only enable ease of packaging but also allow a dense co-integration of the electronic and photonic ICs are essential. In that context, we demonstrate an adaptive patterning of both optical and electrical fan-out for face-up electronic-photonic integration. For the optical fan-out, we developed an approach based on adiabatic optical coupling between single-mode polymer waveguides and silicon waveguides on a silicon photonic chip. The polymer waveguides were directly patterned on the silicon photonic chip by direct-write lithography (DWL). The electrical interconnects between a photonic chip and electronic IC are realized by employing high-speed silver interconnects using aerosol-jet printing (AJP), as a promising alternative for the traditional bond-wires. Furthermore, a direct comparison between the AJP interconnects and the conventional bondwires is established. Finally, an NRZ optical transmitter has been successfully demonstrated based on the AJP interconnection and clear open eye diagrams were obtained at 56 Gb/s.
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The growing demand for I/O bandwidth in high-performance applications, such as datacenter switches and HPC nodes, drives the need for on-package integration of Optical I/O modules with the host CMOS ICs [1]. Silicon Photonics (SiPh) is a... more
The growing demand for I/O bandwidth in high-performance applications, such as datacenter switches and HPC nodes, drives the need for on-package integration of Optical I/O modules with the host CMOS ICs [1]. Silicon Photonics (SiPh) is a prime technology platform to realize multi-Tb/s hybrid CMOS-SiPh modules for $1\mathrm {m}-500\mathrm {m} +$ optical interconnect distances [2]. Such Optical I/O modules require interfaces for dense, high-speed electrical I/O and low-noise power and ground delivery, which can be enabled by the integration of through-silicon vias (TSV) into the SiPh platform. Here, we describe challenges and results for $10 \mu \mathrm{m} \times 100 \mu \mathrm {m}$ TSV-middle integration into a 300mm SiPh interposer platform. TSVs with low RF loss up to 50GHz are demonstrated along with low SiPh waveguide losses and high-performance Ge photodetectors.
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We demonstrate 112 Gb/s 4-level pulse amplitude modulation over 2 km of SMF using a C-band GeSi electro-absorption modulator for data-center interconnects. Also, we present first results towards 400 Gb/s wavelength division multiplexed... more
We demonstrate 112 Gb/s 4-level pulse amplitude modulation over 2 km of SMF using a C-band GeSi electro-absorption modulator for data-center interconnects. Also, we present first results towards 400 Gb/s wavelength division multiplexed transmission.
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Research Interests: Materials Science, Optics, Medical Imaging, Fiber Optics, Photonics, and 15 moreSilicon, Silicon Photonics, Optoelectronics, Society, Optical, Light, Optical Interconnects, Germanium, Cmos, Optical physics, Photodetector, Technology and Engineering, Electrical And Electronic Engineering, Dark Current, and Responsivity
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We demonstrate an O band 40Gb/s silicon microring modulator assembled with a 1V driver in a 52km metro transmission experiment without dispersion compensation, achieving a record high bandwidth distance product of 2080 Gbkm/s.
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We present a fully CMOS compatible frequency shifter device, in a I&Q dual Mach-Zehnder architecture. Frequency shift up to 410 MHz are obtained, with carrier and image sideband extinction from 27 to 51 dB.
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Germanium-based waveguide electro-absorption modulators are reported in C- and L-band wavelength operation at 56Gb/s (NRZ-OOK) with extinction ratio of >3dB at 2V peak-to-peak and insertion loss below 5dB. The device is implemented in... more
Germanium-based waveguide electro-absorption modulators are reported in C- and L-band wavelength operation at 56Gb/s (NRZ-OOK) with extinction ratio of >3dB at 2V peak-to-peak and insertion loss below 5dB. The device is implemented in a fully integrated Si photonics platform on 200mm silicon-on-insulator wafer with 220nm top Si thickness. Wafer-scale performance data confirms the manufacturability of the device. This demonstrates the great potential for realizing high-density and low-power silicon photonic transceivers for short range interconnect.
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We present an 8×8 silicon photonics AWGR with 10 nm channel spacing for O-band cyclic-routing operation. Successful transmission at 25 Gb/s is demonstrated for all 8×8 AWGR channel combinations with a maximum power penalty of 0.82 dB.
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In this article, we present for the first time to our knowledge, a DWDM <inline-formula> <tex-math notation="LaTeX">$16\times 16$ </tex-math></inline-formula> silicon photonic cyclic-frequency AWGR... more
In this article, we present for the first time to our knowledge, a DWDM <inline-formula> <tex-math notation="LaTeX">$16\times 16$ </tex-math></inline-formula> silicon photonic cyclic-frequency AWGR device. The AWGR features a channel spacing of 1.06 nm (189 GHz), a free spectral range of 17.80 nm (3.16 THz) and a 3-dB channel bandwidth of 0.65 nm (116 GHz). Its proper cyclic-frequency operation was experimentally verified for all <inline-formula> <tex-math notation="LaTeX">$16\times 16$ </tex-math></inline-formula> channels with channel peak insertion loss values in the range of 3.90 dB to 8.37 dB, yielding a channel loss non-uniformity of 4.47 dB. Its compact footprint of 0.27 mm <inline-formula> <tex-math notation="LaTeX">$\times0.71$ </tex-math></inline-formula> mm and its low crosstalk value of 21.65 dB highlight its potential for employment in future AWGR-based interconnect schemes in O-band.