[go: up one dir, main page]

Katabami et al., 2013 - Google Patents

Design of a GALS-NoC using soft-cores on FPGAs

Katabami et al., 2013

Document ID
276225986801278965
Author
Katabami H
Saito H
Yoneda T
Publication year
Publication venue
2013 IEEE 7th International Symposium on Embedded Multicore Socs

External Links

Snippet

In this paper, we propose a Globally-Asynchronous Locally-Synchronous Network-on-Chip (GALS-NoC) architecture for FPGAs. Each node in the proposed GALS-NoC is based on a soft-core processor for FPGAs. Each node also has a local clock generator with a clock …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234—Action, measure or step performed to reduce power consumption
    • G06F1/3237—Power saving by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Similar Documents

Publication Publication Date Title
Kurth et al. An open-source platform for high-performance non-coherent on-chip communication
US7401333B2 (en) Array of parallel programmable processing engines and deterministic method of operating the same
Tran et al. NoCTweak: a highly parameterizable simulator for early exploration of performance and energy of networks on-chip
Ogras et al. Modeling, analysis and optimization of network-on-chip communication architectures
Liu et al. Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip
Kasapaki et al. Argo: A time-elastic time-division-multiplexed noc using asynchronous routers
Kamali et al. DuCNoC: A high-throughput FPGA-based NoC simulator using dual-clock lightweight router micro-architecture
Abdelfattah et al. Design and applications for embedded networks-on-chip on FPGAs
Zoni et al. A dvfs cycle accurate simulation framework with asynchronous noc design for power-performance optimizations
Ax et al. Comparing synchronous, mesochronous and asynchronous NoCs for GALS based MPSoCs
Katabami et al. Design of a GALS-NoC using soft-cores on FPGAs
Zhao et al. A dedicated monitoring infrastructure for multicore processors
Kundu et al. Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
Reddy et al. OpenNoC: An open-source NoC infrastructure for FPGA-based hardware acceleration
Salminen On design and comparison of on-chip networks.
Bahn et al. On design and application mapping of a Network-on-Chip (NoC) architecture
Russell et al. Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC
Shen et al. An FPGA-based distributed computing system with power and thermal management capabilities
Terraneo et al. A cycle accurate simulation framework for asynchronous noc design
Rodriguez et al. Leveraging partial dynamic reconfiguration on zynq soc fpgas
Menaka et al. Asynchronous circular buffers based on FIFO for network on chips
Pu et al. Power and area efficient router with automated clock gating for neuromorphic computing
Wächter et al. HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAs
Hansson et al. A quantitative evaluation of a network on chip design flow for multi-core consumer multimedia applications
US20170212861A1 (en) Clock tree implementation method, system-on-chip and computer storage medium