Kamali et al., 2017 - Google Patents
DuCNoC: A high-throughput FPGA-based NoC simulator using dual-clock lightweight router micro-architectureKamali et al., 2017
- Document ID
- 2944030587398017472
- Author
- Kamali H
- Azar K
- Hessabi S
- Publication year
- Publication venue
- IEEE Transactions on Computers
External Links
Snippet
On-chip interconnections play an important role in multi/many-processor systems-on-chip (MPSoCs). In order to achieve efficient optimization, each specific application must utilize a specific architecture, and consequently a specific interconnection network. For design space …
- 238000004088 simulation 0 abstract description 39
Classifications
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- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F15/00—Digital computers in general; Data processing equipment in general
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- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
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- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
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- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
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- G06F9/44—Arrangements for executing specific programmes
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