[go: up one dir, main page]

Rodriguez et al., 2014 - Google Patents

Leveraging partial dynamic reconfiguration on zynq soc fpgas

Rodriguez et al., 2014

Document ID
12145540914869487999
Author
Rodriguez J
Ackermann K
Publication year
Publication venue
2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

External Links

Snippet

The ability of modern FPGAs to change isolated regions of their configuration during run- time is increasingly appreciated by industry. Integrating powerful microprocessors modern FPGAs evolved to efficient SoC architectures, making dynamic partial reconfiguration …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/78Architectures of general purpose stored programme computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored programme computers comprising a single central processing unit with reconfigurable architecture
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08Clock generators with changeable or programmable clock frequency
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163Interprocessor communication
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736Structural details of routing resources
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit

Similar Documents

Publication Publication Date Title
Vipin et al. DyRACT: A partial reconfiguration enabled accelerator and test platform
Kalte et al. A prototyping platform for dynamically reconfigurable system on chip designs
JP2009543472A (en) Reconfigurable logical fabric for integrated circuits and systems and methods for configuring a reconfigurable logical fabric
US9584130B1 (en) Partial reconfiguration control interface for integrated circuits
JP6655028B2 (en) Extraction of system architecture in high-level synthesis
TW201428521A (en) System, device and method for designing and emulating
US20250208209A1 (en) Debug trace microsectors
EP3658928B1 (en) Logic analyzer for integrated circuits
Paulsson et al. Implementation of a virtual internal configuration access port (jcap) for enabling partial self-reconfiguration on xilinx spartan iii fpgas
Gonzalez et al. Self-reconfigurable embedded systems on low-cost FPGAs
Rodriguez et al. Leveraging partial dynamic reconfiguration on zynq soc fpgas
US9575123B2 (en) Registers for post configuration testing of programmable logic devices
Saidi et al. Soft-core embedded FPGA based system on chip
US8015531B1 (en) Deferred parameterization
Shen et al. An FPGA-based distributed computing system with power and thermal management capabilities
Malik et al. EPOCH: Enabling preemption operation for context saving in heterogeneous FPGA systems
Liu et al. A NoC emulation/verification framework
Katabami et al. Design of a GALS-NoC using soft-cores on FPGAs
US20230052788A1 (en) Software-Defined Synthesizable Testbench
Russo Adaptation of High Performance and High Capacity Reconfigurable Systems to OpenCL Programming Environments
US8578075B1 (en) Performance constraints for system synthesis
Neuendorffer FPGA platforms for embedded systems
Kulmala Scalable Multiprocessor System-on-chip Architecture Design on FPGA
Astarloa et al. A reconfigurable SoC architecture for high volume and multichannel data transaction in industrial environments
Essig et al. On-demand instantiation of co-processors on dynamically reconfigurable FPGAs