WO2026013522A1 - Semiconductor device and method for producing semiconductor device - Google Patents

Abstract

Provided is a highly reliable semiconductor device. The semiconductor device has a trench capacitor. The semiconductor device has an insulating layer provided with an opening. A first electrode of the capacitor is provided along a side surface of the opening of the insulating layer. An upper end surface of the first electrode has a lower height from a reference surface than an upper surface of the insulating layer. A ferroelectric layer containing oxygen is provided so as to have a region in contact with the first electrode in the opening. A region of the first electrode in contact with the ferroelectric layer becomes an oxide region. A second electrode of the capacitor is provided on the ferroelectric layer so as to have a region facing the first electrode across the ferroelectric layer in the opening.

Description

Semiconductor device and method for manufacturing the same

One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Furthermore, one embodiment of the present invention relates to a method for manufacturing a semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, integrated circuits, chips equipped with integrated circuits, and electronic components that house chips in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

In recent years, development of semiconductor devices such as LSIs (Large Scale Integration), CPUs (Central Processing Units), and memory (storage devices) has progressed. These semiconductor devices are used in a variety of electronic devices, including computers and personal digital assistants. Furthermore, various memory storage methods have been developed to suit different applications, such as temporary storage during processing and long-term data storage. Typical memory storage methods include DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and flash memory.

Furthermore, as shown in Non-Patent Documents 1 and 2, research and development of memories using ferroelectrics is being actively conducted. For next-generation ferroelectric memories, research on ferroelectric _HfO2 -based materials (Non-Patent Document 3), research on the ferroelectricity of _{Hf0.5Zr0.5O2 thin films} (Non-Patent Document 4), research on the ferroelectricity of _HfO2 thin films (Non-Patent Document 5), and demonstration of integration of FeRAM (Ferroelectric _Random Access Memory) using ferroelectric _Hf0.5Zr0.5O2 with CMOS (Non-Patent Document ₆ ) are also being actively conducted.

T. S. Boescke, et al. , “Ferroelectricity in hafnium oxide thin films”, APL99, 2011 N. Ramaswamy, et al. , “NVDRAM:A 32Gb Dual Layer 3D Stacked Non-volatile Ferroelectric Mem ory with Near-DRAM Performance for Demanding AI Workloads”, IEDM 2023 Zhen Fan, et al. , “Ferroelectric HfO▲2▼-based materials for next-generation ferroelectric memories”, JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016 Jun Okuno, et al. , “SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf▲0.5▼Zr▲0.5▼O▲2▼”, VLSI 2020 Akira Toriumi, "Ferroelectricity of HfO2 Thin Films," The Japan Society of Applied Physics, Vol. 88, No. 9, 2019 T. Francois, et al. , “Demonstration of BEOL-compatible ferroelectric Hf▲0.5▼Zr▲0.5▼O▲2▼ scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications”, IEDM 2019 Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https://unit.aist.go.jp/rpd-envene/PV/ja/results/2019/oral/T13.pdf>

When metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide are used as ferroelectrics, if oxygen is released from the ferroelectric, the remanent polarization may decrease and the breakdown voltage may decrease after repeated rewriting. Therefore, if oxygen is released from the ferroelectric, the reliability of the memory containing that ferroelectric may decrease.

An object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated, and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a novel semiconductor device and a manufacturing method thereof.

Note that the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. Problems other than these may be extracted from the description in the specification, drawings, and claims.

One aspect of the present invention is a semiconductor device comprising a substrate, a first insulating layer, a first conductive layer, a second conductive layer, and a ferroelectric layer, wherein the first insulating layer, first conductive layer, second conductive layer, and ferroelectric layer are provided on the substrate, the first insulating layer has an opening, the first conductive layer has a region along the side of the opening in the first insulating layer, the top surface of the first conductive layer is lower from the substrate than the top surface of the first insulating layer, the ferroelectric layer has a region in contact with the first conductive layer in the opening, the second conductive layer has a region facing the first conductive layer in the opening with the ferroelectric layer sandwiched between them, the first conductive layer has an oxide region, the oxide region includes a region in contact with the ferroelectric layer, and the ferroelectric layer contains oxygen.

Alternatively, in the above aspect, the oxide region may include an oxide of an element contained in the first conductive layer.

Alternatively, in the above aspect, the angle of the upper end surface of the first conductive layer relative to the upper surface of the substrate may be greater than 0°.

Alternatively, in the above aspect, the second conductive layer may have a first layer and a second layer on the first layer, the first layer being provided so as to fill the opening, and the thermal expansion coefficient of the first layer being greater than the thermal expansion coefficient of the second layer.

Alternatively, in the above aspect, the first layer may contain titanium nitride and the second layer may contain tungsten.

Alternatively, in the above aspect, the semiconductor device may include a second insulating layer, a third insulating layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, wherein the second insulating layer is located on the second conductive layer and the first insulating layer, the third conductive layer and the fourth conductive layer are located on the second insulating layer, the second insulating layer has a groove portion overlapping a region between the third conductive layer and the fourth conductive layer and having a region reaching the second conductive layer, the semiconductor layer has a region contacting the second conductive layer, a region contacting the third conductive layer, a region contacting the fourth conductive layer, and a region along a portion of a side surface of the second insulating layer in the groove, the third insulating layer is provided on the semiconductor layer so as to have a region located inside the groove, and the fifth conductive layer may have a region inside the groove facing the semiconductor layer with the third insulating layer sandwiched therebetween.

Alternatively, the above aspect may have a fourth insulating layer and a sixth conductive layer, the fourth insulating layer being located on the third to fifth conductive layers, the sixth conductive layer being located on the fourth insulating layer, and the sixth conductive layer being electrically connected to the third conductive layer and the fourth conductive layer.

Alternatively, in the above aspect, the groove and the fifth conductive layer may extend in a first direction, and the sixth conductive layer may extend in a second direction, the second direction being perpendicular to the first direction.

Alternatively, in the above aspect, the semiconductor layer may contain indium.

Alternatively, one embodiment of the present invention is a method for manufacturing a semiconductor device, which includes forming a first insulating layer over a substrate, forming an opening in the first insulating layer, forming a conductive film to cover the opening, applying photoresist to the conductive film, and performing anisotropic etching on the photoresist to form a resist mask in the opening and processing the conductive film to form a first conductive layer along the side surface of the opening in the first insulating layer, removing the resist mask, and performing oxidation treatment on the first conductive layer to form an oxide region in the first conductive layer, forming a ferroelectric layer containing oxygen so as to have a region in contact with the oxide region, and forming a second conductive layer on the ferroelectric layer so as to have a region located in the opening, and the first conductive layer is formed so that the height of the top surface of the first conductive layer from the substrate is lower than the height of the top surface of the first insulating layer from the substrate.

Alternatively, in the above aspect, the oxidation treatment may involve forming a second insulating layer containing oxygen so as to have a region in contact with the first conductive layer, and then removing the second insulating layer.

Alternatively, in the above aspect, the second conductive layer may be formed by forming a first layer that fills the opening and a second layer on the first layer, and the thermal expansion coefficient of the first layer may be greater than the thermal expansion coefficient of the second layer.

Alternatively, in the above aspect, the first layer may be formed to contain titanium nitride, and the second layer may be formed to contain tungsten.

One embodiment of the present invention can provide a highly reliable semiconductor device and a manufacturing method thereof. Alternatively, one embodiment of the present invention can provide a semiconductor device that enables miniaturization and high integration, and a manufacturing method thereof. Alternatively, one embodiment of the present invention can provide a semiconductor device with low power consumption and a manufacturing method thereof. Alternatively, one embodiment of the present invention can provide a semiconductor device that operates at high speed and a manufacturing method thereof. Alternatively, one embodiment of the present invention can provide a novel semiconductor device and a manufacturing method thereof.

Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have to have all of these effects. Effects other than these may be extracted from the description in the specification, drawings, and claims.

1A and 1B are perspective views showing an example of the configuration of a semiconductor device.
2A and 2B are plan views showing examples of the configuration of a semiconductor device.
3A, 3B, and 3C are cross-sectional views showing examples of the configuration of a semiconductor device.
4A and 4B are cross-sectional views showing examples of the configuration of a semiconductor device.
5A and 5B are cross-sectional views showing examples of the configuration of a semiconductor device.
6A and 6B are cross-sectional views showing examples of the configuration of a semiconductor device.
7A is a circuit diagram showing an example of the configuration of a memory cell, and FIG. 7B is a perspective view showing an example of the configuration of a semiconductor device.
8A, 8B, and 8C are plan views showing examples of the configuration of a semiconductor device.
9A and 9B are cross-sectional views showing examples of the configuration of a semiconductor device.
10A and 10B are cross-sectional views showing examples of the configuration of a semiconductor device.
11A and 11B are cross-sectional views showing examples of the configuration of a semiconductor device.
FIG. 12 is a cross-sectional view showing an example of the configuration of a semiconductor device.
13A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 13B and 13C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
14A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 14B and 14C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
15A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 15B and 15C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
16A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 16B and 16C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
17A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 17B and 17C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
18A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 18B and 18C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
19A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 19B and 19C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
20A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 20B and 20C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
21A is a circuit diagram showing an example of the configuration of a memory cell, and FIG. 21B is a plan view showing an example of the configuration of a semiconductor device.
FIG. 22 is a cross-sectional view showing an example of the configuration of a semiconductor device.
FIG. 23 is a cross-sectional view showing an example of the configuration of a semiconductor device.
FIG. 24 is a cross-sectional view showing an example of the configuration of a semiconductor device.
FIG. 25 is a diagram illustrating an example of a hysteresis characteristic.
26A and 26B are diagrams illustrating the carrier concentration dependence of Hall mobility, and Fig. 26C is a cross-sectional view illustrating an indium oxide film.
FIG. 27 is a block diagram illustrating an example of the configuration of a semiconductor device.
28A and 28B are perspective views illustrating a configuration example of a semiconductor device.
FIG. 29 is a block diagram illustrating the CPU.
30A and 30B are perspective views of a semiconductor device.
31A and 31B are perspective views of a semiconductor device.
FIG. 32 is a conceptual diagram illustrating the hierarchy of a storage device.
33A and 33B are diagrams illustrating an example of an electronic component.
34A, 34B, and 34C are diagrams showing an example of a mainframe computer. Fig. 34D is a diagram showing an example of space equipment. Fig. 34E is a diagram showing an example of a storage system applicable to a data center.
35A and 35B are cross-sectional STEM images according to the example.
36A and 36B are diagrams showing input voltage waveforms in a write-endurance test.
37A and 37B are diagrams showing the results of a write-endurance test according to an example, and IV characteristics according to an example.
FIG. 38 is a diagram showing the results of the rewrite endurance test according to the example.

Embodiments will be described in detail using the drawings. However, the present invention is not limited to the following description, and those skilled in the art will readily understand that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

In the configuration of the invention described below, the same parts or parts with similar functions will be denoted by the same reference numerals in different drawings, and repeated explanations will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

The ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes, stacking order, or placement order. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conduction. In this specification, the term "transistor" includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).

In this specification, a transistor using metal oxide in a semiconductor layer and a transistor having metal oxide in a channel formation region may be referred to as an OS transistor. Furthermore, a transistor having silicon in a channel formation region may be referred to as a Si transistor.

In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. It has a region (also called a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and drain through the channel formation region. In this specification, a channel formation region refers to a region through which current mainly flows.

Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

Note that impurities in a semiconductor refer to, for example, elements other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect level density of the semiconductor or reduce the crystallinity. When the semiconductor is a metal oxide, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the metal oxide. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (also referred to as _VO ) in the metal oxide.

In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. An oxynitride refers to a material whose composition contains more nitrogen than oxygen. Here, when referring to an oxynitride, the composition may contain more oxygen than nitrogen, or may contain more nitrogen than oxygen, or the nitrogen and oxygen contents may be equal.

To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

In this specification, the term "content" refers to the proportion of a component contained in a film. For example, when a metal oxide layer contains metal element X, metal element Y, and metal element Z, and the atomic numbers of metal element X, metal element Y, and metal element Z contained in the metal oxide layer are _Ax , _Ay , and _Az , respectively, the content of metal element X can be expressed as _Ax /( _Ax + _Ay + _Az ). Furthermore, when the ratio of the atomic numbers of metal element X, metal element Y, and metal element Z in the metal oxide layer (atomic ratio) is expressed as _Bx : _{By:Bz ,} the content of metal element X can be expressed as _Bx /( _Bx + _By + _Bz ).

Note that the terms "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by placing a superscript bar above the number; however, due to formatting constraints, in this specification, numbers may be expressed by placing a - (minus sign) before them instead of placing a bar above them. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with { }.

Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of between -10 degrees and 10 degrees, inclusive. Therefore, it also includes cases in which the angle is between -5 degrees and 5 degrees, inclusive. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of between -20 degrees and 20 degrees, inclusive. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of between 80 degrees and 100 degrees, inclusive. Therefore, it also includes cases in which the angle is between 85 degrees and 95 degrees, inclusive. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of between 70 degrees and 110 degrees, inclusive.

In this specification, "connection" includes, as an example, "electrical connection." Note that "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Furthermore, even if there is a time during the operation of the circuit when no electrical signal is exchanged or an electrical potential interaction occurs between A and B, if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B, then it can still be defined that "A and B are indirectly connected."

An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, this would include a case where a capacitive element is connected between A and B, or a case where a transistor gate insulating film or the like is present between A and B. Therefore, it cannot be said that "the transistor gate (A) and the transistor source or drain (B) are indirectly connected."

Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another from a power supply, GND, etc.

Unless otherwise specified, in this specification, off-state current refers to the leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or cut-off state). Unless otherwise specified, the off state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).

In this specification and elsewhere, a tapered shape refers to a shape in which at least a portion of the side of a structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable for the structure to have a region in which the angle (also called the taper angle) between the inclined side and the substrate surface or the surface on which the structure is to be formed is greater than 0 degrees and less than 90 degrees. The side of the structure, the substrate surface, and the surface on which the structure is to be formed do not necessarily have to be completely flat; they may be approximately planar with a slight curvature, or approximately planar with slight irregularities.

In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as A has an area located on B. Similarly, when it is stated that A is in contact with B or A overlaps with B, at least a portion of A is in contact with B or overlaps with B. Therefore, it can be rephrased as A has an area in contact with B or A has an area overlapping with B, respectively. Similarly, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as A has an area covering B.

In this specification, "edges that match or approximately match" and "side surfaces that match or approximately match" refer to at least a portion of the contours of stacked layers overlapping in a planar view. This includes, for example, cases where the upper and lower layers are processed using the same mask pattern, or where only a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the terms "edges that match or approximately match" or "side surfaces that match or approximately match" are also used.

In this specification, "step discontinuity" refers to a phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (e.g., a step, etc.).

In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

Note that in the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. Note that in this specification, the "X direction" refers to the direction along the X axis, and there is no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. Note that in this specification, the X direction may be referred to as the row direction, and the Y direction may be referred to as the column direction.

(Embodiment 1)
In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

One aspect of the present invention relates to a ferroelectric capacitor and a memory having a ferroelectric capacitor. In this specification, a capacitor that uses a ferroelectric layer as a dielectric layer is referred to as a ferroelectric capacitor. Also, a memory having a ferroelectric capacitor is referred to as a ferroelectric memory. In one aspect of the present invention, the ferroelectric capacitor has a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer. Therefore, the ferroelectric capacitor can be a MIM (Metal-Insulator-Metal) capacitor. Note that in a capacitor having a first electrode, a dielectric layer on the first electrode, and a second electrode on the dielectric layer, the first electrode may be referred to as the lower electrode of the capacitor, and the second electrode may be referred to as the upper electrode of the capacitor.

Ferroelectrics have the property that when a voltage is applied, the polarization aligns in a certain direction, and remains aligned even after the voltage application is stopped. Furthermore, reversing the polarity of the voltage reverses the polarization. Ferroelectric memory can function as non-volatile memory by applying the properties of ferroelectrics.

In this specification, etc., a semiconductor device may refer to a ferroelectric capacitor or a ferroelectric memory. A semiconductor device may also refer to a transistor included in a ferroelectric memory.

A metal oxide can be used for the ferroelectric layer. Examples of metal oxides include hafnium oxide, zirconium oxide, and hafnium zirconium oxide. When a metal oxide is used for the ferroelectric layer, if oxygen is released from the ferroelectric layer, the remanent polarization may decrease when data is repeatedly rewritten to the ferroelectric memory. Furthermore, if data is repeatedly rewritten to the ferroelectric memory, the withstand voltage of the ferroelectric capacitor may decrease. For these reasons, if oxygen is released from the ferroelectric layer, the reliability of the ferroelectric memory may decrease.

Therefore, in one aspect of the present invention, a first electrode is formed, an oxidation treatment is performed on the first electrode to form an oxide region, and then a ferroelectric layer is formed in contact with the oxide region. This makes it possible to suppress absorption of oxygen in the ferroelectric layer by the first electrode compared to when a ferroelectric layer is formed without forming an oxide region on the first electrode. This prevents oxygen from being desorbed from the ferroelectric layer, which would otherwise reduce the reliability of the ferroelectric memory. As a result, one aspect of the present invention can achieve a highly reliable semiconductor device. Here, an example of the oxidation treatment is a method in which an insulating layer containing oxygen is formed and then the insulating layer is removed.

In one embodiment of the present invention, the ferroelectric capacitor is a trench-type capacitor. In this specification, a trench-type capacitor refers to a capacitor in which a first electrode, a dielectric layer on the first electrode, and a second electrode on the dielectric layer are provided so as to have a region located inside an opening in an interlayer insulating layer. A trench-type capacitor can increase the capacitance per occupied area compared to, for example, a parallel-plate type capacitor. This allows the occupied area of the capacitor to be reduced while maintaining the capacitance. This makes it possible to achieve miniaturization or high integration of semiconductor devices.

In one aspect of the present invention, the first electrode is provided along the side of an opening in the interlayer insulating layer. To form the first electrode, a conductive film is first formed to cover the opening. Next, photoresist is applied to the conductive film, and anisotropic etching is performed on the entire surface of the photoresist to form a resist mask inside the opening. The conductive film is then processed to form the first electrode. When forming the first electrode using this method, the first electrode can be formed so that the height of the top surface of the first electrode from a reference plane is lower than the height of the top surface of the interlayer insulating layer from the reference plane. The reference plane can be, for example, the top surface of the substrate. The resist mask is removed after the first electrode is formed.

Furthermore, by forming the first electrode using the above-described method, the angle of the top surface of the first electrode relative to the top surface of the substrate can be made greater than 0°. In other words, the top surface of the first electrode has a tapered shape. This prevents electric field concentration in the ferroelectric layer near the top surface of the first electrode. This prevents dielectric breakdown in the ferroelectric layer, resulting in a highly reliable semiconductor device.

<Configuration Example 1 of Semiconductor Device>
1A and 1B are perspective views illustrating a structural example of a semiconductor device according to one embodiment of the present invention, each illustrating a structural example of a capacitor 100. FIG. 1B illustrates a cross-sectional structural example in which a portion of the structure in FIG. 1A is omitted.

FIGS. 2A and 2B are plan views showing an example configuration of a semiconductor device according to one embodiment of the present invention. FIG. 2A shows an example configuration of a capacitor 100. Some elements of FIG. 2A are omitted in FIG. 2B.

Figure 3A is a cross-sectional view taken along dashed lines A1-A2 in Figures 2A and 2B. Figure 3B is a cross-sectional view taken along dashed lines B1-B2 in Figures 2A and 2B. Figure 3C is a cross-sectional view taken along dashed lines C1-C2 in Figure 3A. Figures 3A to 3C show an example configuration of capacitor 100. Note that Figure 3C is also referred to as a plan view, and more specifically, can be said to be a plan view showing an example cross-sectional configuration taken along dashed lines C1-C2. Figure 4A is an enlarged view of capacitor 100 shown in Figure 3A.

In Figures 1A to 4A, the X, Y, and Z directions are indicated by arrows. Note that the directions do not necessarily have to match between Figures 1A to 4A. In subsequent figures, the X, Y, and Z directions do not necessarily have to match between the figures.

The semiconductor device shown in Figures 1A to 4A has an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a capacitor 100 on the conductive layer 110, and an insulating layer 180 on the conductive layer 110 and on the insulating layer 140. Here, the insulating layer 140 and the insulating layer 180 function as interlayer insulating layers and preferably have flat upper surfaces. Furthermore, the insulating layer 140 can function as a base insulating layer.

The insulating layer 140 and the insulating layer 180 can be made of, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride oxide, and silicon nitride. The conductive layer 110 is preferably made of a highly conductive material such as tungsten, copper, or aluminum.

Capacitor 100 has a conductive layer 115 on conductive layer 110, a ferroelectric layer 130 on conductive layer 115 and on insulating layer 180, and a conductive layer 120 on ferroelectric layer 130. Note that in Figure 2B, the conductive layer 120, ferroelectric layer 130, and insulating layer 180 are omitted from Figure 2A.

Conductive layer 115 has a region that functions as one of the pair of electrodes of capacitor 100. Conductive layer 120 has a region that functions as the other of the pair of electrodes of capacitor 100. In capacitor 100, ferroelectric layer 130 is sandwiched between conductive layer 115 and conductive layer 120. Therefore, capacitor 100 constitutes an MIM capacitor. Here, capacitor 100 is a ferroelectric capacitor because it has a ferroelectric layer as its dielectric layer. Note that conductive layer 115 is also referred to as the lower electrode of capacitor 100. Also, conductive layer 120 is also referred to as the upper electrode of capacitor 100.

Figures 1A to 4A show an example in which conductive layer 110 and conductive layer 120 are arranged in a strip shape. Note that in this specification, strip shape refers to a shape having an area extending in a certain direction (e.g., the X direction, Y direction, or Z direction). Figures 1A to 4A show an example in which conductive layer 110 extends in the Y direction and conductive layer 120 extends in the X direction.

As shown in Figures 1A to 4A, an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. The conductive layer 115, ferroelectric layer 130, and conductive layer 120 of the capacitor 100 are provided inside the opening 190. Therefore, the capacitor 100 is a trench-type capacitor. This allows for a larger capacitance per occupied area compared to when the capacitor 100 is, for example, a parallel-plate capacitor. This allows for a smaller occupied area of the capacitor 100 while maintaining the capacitance of the capacitor 100. This allows for miniaturization or higher integration of semiconductor devices. Note that in the plan view, the shape of the bottom of the opening 190 is shown as the shape of the opening 190.

The thicker the insulating layer 180, the greater the capacitance per occupied area in the capacitor 100. On the other hand, if the insulating layer 180 is made too thick, the productivity of the semiconductor device decreases. The thickness of the insulating layer 180 in the region overlapping with the conductive layer 110 is, for example, preferably 30 nm to 3000 nm, more preferably 50 nm to 1000 nm, even more preferably 100 nm to 800 nm, still more preferably 200 nm to 700 nm, and even more preferably 300 nm to 600 nm, and is typically 400 nm.

2A, 2B, and 3C show an example in which the shape of the opening 190 in plan view is circular. By making the shape of the opening 190 in plan view circular, the processing accuracy when forming the opening 190 can be improved. Therefore, the opening 190 can be formed in a fine size. However, the present invention is not limited to this. In plan view, the opening 190 can be, for example, a circle or an approximately circle such as an ellipse, a polygon such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygon with rounded corners. Note that the circle is not limited to a perfect circle. Furthermore, the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).

Figures 1A, 1B, 3A, 3B, and 4A show an example in which the side surface of the opening 190 in the insulating layer 180 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. This configuration makes it possible to miniaturize or increase the integration density of semiconductor devices.

The conductive layer 115 is provided along the side surface of the opening 190 in the insulating layer 180. The conductive layer 115 also has a region in contact with the conductive layer 110. Here, Figures 1B, 3A, 3B, and 4A show an example in which the conductive layer 110 has a recess at a position overlapping the opening 190. In this case, the bottom of the opening 190 includes the bottom surface of the recess in the conductive layer 110. The sidewall of the opening 190 also includes the side surface of the recess in the conductive layer 110 and the side surface of the insulating layer 180.

In this specification, the sidewall of an opening refers to the side surface of the layer in which the opening is formed, within the opening. Also, if the opening reaches A, the top surface of A can be referred to as the bottom of the opening.

By having a recess in the conductive layer 110 at a position overlapping the opening 190, the contact area between the conductive layer 110 and the conductive layer 115 can be increased compared to when the recess is not present. This reduces the contact resistance between the conductive layer 110 and the conductive layer 115.

If the thickness of the conductive layer 115 is too thick, the conductive layer 120 will not be able to be provided inside the opening 190. Alternatively, the volume of the conductive layer 120 inside the opening 190 will be small. On the other hand, if the thickness of the conductive layer 115 is too thin, the electrical resistance of the conductive layer 115 will be high. The thickness of the conductive layer 115 is preferably, for example, 1 nm to 30 nm, more preferably 2 nm to 20 nm, and even more preferably 3 nm to 10 nm, and can be typically 5 nm.

The ferroelectric layer 130 is provided on the conductive layer 115 and on the insulating layer 180 so as to have an area in contact with the conductive layer 115 inside the opening 190. The ferroelectric layer 130 is provided so as to cover the conductive layer 115. The ferroelectric layer 130 is provided along the side and top surfaces of the conductive layer 115 inside the opening 190. The top surface of the ferroelectric layer 130 and the side surface opposite the conductive layer 115 can be in contact with the conductive layer 120.

Ferroelectric materials that can be used for the ferroelectric layer 130 include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Ferroelectric materials include materials in which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 can be set appropriately. For example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Ferroelectric materials include materials in which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. The ratio of the number of zirconium atoms to the number of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. In addition, as the ferroelectric, piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO _x (X is a real number greater than 0)), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used. In addition, as the ferroelectric, GaFeO ₃ with a κ-alumina structure may be used.

In the above description, metal oxides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides obtained by adding nitrogen to the above metal oxides may be used. For example, perovskite-type oxynitrides such as SrTaO ₂ N and BaTaO ₂ N may be used as ferroelectrics.

Furthermore, the ferroelectric may be, for example, a mixture or compound made of multiple materials selected from the materials listed above. For example, the ferroelectric may have a layered structure made of multiple materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change not only depending on the film formation conditions but also on various processes. For this reason, in this specification, the term ferroelectric is used to refer not only to materials that exhibit ferroelectricity, but also to materials that can have ferroelectricity.

Metal oxides containing hafnium and/or zirconium can exhibit ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing hafnium and/or zirconium can exhibit ferroelectricity even in very small areas. Therefore, by using metal oxides containing hafnium and/or zirconium, miniaturization of semiconductor devices can be achieved. A representative example of a metal oxide containing hafnium and zirconium is HfZrO _X. Furthermore, a metal oxide in which Y (yttrium) is added to HfZrO _X can also be used. Adding Y (yttrium) to HfZrO _X can enhance ferroelectricity.

Ferroelectricity is believed to be manifested when an external electric field displaces oxygen or nitrogen in crystals contained in the ferroelectric layer. It is also believed that the manifestation of ferroelectricity depends on the crystalline structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to manifest ferroelectricity, the insulating layer must contain crystals. It is particularly preferable for an insulating layer to contain crystals with an orthorhombic crystalline structure, as this will manifest ferroelectricity. The crystalline structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having both an amorphous structure and a crystalline structure.

Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the concentration of oxygen vacancies in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in an oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

Metal oxides containing one or both of hafnium and zirconium are preferred as ferroelectric layers because, as mentioned above, they can exhibit ferroelectricity even in thin films of only a few nanometers. The film thickness of the ferroelectric layer 130 is preferably 0.1 nm to 30 nm, more preferably 1 nm to 20 nm, and even more preferably 5 nm to 15 nm, and is typically 10 nm.

Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in a small area, making them preferable materials for forming ferroelectric layers. For example, ferroelectricity can be achieved even when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ² or less, 10 μm ² or less, 1 μm ² or less, or 0.1 μm ² or less. Ferroelectricity can also be achieved even when the area is 10,000 nm ² or less, or 1,000 nm ² or less. By using a ferroelectric layer with a small area, the occupied area of the capacitor 100 can be reduced.

Here, when a metal oxide or metal oxynitride is used as the ferroelectric layer 130, if oxygen contained in the ferroelectric layer 130 is desorbed, the remanent polarization may decrease when data is repeatedly rewritten to a ferroelectric memory including the capacitor 100. Furthermore, if data is repeatedly rewritten to a ferroelectric memory including the capacitor 100, the breakdown voltage of the capacitor 100 may decrease. Therefore, if oxygen is desorbed from the ferroelectric layer 130, the reliability of the ferroelectric memory may decrease.

Therefore, in one embodiment of the present invention, the conductive layer 115 has an oxide region 115ox. The oxide region 115ox includes a region in contact with the ferroelectric layer 130. For example, the region of the conductive layer 115 in contact with the ferroelectric layer 130 and the region nearby are defined as the oxide region 115ox. For example, after forming the conductive layer 115 and before forming the ferroelectric layer 130, the conductive layer 115 is subjected to an oxidation treatment to form the oxide region 115ox. The oxygen content in the oxide region 115ox is higher than the oxygen content in the region of the conductive layer 120 in contact with the ferroelectric layer 130, for example.

As a result, compared to when the ferroelectric layer 130 is formed without forming the oxide region 115ox in the conductive layer 115, it is possible to prevent oxygen contained in the ferroelectric layer 130 from being absorbed by the conductive layer 115. This prevents oxygen from being released from the ferroelectric layer 130, which would otherwise cause a decrease in the reliability of the ferroelectric memory. As a result, one aspect of the present invention makes it possible to realize a highly reliable semiconductor device.

In this specification, the oxide region 115ox is included in the conductive layer 115, that is, the oxide region 115ox can be part of the conductive layer 115. Note that the oxide region 115ox does not necessarily have to be included in the conductive layer 115.

For the conductive layer 115, it is preferable to use a conductive material that maintains low electrical resistance even when oxidized. This allows the electrical resistance of the oxide region 115ox to be maintained low. Therefore, an increase in the electrical resistance of the conductive layer 115 due to the formation of the oxide region 115ox can be suppressed. Therefore, even when the oxide region 115ox is formed in the conductive layer 115, a semiconductor device that operates at high speed can be realized. For example, a conductive material containing nitrogen is preferably used for the conductive layer 115. For example, titanium nitride, tantalum nitride, ruthenium nitride, nitrides containing molybdenum, nitrides containing tungsten, titanium, and aluminum, nitrides containing tantalum and aluminum, etc. can be used for the conductive layer 115.

The oxide region 115ox can contain an oxide of an element contained in the conductive layer 115, for example, a metal element. Furthermore, if the conductive layer 115 contains nitrogen, the oxide region 115ox can contain an oxynitride of an element contained in the conductive layer 115, for example, a metal element. For example, if titanium nitride is used as the conductive layer 115, the oxide region 115ox can contain titanium oxide and titanium oxynitride.

An example of an oxidation process for forming the oxide region 115ox is to form an insulating layer containing oxygen and then remove the insulating layer. The insulating layer containing oxygen can be made of silicon oxide, for example.

Figure 4B shows an example in which the entire conductive layer 115 shown in Figure 4A is an oxide region 115ox. If the conductive layer 115 is thin, the above-mentioned oxidation treatment may cause the entire conductive layer 115 to become the oxide region 115ox. Even in this case, by using a conductive material for the conductive layer 115 that maintains low electrical resistance even after oxidization, the conductive layer 115 can function as one of a pair of electrodes of the capacitor 100.

4A and 4B, the upper end surface 103 of the conductive layer 115 can be located at a lower height from the reference plane than the upper surface 105 of the insulating layer 180. The reference plane can be, for example, the upper surface of the substrate or the upper surface of the insulating layer 140. The angle θ of the upper end surface 103 relative to the reference plane can be greater than 0°. That is, the upper end surface 103 can have a tapered shape. Specifically, the height from the reference plane of the end of the upper end surface 103 opposite the insulating layer 180 (toward the center of the opening 190) can be lower than the height from the reference plane of the end of the upper end surface 103 on the insulating layer 180 side. Here, the upper end surface 103 can be rephrased as the upper surface of the conductive layer 115, specifically the upper surface including the top part of the conductive layer 115 (the part with the highest height from the reference plane).

As a result, electric field concentration in the ferroelectric layer 130 near the upper end surface 103 can be suppressed. This prevents dielectric breakdown in the ferroelectric layer 130, resulting in a highly reliable semiconductor device.

Here, the larger the angle θ, the more effectively electric field concentration in the ferroelectric layer 130 near the upper end surface 103 can be suppressed. On the other hand, if the angle θ is too large, it becomes difficult to fabricate the conductive layer 115. In light of the above, the angle θ is preferably greater than 5° and less than 85°, more preferably 10° to 80°, even more preferably 15° to 70°, and even more preferably 20° to 60°.

Note that Figures 4A and 4B show an example in which the region 102 between the upper surface 105 of the insulating layer 180 and the side surface of the opening 190 has a curved portion. By having the curved portion in the region 102, the ferroelectric layer 130 can cover the region 102 with good coverage. This makes it possible to prevent, for example, discontinuities in the ferroelectric layer 130, thereby realizing a highly reliable semiconductor device.

Furthermore, Figures 4A and 4B show an example in which region 101 between the side and bottom surfaces of conductive layer 115 within the recess of conductive layer 110 has a curved portion. By having region 101 have a curved portion, it is possible to suppress electric field concentration in ferroelectric layer 130 near region 101. This makes it possible to prevent dielectric breakdown of ferroelectric layer 130, resulting in a highly reliable semiconductor device.

The conductive layer 120 is provided on the ferroelectric layer 130 so as to have a region inside the opening 190 that faces the conductive layer 115 with the ferroelectric layer 130 sandwiched between them. The conductive layer 120 is provided so as to fill the opening 190. Note that Figures 1A to 3B show an example in which the upper end of the ferroelectric layer 130 coincides or approximately coincides with the lower end of the conductive layer 120.

In Figures 1A, 1B, 3A, 3B, etc., an example is shown in which the conductive layer 120 has a two-layer structure including a conductive layer 120_1 and a conductive layer 120_2 on the conductive layer 120_1. The conductive layer 120_1 can be provided so as to fill the opening 190.

When the conductive layer 120_1 is provided to fill the opening 190, the ferroelectric layer 130 can be provided to cover the conductive layer 120_1, and the conductive layer 115 can be provided to cover the ferroelectric layer 130 in the cross section shown in FIG. 3C. Furthermore, the oxide region 115ox can be provided, for example, to cover the entire outer periphery of the ferroelectric layer 130. For example, if the opening 190 in the insulating layer 180 has a circular shape in a planar view, the conductive layer 120_1 can be provided at the center of the circle. Furthermore, the outer peripheries of the conductive layer 120_1, the ferroelectric layer 130, and the conductive layer 115 can be concentrically arranged around the center of the opening 190.

3C, 4A, and 4B show the width D of the opening 190 in the insulating layer 180. Specifically, width D is the width of the opening 190 in the region between region 101 and region 102. For example, if the shape of the opening 190 in a planar view is circular, width D corresponds to the diameter of the circle. By making the film thickness of the conductive layer 120_1 thicker than the film thickness of the conductive layer 115, the film thickness of the ferroelectric layer 130, and width D, the conductive layer 120_1 can be provided to fill the opening 190. For example, if the film thickness of the conductive layer 115 is 5 nm, the film thickness of the ferroelectric layer 130 is 10 nm, and width D is 60 nm, the conductive layer 120_1 can be provided to fill the opening 190 by making the film thickness of the conductive layer 120_1 outside the opening 190 15 nm or more.

The film thickness of the conductive layer 120_1 outside the opening 190 is preferably, for example, 15 nm or more and 100 nm or less, more preferably 20 nm or more and 70 nm or less, and even more preferably 25 nm or more and 50 nm or less, and can typically be 30 nm.

When the conductive layer 120_1 is provided to fill the opening 190, it is preferable to use a conductive material for the conductive layer 120_1 that has a larger thermal expansion coefficient than the conductive material used for the conductive layer 120_2. This makes it easier for tensile stress to be applied from the conductive layer 120_1 to the ferroelectric layer 130 when the temperature is lowered after the heat treatment. The application of tensile stress to the ferroelectric layer 130 makes it easier for the crystal structure of the ferroelectric layer 130 to exhibit ferroelectricity. For example, crystals having an orthorhombic crystal structure are more likely to be formed in the ferroelectric layer 130. This increases the proportion of crystals having an orthorhombic crystal structure in the ferroelectric layer 130, thereby increasing the amount of remanent polarization. As a result, a highly reliable semiconductor device can be realized.

The conductive layer 120_2 is preferably made of a material with high conductivity, for example, a material with higher conductivity than the conductive layer 120_1. This allows the electrical resistance of the conductive layer 120 to be lower than when the conductive layer 120 has a single-layer structure of the conductive layer 120_1, for example. Therefore, a semiconductor device that operates at high speed can be realized.

The thickness of the conductive layer 120_2 in the region not overlapping with the opening 190 is preferably, for example, 5 nm to 500 nm, more preferably 10 nm to 100 nm, even more preferably 20 nm to 70 nm, and even more preferably 30 nm to 50 nm. Increasing the thickness of the conductive layer 120_2 makes it easier to reduce the electrical resistance of the conductive layer 120. For example, making the thickness of the conductive layer 120_2 in the region not overlapping with the opening 190 equal to or greater than the thickness of the conductive layer 120_1 in that region makes it easier to reduce the electrical resistance of the conductive layer 120. For example, if the thickness of the conductive layer 120_1 outside the opening 190 is 30 nm, the thickness of the conductive layer 120_2 in that region is preferably 30 nm or greater, more preferably 35 nm or greater, and typically 40 nm.

As mentioned above, it is preferable to use a material with a larger thermal expansion coefficient than conductive layer 120_2 for conductive layer 120_1, and a material with higher conductivity than conductive layer 120_2 for conductive layer 120_1. For example, it is preferable to use titanium nitride for conductive layer 120_1 and tungsten for conductive layer 120_2.

As described above, a semiconductor device having capacitor 100 can be a highly reliable semiconductor device.

Figures 5A and 5B show an example in which the insulating layer 180 shown in Figures 3A and 3B has a three-layer structure consisting of insulating layer 180a, insulating layer 180b on insulating layer 180a, and insulating layer 180c on insulating layer 180b. Also, Figures 5A and 5B show an example in which the top surface of insulating layer 180b is flat. Note that insulating layer 180 may have a two-layer structure, or a stacked structure of four or more layers.

The insulating layer 180a and the insulating layer 180c can be made of an oxygen barrier insulating layer. By using an oxygen barrier insulating layer as the insulating layer 180a, it is possible to prevent the conductive layer 110 from oxidizing and increasing its electrical resistance. By using an oxygen barrier insulating layer as the insulating layer 180c, it is possible to prevent the conductive layer 120 from oxidizing and increasing its electrical resistance. As a result, a semiconductor device that operates at high speed can be realized.

In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The term "barrier properties" refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen, when described as a corresponding substance, refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, a substance bonded to hydrogen, such as a water molecule or OH ⁻ . Note that impurities, when described as a corresponding substance, refer to impurities in a channel formation region or a semiconductor layer, unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (such as N ₂ O, NO, and NO ₂ ), a copper atom, and the like. Note that oxygen, when described as a corresponding substance, refers to at least one of, for example, an oxygen atom, an oxygen molecule, and the like.

For example, silicon nitride, silicon nitride oxide, oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, etc. can be used for insulating layer 180a and insulating layer 180c. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

The insulating layer 180b can be made of a material with a lower dielectric constant than the insulating layers 180a and 180c. This can prevent parasitic capacitance from forming between the conductive layer 110 and the conductive layer 120, for example. This allows for a semiconductor device that operates at high speed. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 180b.

The thickness of insulating layer 180b is preferably equal to or greater than the thicknesses of insulating layers 180a and 180c. This effectively prevents the formation of the parasitic capacitance described above. For example, the thickness of insulating layer 180b in the region overlapping with conductive layer 110 is preferably 60 nm to 3000 nm, more preferably 60 nm to 1000 nm, even more preferably 100 nm to 800 nm, still more preferably 200 nm to 600 nm, and even more preferably 300 nm to 400 nm, and is typically 350 nm.

Figures 6A and 6B are diagrams showing an example in which the conductive layer 115 shown in Figures 3A and 3B does not have an oxide region 115ox, and an insulating layer 116 is provided between the conductive layer 115 and the ferroelectric layer 130. As shown in Figures 6A and 6B, the insulating layer 116 is provided on the conductive layer 115 and on the insulating layer 180 so as to have an area in contact with the conductive layer 115 inside the opening 190. The insulating layer 116 is provided so as to cover the conductive layer 115. The insulating layer 116 is provided along the side and top surfaces of the conductive layer 115 inside the opening 190. The insulating layer 116 can function as a dielectric for the capacitor 100.

In the example shown in Figures 6A and 6B, the ferroelectric layer 130 is provided on the insulating layer 116. The ferroelectric layer 130 is provided inside the opening 190 and along the side and top surfaces of the insulating layer 116.

Even when the capacitor 100 has the configuration shown in Figures 6A and 6B, the oxygen contained in the ferroelectric layer 130 can be prevented from being absorbed by the conductive layer 115, compared to when the insulating layer 116 is not provided and the conductive layer 115 does not have the oxide region 115ox. This makes it possible to prevent oxygen from being released from the ferroelectric layer 130. As a result, a highly reliable semiconductor device can be realized.

The insulating layer 116 can be made of, for example, a nitride film, an oxide film, or an oxynitride film. It is preferable to use a material with a high dielectric constant for the insulating layer 116, as this increases the capacitance of the capacitor 100. The insulating layer 116 can be made of, for example, a silicon nitride film, a titanium oxide film, or a hafnium oxynitride film.

Furthermore, it is preferable to make the film thickness of the insulating layer 116 as thin as possible compared to the film thickness of the ferroelectric layer 130, as this increases the electrostatic capacitance of the capacitor 100. The film thickness of the insulating layer 116 is preferably 0.1 nm to 10 nm, more preferably 0.2 nm to 5 nm, even more preferably 0.3 nm to 3 nm, and even more preferably 0.5 nm to 1 nm.

<Configuration Example 2 of Semiconductor Device>
7A is a circuit diagram showing an example of the configuration of a memory cell 150. The memory cell 150 has a capacitor 100 and a transistor 200. As described above, the capacitor 100 is a ferroelectric capacitor. Therefore, the memory cell 150 is a ferroelectric memory.

One of the pair of electrodes of the capacitor 100 is connected to the wiring PL. The other of the pair of electrodes of the capacitor 100 is connected to one of the source and drain of the transistor 200. The other of the source and drain of the transistor 200 is connected to the wiring BL. The gate of the transistor 200 is connected to the wiring WL.

The wiring PL functions as a power supply line for applying a predetermined potential to one of a pair of electrodes of the capacitor 100. The wiring BL functions as a bit line for writing data to the memory cell 150 and reading data from the memory cell 150. The wiring WL functions as a word line for controlling whether the transistor 200 is turned on or off.

Figure 7B is a perspective view showing an example configuration of a memory cell 150. Figure 8A is a plan view showing an example configuration of a memory cell 150. Figures 8B and 8C are plan views showing some elements selected from Figure 8A.

Figure 9A is a cross-sectional view taken along dashed lines A1-A2 in Figures 8A to 8C. Figure 9B is a cross-sectional view taken along dashed lines B1-B2 in Figures 8A to 8C. Figure 10A is a cross-sectional view taken along dashed lines A3-A3 in Figures 8A to 8C. Figure 10B is a cross-sectional view taken along dashed lines B3-B4 in Figures 8A to 8C.

Figures 9A and 9B show an example configuration of the capacitor 100. The configuration of the capacitor 100 shown in Figures 9A and 9B is similar to that of the capacitor 100 shown in Figures 3A and 3B, respectively. Note that the insulating layer 180 may have a laminated structure, similar to the insulating layer 180 shown in Figures 5A and 5B, for example.

The semiconductor device shown in Figures 7B to 10B includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a capacitor 100 on the conductive layer 110, an insulating layer 180 on the conductive layer 110 and on the insulating layer 140, a transistor 200 on the capacitor 100, an insulating layer 280 on the capacitor 100 and on the insulating layer 180, an insulating layer 283 on the transistor 200 and on the insulating layer 280, an insulating layer 285 on the insulating layer 283, a conductive layer 244a, a conductive layer 244b, and a conductive layer 245 on the conductive layer 244a, the conductive layer 244b, and the insulating layer 285. Here, the insulating layer 280 and the insulating layer 285 function as interlayer insulating layers and preferably have flat top surfaces.

The transistor 200 includes a conductive layer 120, conductive layers 240a and 240b on an insulating layer 280, a semiconductor layer 230 on the conductive layer 120, the conductive layer 240a, and the conductive layer 240b, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. The semiconductor layer 230 can be made of, for example, a metal oxide. In this case, the transistor 200 is an OS transistor.

The conductive layer 260 has a region that functions as the gate electrode of the transistor 200. The insulating layer 250 has a region that functions as the gate insulating layer of the transistor 200. The conductive layer 120 has a region that functions as one of the source electrode and drain electrode of the transistor 200. The conductive layer 240a and the conductive layer 240b function as the other of the source electrode and drain electrode of the transistor 200 and are connected to each other via the conductive layer 244a, the conductive layer 244b, and the conductive layer 245.

Figure 8B shows only the conductive layer 120, semiconductor layer 230, conductive layer 240a, conductive layer 240b, and insulating layer 280b from the elements shown in Figure 8A. Figure 8C shows only the conductive layer 120, conductive layer 240a, conductive layer 240b, and insulating layer 280b from the elements shown in Figure 8A. In other words, Figure 8C omits the semiconductor layer 230 from Figure 8B.

In the memory cell 150, the conductive layer 110 has a region that functions as the wiring PL shown in FIG. 7A. The conductive layer 260 has a region that functions as the wiring WL shown in FIG. 7A. The conductive layer 245 has a region that functions as the wiring BL shown in FIG. 7A.

Figures 7B to 10B show an example in which the conductive layer 110, the conductive layer 260, and the conductive layer 245 are arranged in a strip shape. Figures 7B to 10B show an example in which the conductive layer 245 extends in the X direction, and the conductive layer 110 and the conductive layer 260 extend in the Y direction. That is, Figures 7B to 10B show an example in which, in a plan view, the wiring PL is arranged parallel to the wiring WL and perpendicular to the wiring BL. Note that the wiring PL does not have to be arranged parallel to the wiring WL, and may be arranged parallel to the wiring BL, for example.

Figure 7B and Figures 9A to 10B show an example in which the insulating layer 280 has a three-layer structure consisting of an insulating layer 280a, an insulating layer 280b on insulating layer 280a, and an insulating layer 280c on insulating layer 280b. Note that the insulating layer 280 may have a two-layer structure or a stacked structure of four or more layers.

As shown in Figures 9A and 9B, the insulating layer 280a has a region in contact with the conductive layer 120. Specifically, the insulating layer 280a has a region in contact with the side surface of the conductive layer 120. The insulating layer 280a may have a region in contact with the top surface of the conductive layer 120, and may also have a region in contact with the ferroelectric layer 130. Furthermore, the insulating layer 280a may have a region in contact with the top surface of the insulating layer 180.

Insulating layers 280a, 280b, and 280c have grooves 290. Grooves 290 extend in a direction parallel to the extension direction of conductive layer 260.

In this specification, the term "groove" can be alternatively referred to as a "slit" or "trench." Furthermore, the term "groove portion" can be alternatively referred to as a "slit portion" or "trench portion." Furthermore, the term "groove portion" can also be alternatively referred to as a "slit" or "trench."

The groove 290 has a region that reaches the conductive layer 120. The groove 290 is provided as a recess in the region of the insulating layer 280a that does not overlap with the conductive layer 120. Note that Figure 9A shows an example in which the conductive layer 120 has a recess. This recess can be included in the groove 290. However, this recess does not have to be included in the groove 290. Figures 9A to 10A show an example in which the depth of the groove 290 in the region that does not overlap with the conductive layer 120 is deeper than the depth of the groove 290 in the region that overlaps with the conductive layer 120.

When the bottom surface of the recess in the conductive layer 120 is included in the groove 290, the bottom of the groove 290 includes the bottom surface of the recess in the conductive layer 120. Furthermore, the sidewalls of the groove 290 include the side surfaces of the recess in the conductive layer 120, the side surfaces of the insulating layer 280a, the side surfaces of the insulating layer 280b, and the side surfaces of the insulating layer 280c.

In the above case, the bottom of groove 290 includes the upper surface of conductive layer 120 and the upper surface of insulating layer 280a. In other words, the bottom of groove 290 includes the bottom surface of the recess in conductive layer 120 and the bottom surface of the recess in insulating layer 280a. Furthermore, the sidewalls of groove 290 include the side surfaces of the recess in conductive layer 120, the side surfaces of insulating layer 280a, the side surfaces of insulating layer 280b, and the side surfaces of insulating layer 280c. Groove 290 includes the groove in conductive layer 120, the groove in insulating layer 280a, the groove in insulating layer 280b, and the groove in insulating layer 280c.

In this specification, the groove 290 provided in the insulating layer 280a may be referred to as the first groove. Furthermore, the groove 290 provided in the insulating layer 280b may be referred to as the second groove. Furthermore, the groove 290 provided in the insulating layer 280c may be referred to as the third groove. The first groove, second groove, and third groove may be provided so as to overlap one another. Furthermore, the recesses in the conductive layer 120 may be provided so as to overlap the first groove, second groove, and third groove. Note that the ordinal numbers may be interchanged as appropriate.

The groove portion 290 can be formed by processing the insulating layer 280c, the insulating layer 280b, and the insulating layer 280a using an etching process. Dry etching is particularly preferable because it is suitable for fine processing. Furthermore, for example, the dry etching process can form a recess in the conductive layer 120. The recess can be included in the groove portion 290 as described above.

Here, it is preferable to process insulating layer 280b using conditions different from those for processing insulating layer 280a. Specifically, it is preferable to process insulating layer 280b under conditions that provide a high selectivity to insulating layer 280a. This makes it possible to prevent a portion of insulating layer 280a from being unintentionally removed when processing insulating layer 280b.

In the regions that do not overlap with the groove portion 290, the top surfaces of the insulating layer 280a, the insulating layer 280b, and the insulating layer 280c can be flattened. For example, after the insulating layer 280a is formed, a planarization treatment is performed on the insulating layer 280a. Chemical mechanical polishing (CMP) treatment is suitable as the planarization treatment. Note that etching treatment (also referred to as etch-back treatment) may also be performed as the planarization treatment. After the planarization treatment is performed on the insulating layer 280a, the insulating layer 280b and the insulating layer 280c can be formed on the insulating layer 280a, thereby flattening the top surfaces of the insulating layer 280b and the insulating layer 280c. Here, by performing a planarization process on the insulating layer 280a, it is possible to make the film thickness of the insulating layer 280a in the region that overlaps with the conductive layer 120 thinner than the film thickness of the insulating layer 280a in the region that does not overlap with the conductive layer 120.

The insulating layers 280a and 280c can be made of an oxygen-barrier insulating layer. The insulating layer 280b can be made of a material with a lower dielectric constant than the insulating layers 280a and 280c. Using an oxygen-barrier insulating layer as the insulating layer 280a can prevent the conductive layer 120 from oxidizing and increasing its electrical resistance. Using an oxygen-barrier insulating layer as the insulating layer 280c can prevent the conductive layers 240a and 240b from oxidizing and increasing their electrical resistance. Using a material with a lower dielectric constant than the insulating layers 280a and 280c as the insulating layer 280b can prevent the formation of parasitic capacitance, for example, between the conductive layers 120 and 240a and between the conductive layers 120 and 240b. This allows for a semiconductor device that operates at high speed.

The insulating layer 280a can be made of the same material as that used for the insulating layer 180a shown in Figures 5A and 5B. The insulating layer 280b can be made of the same material as that used for the insulating layer 180b shown in Figures 5A and 5B. The insulating layer 280c can be made of the same material as that used for the insulating layer 180c shown in Figures 5A and 5B.

Here, it is preferable that the thickness of insulating layer 280b is equal to or greater than the thickness of insulating layer 280c, since this effectively prevents the formation of parasitic capacitance, for example, between conductive layer 120 and conductive layer 240a, and between conductive layer 120 and conductive layer 240b. When the thickness of insulating layer 280b is equal to or greater than the thickness of insulating layer 280c, i.e., when the thickness of insulating layer 280c is equal to or less than the thickness of insulating layer 280b, the thickness of insulating layer 280c can be equal to or less than the thickness of insulating layer 280a in the region that does not overlap with conductive layer 120. Furthermore, the thickness of insulating layer 280c can be, for example, approximately the same as the thickness of insulating layer 280a in the region that overlaps with conductive layer 120. Note that, for example, the thickness of insulating layer 280b affects the channel length of transistor 200. Therefore, for example, the thickness of insulating layer 280b is appropriately set according to the design value of the channel length of transistor 200. The thickness of the insulating layer 280c may be set to match the design value of the channel length of the transistor 200.

The insulating layer 280b preferably has a region containing excess oxygen, which allows oxygen to be supplied from the insulating layer 280b to the semiconductor layer 230. Therefore, oxygen vacancies and _VOH in the channel formation region of the transistor 200 can be reduced.

It is preferable that the concentrations of impurities such as hydrogen or water in insulating layer 180, insulating layer 280a, insulating layer 280b, and insulating layer 280c are reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of transistor 200. For example, by depositing insulating layer 180, insulating layer 280a, insulating layer 280b, and insulating layer 280c using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentrations in insulating layer 180, insulating layer 280a, insulating layer 280b, and insulating layer 280c, respectively, can be reduced.

At least some of the components of the transistor 200 are arranged inside the groove 290. Specifically, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged so that at least a portion of each is located inside the groove 290. Furthermore, the conductive layers 240a and 240b are arranged so as to face each other across the groove 290 in a planar view. Note that the groove 290 may be arranged not only between the insulating layers 280a, 280b, and 280c, but also between the conductive layers 240a and 240b.

The width of the groove 290 in a direction perpendicular to its extension direction, for example, the width of the groove 290 in the X direction, is set by the film thickness of each of the semiconductor layer 230, insulating layer 250, and conductive layer 260 provided inside the groove 290. The width of the groove 290 in a direction perpendicular to its extension direction is, for example, preferably 5 nm to 300 nm, more preferably 5 nm to 200 nm, more preferably 5 nm to 100 nm, more preferably 10 nm to 60 nm, more preferably 10 nm to 50 nm, more preferably 20 nm to 40 nm, and even more preferably 20 nm to 30 nm.

Figures 8A to 9A show an example in which the inner side of conductive layer 240a (the groove 290 side in plan view) coincides or approximately coincides with the sidewall of groove 290. Also shown is an example in which the inner side of conductive layer 240b (the groove 290 side in plan view) coincides or approximately coincides with the sidewall of groove 290. This configuration allows conductive layer 240a, conductive layer 240b, and groove 290 to be formed simultaneously.

The semiconductor layer 230 is provided so as to cover a portion of the groove 290. The semiconductor layer 230 has a region in contact with the top surface of the conductive layer 240a outside the groove 290, a region in contact with the side surface of the conductive layer 240a, a region in contact with the top surface of the conductive layer 240b, and a region in contact with the side surface of the conductive layer 240b. The semiconductor layer 230 also has a region in contact with the conductive layer 120 inside the groove 290. Specifically, the semiconductor layer 230 can have a region in contact with the bottom surface of the recess of the conductive layer 120 inside the groove 290, and a region in contact with the side surface of the recess.

Furthermore, the semiconductor layer 230 has a region that runs along the sidewall of the groove 290. Inside the groove 290, the semiconductor layer 230 can have a region that contacts the side surface of the insulating layer 280a, a region that contacts the side surface of the insulating layer 280b, and a region that contacts the side surface of the insulating layer 280c.

8A to 10B show an example in which the end of the semiconductor layer 230 is located outside the end of the conductive layer 240a and the end of the conductive layer 240b in the region where it does not overlap the groove 290. In the example shown in FIGS. 8A to 10B, it can be said that the semiconductor layer 230 covers the entire conductive layer 240a and the entire conductive layer 240b. Note that the lower end of the semiconductor layer 230 may have a region that coincides or approximately coincides with the upper end of the conductive layer 240a and a region that coincides or approximately coincides with the upper end of the conductive layer 240b in the region where it does not overlap the groove 290. Furthermore, the end of the semiconductor layer 230 may be located inside the end of the conductive layer 240a and the end of the conductive layer 240b in the region where it does not overlap the groove 290. That is, the end of the semiconductor layer 230 may have a region that overlaps with the conductive layer 240a and a region that overlaps with the conductive layer 240b in the region where it does not overlap the groove 290.

For example, a metal oxide can be used for the semiconductor layer 230. It is preferable to use indium oxide (also referred to as indium oxide) as the metal oxide. This enables the transistor 200 to have a large on-state current. Furthermore, the transistor 200 can have a small off-state current. Indium oxide will be described in detail in Embodiment 2.

A metal oxide other than indium oxide may be used for the semiconductor layer 230. Examples of metal oxides other than indium oxide include oxides containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO). By using IGZO for the semiconductor layer 230, the transistor 200 can have a low off-state current.

The thickness of the semiconductor layer 230 is preferably 1 nm to 50 nm, more preferably 2 nm to 30 nm, even more preferably 2.5 nm to 20 nm, still more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. It is preferable that at least a portion of the semiconductor layer 230 has a region with the above thickness. For example, it is preferable that the channel formation region of the semiconductor layer 230 has a region with the above thickness. Setting the thickness of the semiconductor layer 230 within the above range can improve the crystallinity of the semiconductor layer 230. By improving the crystallinity of the semiconductor layer 230, the semiconductor layer 230 can have crystal grains.

The insulating layer 250 is provided on the semiconductor layer 230 so as to have a region located inside the groove 290. The insulating layer 250 can be provided to cover the semiconductor layer 230.

The conductive layer 260 is provided on the insulating layer 250 so as to have a region located inside the groove 290. The conductive layer 260 can be provided so as to fill the groove 290. The conductive layer 260 has a region inside the groove 290 that faces the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

As described above, the semiconductor layer 230 is provided inside the groove 290. Furthermore, the transistor 200 has a configuration in which one of the source and drain electrodes (here, the conductive layer 120) is located on the bottom and the other of the source and drain electrodes (here, the conductive layer 240a and the conductive layer 240b) is located on the top, so that current flows vertically. In other words, a channel is formed along the sidewall of the groove 290.

In the semiconductor layer 230, the region inside the groove 290 facing the conductive layer 260 with the insulating layer 250 sandwiched therebetween and the region nearby function as the channel formation region of the transistor 200. The region of the semiconductor layer 230 near the conductive layer 120 functions as one of the source region and the drain region. At least one of the region of the semiconductor layer 230 near the conductive layer 240a and the region of the semiconductor layer 230 near the conductive layer 240b functions as the other of the source region and the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region. The source region and the drain region are low-resistance regions with higher carrier concentrations than the channel formation region.

By using the above configuration, a channel formation region and a source region or drain region can be formed inside the groove 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, source region, and drain region are provided separately on the XY plane. This allows for miniaturization or high integration of semiconductor devices.

The channel length of transistor 200 is the distance between the source region and the drain region in semiconductor layer 230. In Figure 9A, the channel length Lc of transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, channel length Lc is the distance between the edge of the region where semiconductor layer 230 and conductive layer 240a contact and the edge of the region where semiconductor layer 230 and conductive layer 120 contact. Note that, in a cross-sectional view, channel length Lc may also be the distance between the edge of the region where semiconductor layer 230 and conductive layer 240b contact and the edge of the region where semiconductor layer 230 and conductive layer 120 contact.

The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. On the other hand, the channel length of transistor 200 can be set by the film thicknesses of insulating layers 280a, 280b, and 280c. Therefore, the channel length of transistor 200 can be made into an extremely fine structure that is below the exposure limit of photolithography (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of transistor 200, improving its frequency characteristics.

Note that the channel length of transistor 200 is determined by the film thicknesses of insulating layers 280a, 280b, and 280c. Therefore, the channel length does not affect the area occupied by transistor 200, for example, the area of transistor 200 in a planar view. By setting the channel length of transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in forming trench 290, etc.

From the above, the channel length of a transistor included in a semiconductor device of one embodiment of the present invention is preferably 0.1 nm to 1 μm, more preferably 1 nm to 500 nm, and even more preferably 5 nm to 300 nm.

Here, by having a recess in the conductive layer 120, for example, at a position overlapping the groove portion 290 of the insulating layer 280a, the height of the lower surface of the insulating layer 250 and the height of the lower surface of the conductive layer 260 inside the groove portion 290 can each be lower than when the recess is not present. Here, the height of each surface can be determined using the surface on which the transistor is formed as a reference. Note that the surface used as a reference is not limited to the surface on which the transistor is formed. For example, the top surface of the substrate on which the semiconductor device is provided can also be used as a reference.

By lowering the height of the bottom surface of the conductive layer 260, a gate electric field can be more easily applied to the semiconductor layer 230. This improves the electrical characteristics of the transistor 200. Furthermore, regardless of whether the conductive layer 120 or the conductive layer 240a and the conductive layer 240b is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved.

When forming the semiconductor layer 230 in a semiconductor device according to one embodiment of the present invention, a semiconductor film is formed so as to cover the groove 290, and then the semiconductor film is processed to remove a portion of the semiconductor film. The semiconductor film can be processed using an etching process. In particular, dry etching is preferably used because it enables miniaturization or high integration of the semiconductor device. Here, when the semiconductor film is processed to form the semiconductor layer 230, a portion of the region of the semiconductor film that is along the sidewall of the groove 290 is removed. The removal of this region is preferably performed under isotropic conditions.

When processing a semiconductor film using a dry etching process under isotropic conditions, ions contained in the etching gas may not be sufficiently accelerated. This can result in a long processing time for the semiconductor film. Therefore, if, for example, a portion of the ferroelectric layer 130 is exposed due to the formation of the groove 290, the ferroelectric layer 130 will be exposed to the etching gas for a long time. This makes the ferroelectric layer 130 more susceptible to unintentional processing. Therefore, by providing the insulating layer 280a as described above, even when processing the semiconductor film requires a long time, it is possible to prevent, for example, the ferroelectric layer 130 from being unintentionally processed and partially removed. This prevents fluctuations in the electrical characteristics of, for example, the capacitor 100, resulting in a highly reliable semiconductor device. Furthermore, since the manufacturing yield of the semiconductor device can be increased, a semiconductor device that can be manufactured at low cost can be provided. Furthermore, for example, a material with a low etching selectivity with respect to the semiconductor layer 230 can be used for the ferroelectric layer 130. This broadens the range of materials that can be used for the ferroelectric layer 130.

The insulating layer 283 is located on the conductive layer 260 and the insulating layer 250. The insulating layer 283 can be a barrier insulating layer against impurities such as hydrogen. This can prevent impurities such as hydrogen from penetrating into the transistor 200. This makes it possible to provide a highly reliable semiconductor device. An example of a barrier insulating layer against hydrogen is a silicon nitride film. Details of the material for the barrier insulating layer against hydrogen will be described later.

Insulating layer 285 is located on insulating layer 283. Insulating layer 285, insulating layer 283, insulating layer 250, and semiconductor layer 230 have opening 270a reaching conductive layer 240a and opening 270b reaching conductive layer 240b. Conductive layer 244a is provided in opening 270a, and conductive layer 244b is provided in opening 270b. For example, conductive layer 244a is provided to fill opening 270a, and conductive layer 244b is provided to fill opening 270b. Conductive layer 244a may have a region in opening 270a that contacts conductive layer 240a. Conductive layer 244b may have a region in opening 270b that contacts conductive layer 240b. Hereinafter, openings 270a and 270b may be collectively referred to as opening 270. Furthermore, conductive layer 244a and conductive layer 244b may be collectively referred to as conductive layer 244.

Conductive layer 245 is provided on insulating layer 285, conductive layer 244a, and conductive layer 244b. Conductive layer 245 can have a region in contact with the top surface of conductive layer 244a and a region in contact with the top surface of conductive layer 244b. As a result, conductive layer 240a and conductive layer 240b can be connected via conductive layer 244a, conductive layer 245, and conductive layer 244b.

The conductive layer 245 overlaps with the conductive layer 260 via the insulating layer 283 and the insulating layer 285. This reduces parasitic capacitance compared to, for example, a case where the conductive layer 240a and the conductive layer 240b extend in the Y direction without providing the conductive layer 245. For example, the parasitic capacitance between the conductive layer 240a and the conductive layer 260 and the parasitic capacitance between the conductive layer 240b and the conductive layer 260 can be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that the height of the top surfaces of the conductive layer 244a and the conductive layer 244b is preferably the same as or approximately the same as the height of the top surface of the insulating layer 285.

As described above, the conductive layer 245 intersects with the conductive layer 260 in a planar view, for example, perpendicular or substantially perpendicular to the conductive layer 260. This allows the area where the conductive layer 245 and the conductive layer 260 overlap to be smaller than when the conductive layer 245 and the conductive layer 260 are arranged parallel to each other in a planar view. This reduces the parasitic capacitance generated between the conductive layer 260 and the conductive layer 245. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that, for example, if the insulating layer 285 is sufficiently thick and the parasitic capacitance per unit area generated between the conductive layer 260 and the conductive layer 245 is negligibly small, the conductive layer 260 and the conductive layer 245 may be arranged parallel to each other in a planar view.

Figures 9A and 10B show an example in which the conductive layer 240a has a two-layer structure made up of a conductive layer 240a_1 and a conductive layer 240a_2 on the conductive layer 240a_1. Also, an example in which the conductive layer 240b has a two-layer structure made up of a conductive layer 240b_1 and a conductive layer 240b_2 on the conductive layer 240b_1 is shown.

9A and 10B show an example in which opening 270a is provided not only in insulating layer 285, insulating layer 283, insulating layer 250, and semiconductor layer 230, but also in conductive layer 240a_2. Similarly, FIG. 9A shows an example in which opening 270b is provided in conductive layer 240b_2. Also, an example is shown in which opening 270a reaches conductive layer 240a_1, and opening 270b reaches conductive layer 240b_1. In this case, conductive layer 244a can have a region in contact with the top surface of conductive layer 240a_1 and the side surface of conductive layer 240a_2. Similarly, conductive layer 244b can have a region in contact with the top surface of conductive layer 240b_1 and the side surface of conductive layer 240b_2.

By having conductive layer 244a in contact with the top surface of conductive layer 240a_1, the contact resistance between conductive layer 240a and conductive layer 244a can be reduced, even if the contact resistance per unit area between conductive layer 240a_2 and conductive layer 244a is greater than the contact resistance per unit area between conductive layer 240a_1 and conductive layer 244a. Furthermore, by having conductive layer 244a in contact with the side surface of conductive layer 240a_2, the contact area between conductive layer 240a and conductive layer 244a can be increased compared to when conductive layer 244a is in contact only with the top surface of conductive layer 240a, for example. This reduces the contact resistance between conductive layer 240a and conductive layer 244a. Similarly, the conductive layer 244b contacts the top surface of the conductive layer 240b_1 and also contacts the side surface of the conductive layer 240b_2, thereby reducing the contact resistance between the conductive layer 240b and the conductive layer 244b.

Note that the conductive layer 240a_2 does not have to have the opening 270a, and the conductive layer 240b_2 does not have to have the opening 270b. In this case, the opening 270a reaches the top surface of the conductive layer 240a_2, and the opening 270b reaches the top surface of the conductive layer 240b_2. When the conductive layer 240a_2 does not have the opening 270a, the opening 270a can be formed more easily than when the conductive layer 240a_2 has the opening 270a. Similarly, when the conductive layer 240b_2 does not have the opening 270b, the opening 270b can be formed more easily than when the conductive layer 240b_2 has the opening 270b.

9A and 10B, the opening 270a includes an opening in the insulating layer 285, an opening in the insulating layer 283, an opening in the insulating layer 250, an opening in the semiconductor layer 230, and an opening in the conductive layer 240a_2. Similarly, in the example shown in FIG. 9A, the opening 270b includes an opening in the insulating layer 285, an opening in the insulating layer 283, an opening in the insulating layer 250, an opening in the semiconductor layer 230, and an opening in the conductive layer 240b_2. Note that the shape and size of the openings 270a and 270b in a planar view may differ depending on the layer. Furthermore, when the shape of the openings 270a and 270b in a planar view is circular, the openings in each layer may or may not be concentric.

Figures 9A to 10A show an example in which the conductive layer 260 has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 on the conductive layer 260_1. The conductive layer 260_1 can be disposed to surround the bottom and side surfaces of the conductive layer 260_2.

In the semiconductor device of one embodiment of the present invention, an insulating layer can be provided over the conductive layer 245 and the insulating layer 285. The insulating layer preferably serves as a barrier insulating layer against hydrogen. With this structure, hydrogen diffusion from above the transistor 200 to the semiconductor layer 230 can be suppressed.

Figures 11A and 11B are diagrams showing an example in which the insulating layer 180 shown in Figures 9A and 9B, respectively, has a three-layer structure consisting of insulating layer 180a, insulating layer 180b on insulating layer 180a, and insulating layer 180c on insulating layer 180b. In other words, Figures 11A and 11B show an example in which the insulating layer 180 has the same configuration as Figures 5A and 5B, respectively.

11A and 11B, among insulating layers 180a, 180b, and 180c, it is preferable that the concentration of impurities such as hydrogen or water is reduced in at least insulating layer 180c. By reducing the impurity concentration in insulating layer 180c, which is closest to semiconductor layer 230 among the layers included in insulating layer 180, it is possible to suppress the intrusion of impurities such as hydrogen or water into the channel formation region of transistor 200. For example, the hydrogen concentration in insulating layer 180c can be reduced by depositing insulating layer 180c using a sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas.

Insulating layer 180a and insulating layer 180b may be formed by a method other than sputtering. For example, insulating layer 180a can be formed using atomic layer deposition (ALD). In this case, insulating layer 180a can be formed so as to cover conductive layer 110 with good coverage. Insulating layer 180c may have a different film thickness from insulating layer 180a. For example, if insulating layer 180a is formed by ALD and insulating layer 180c is formed by sputtering, insulating layer 180c may have a thicker film thickness than insulating layer 180a.

Figure 12 shows an example in which the conductive layer 120 shown in Figure 11A has a three-layer structure consisting of a conductive layer 120_1, a conductive layer 120_2 on the conductive layer 120_1, and a conductive layer 120_3 on the conductive layer 120_2. Note that the conductive layer 120 shown in Figure 9A, for example, may have a three-layer stacked structure. Figure 12 shows an example in which the conductive layer 120_3 has a recess.

For the conductive layer 120_3, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a conductive metal oxide, or a conductive material that has the function of suppressing oxygen diffusion. For example, it is preferable to use a conductive material that contains oxygen for the conductive layer 120_3. Specifically, it is preferable to use an oxide conductor for the conductive layer 120_3. Examples of oxide conductors include indium tin oxide (In-Sn oxide, also referred to as ITO), indium tin oxide containing silicon oxide (also referred to as ITSO), and indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)).

By using an oxide conductor as the conductive layer 120_3, which is mainly in contact with the semiconductor layer 230, the contact resistance with the semiconductor layer 230 can be reduced. This shortens the current path between the source and drain, and increases the on-state current of the transistor 200. With this structure, the conductive layer 120 can maintain conductivity even when in contact with the semiconductor layer 230.

<Constituent materials of semiconductor device>
Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure.

[Semiconductor layer]
For example, a metal oxide can be used for the semiconductor layer 230. The metal oxide to be used has a band gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3.0 eV or more.

Indium oxide is preferably used as the semiconductor layer 230. Alternatively, a metal oxide other than indium oxide may be used as the semiconductor layer 230. In this case, for example, gallium oxide or zinc oxide can be used as the semiconductor layer 230. When a metal oxide other than indium oxide is used as the semiconductor layer 230, the metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

The metal oxide used for the semiconductor layer 230 can be IGZO. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) can be used. Alternatively, an oxide containing indium, gallium, tin, and zinc can be used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) can be used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) can be used.

Furthermore, it is preferable that the metal oxide containing indium and element M have a layered structure of multiple oxide layers with different chemical compositions. For example, consider an oxide layer with a two-layer structure consisting of a first layer and a second layer located immediately above the first layer. The atomic ratio of element M to the main component metal element in the metal oxide used for the first layer is preferably greater than the atomic ratio of element M to the main component metal element in the metal oxide used for the second layer. Furthermore, it is preferable that the atomic ratio of element M to In in the metal oxide used for the first layer is greater than the atomic ratio of element M to In in the metal oxide used for the second layer. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the first layer into the second layer.

Furthermore, the atomic ratio of In to the element M in the metal oxide used in the second layer is preferably larger than the atomic ratio of In to the element M in the metal oxide used in the first layer. With this structure, an OS transistor having this structure can have high on-state current and high frequency characteristics.

Specifically, for example, the metal oxide used in the first layer may have a composition of In:M:Zn = 1:3:2 (atomic ratio) or a similar composition, In:M:Zn = 1:3:4 (atomic ratio) or a similar composition, or In:M:Zn = 1:1:0.5 (atomic ratio) or a similar composition. Furthermore, the metal oxide used in the second layer may have a composition of In:M:Zn = 1:1:1 (atomic ratio) or a similar composition, In:M:Zn = 1:1:1.2 (atomic ratio) or a similar composition, In:M:Zn = 1:1:2 (atomic ratio) or a similar composition, or In:M:Zn = 4:2:3 (atomic ratio) or a similar composition. Note that a similar composition includes a range of 0.70 to 1.3 times the desired atomic ratio. For example, if the desired atomic ratio is 4, the atomic ratio of the nearby composition will be between 2.8 and 5.2.

In order to reduce the off-state current of a transistor, it is preferable to use, for example, IGZO as the metal oxide used in the semiconductor layer 230. When the semiconductor layer 230 contains IGZO, the amount of current flowing between the source and drain of the transistor when the gate-source voltage is 0 V is 1×10 ⁻²⁰ A or less per 1 μm of channel width at room temperature, 1×10 ⁻¹⁸ A or less at 85° C., or 1×10 ⁻¹⁶ A or less at 125° C.

As described above, in a transistor in which the semiconductor layer 230 includes IGZO, when the gate-source voltage is lower than the threshold voltage, the amount of current flowing per 1 μm of channel width is 1×10 ⁻¹⁶ A or less, preferably 1×10 ⁻¹⁸ A or less, and more preferably 1×10 ⁻²⁰ A or less. Depending on the situation, the amount of current flowing per 1 μm of channel width may be 1×10 ⁻²⁰ A or less, more preferably 1×10 ⁻²² A or less, and even more preferably 1×10 ⁻²⁴ A or less. In this specification, the operation of the transistor in this region may be referred to as an off state. In addition, the current flowing through the transistor at this time may be referred to as an off current.

Metal oxide structures can be divided into single-crystal structures and other structures (non-single-crystal structures). Non-single-crystal structures include, for example, a CAAC (c-axis aligned crystalline) structure, a polycrystalline structure, a nanocrystalline (nc) structure, a pseudo-amorphous (a-like) structure, and an amorphous structure. The structure of the metal oxide of one embodiment of the present invention is not particularly limited, and any of the above structures can be used. However, using a crystalline metal oxide, such as a CAAC structure or an nc structure, is preferable because it enables the production of a highly reliable semiconductor device.

Indium oxide is preferably used as the metal oxide. Crystalline indium oxide is particularly preferred. Details of crystalline indium oxide will be described later. Furthermore, the metal oxide may be In-Ga-Zn oxide (indium-gallium-zinc oxide), Ga-Zn oxide, or gallium oxide.

Also, metal oxides that can be used include those with an atomic ratio of In:Ga:Zn = 1:3:4, 1:3:2, 1:1:0.5, 1:1:1, 4:2:3, or 3:1:2. Also, metal oxides with an atomic ratio of In:Zn = 4:1 can be used.

Metal oxides can be formed preferably by sputtering or ALD. When metal oxides are formed by sputtering, films with high crystallinity or high film density can be formed. Furthermore, when metal oxides are formed using ALD, atoms can be deposited layer by layer, which has the advantages of enabling films with fewer defects such as pinholes, excellent coating properties, and low temperature film formation. After metal oxide formation, it is preferable to perform an impurity removal process to remove impurities (typically impurities such as water, hydrogen, carbon, and nitrogen) from the metal oxide film. Examples of impurity removal processes include plasma treatment, microwave treatment, and heat treatment.

Semiconductor materials other than metal oxides may be used for the semiconductor layer 230. Examples of such other semiconductor materials include semiconductors made of elemental elements and compound semiconductors.

Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. The boron nitride that can be used for the semiconductor layer 230 preferably has an amorphous structure. The boron arsenide that can be used for the semiconductor layer 230 preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[Insulating layer]
It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 116, insulating layer 140, insulating layer 180, insulating layer 250, insulating layer 280, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

For example, as transistors become more miniaturized and highly integrated, thinner gate insulating layers can cause problems such as leakage current. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer insulating layer can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength. Materials with a low dielectric constant can also be used for insulating layers that function as base insulating layers.

Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include, for example, silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.

Furthermore, a transistor using a metal oxide as a semiconductor layer can have stable electrical characteristics by being surrounded by an insulating layer that functions to suppress the permeation of impurities and oxygen. The insulating layer that functions to suppress the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that functions to suppress the permeation of impurities and oxygen can be made of metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; nitrides such as aluminum nitride or silicon nitride; or nitride oxides such as silicon nitride oxide.

Specific examples of insulating layer materials that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include nitrides such as aluminum nitride and silicon nitride. Other examples include metal nitrides such as silicon nitride oxide. Gallium oxide is also an example of insulating layer materials that function to suppress the permeation of oxygen.

Furthermore, an insulating layer, such as a gate insulating layer, that is in contact with a metal oxide layer or that is provided near a metal oxide layer is preferably an insulating layer that has a region containing excess oxygen. For example, when an insulating layer that has a region containing excess oxygen is in contact with a metal oxide layer or is located near the metal oxide layer, oxygen vacancies in the metal oxide layer can be reduced. Examples of insulating materials that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies. Examples of insulating layers that easily form a region containing excess oxygen include a silicon oxide film, a silicon oxynitride film, and a silicon oxide film with vacancies.

It is preferable to use a hydrogen barrier insulating layer as an insulating layer in contact with a metal oxide layer or an insulating layer provided near a metal oxide layer. The insulating layer's barrier properties against hydrogen can suppress the diffusion of hydrogen into the metal oxide layer. A hydrogen barrier insulating layer can also be said to be an insulating layer that has the function of suppressing the diffusion of hydrogen.

Insulating materials capable of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate. These metal oxides may also contain zirconium, such as oxides containing hafnium and zirconium (hafnium zirconium oxide).

An insulating layer that has the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides with an amorphous structure, some oxygen atoms have dangling bonds, which gives them a high ability to capture or fix hydrogen. Therefore, by having the insulating layer have an amorphous structure, the ability to capture or fix hydrogen can be enhanced.

By making the insulating layer an amorphous structure, it is possible to suppress the formation of grain boundaries. Suppressing the formation of grain boundaries can improve the flatness of the insulating layer. This makes the film thickness distribution of the insulating layer uniform, reducing areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It also makes it possible to uniform the film thickness distribution of films provided on the insulating layer. Furthermore, suppressing the formation of grain boundaries in the insulating layer can reduce leakage current caused by defect levels at the grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

Note that the insulating layer may contain crystalline regions and/or grain boundaries in some areas.

The ability to capture or fix the corresponding substance can also be said to have the property of making the corresponding substance difficult to diffuse. Therefore, the ability to capture or fix the corresponding substance can be rephrased as barrier properties.

Materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium, silicon nitride, and silicon nitride oxide.

The inorganic insulating layers listed as insulating layers capable of capturing or fixing hydrogen and insulating layers capable of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for oxygen barrier insulating layers include oxides containing either or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

1A to 10B show an example in which the insulating layer 140 has a single-layer structure. Note that the insulating layer 140 can also have a stacked structure of two or more layers. For example, the insulating layer 140 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer that has the function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, hafnium silicate film, or aluminum oxide film as the second insulating layer.

The insulating layer 250 is preferably a barrier insulating layer against hydrogen. The insulating layer 250 provided on the semiconductor layer 230 has barrier properties against hydrogen, which can prevent hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, a silicon nitride film has high barrier properties against hydrogen and is therefore suitable as the insulating layer 250.

Furthermore, since the insulating layer 250 is in contact with the semiconductor layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the semiconductor layer 230 to be captured or fixed more effectively. Therefore, the hydrogen concentration in the semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, _VOH in the channel formation region can be reduced, and the channel formation region can be made i-type or substantially i-type.

Furthermore, it is preferable to use an insulating layer having a region containing excess oxygen as the insulating layer 250. This allows oxygen to be supplied from the insulating layer 250 to the semiconductor layer 230, reducing oxygen vacancies in the semiconductor layer 230. A silicon oxide film or a silicon oxynitride film, for example, has a structure that is stable against heat, making it suitable as the insulating layer 250.

Figures 9A to 10B show an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can also have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 from two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of the functions of the insulating layer 250 include the function of extracting hydrogen from the semiconductor layer 230 and the function of suppressing diffusion of hydrogen into the semiconductor layer 230.

For example, the insulating layer 250 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer 230. For example, it is preferable to use an insulating layer that has the function of capturing or fixing hydrogen as the first insulating layer, and to use a barrier insulating layer against hydrogen as the second insulating layer. With this structure, the hydrogen concentration in the semiconductor layer 230 can be reduced and diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having the function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the semiconductor layer 230 can be reduced, and diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

Furthermore, for example, the insulating layer 250 can have a third insulating layer between the semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure consisting of a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having the function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having barrier properties against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the semiconductor layer 230, oxygen can be supplied to the semiconductor layer 230. Furthermore, providing the second insulating layer can prevent oxygen contained in the third insulating layer from diffusing into the conductive layer 260, thereby preventing oxidation of the conductive layer 260. It is also possible to prevent a decrease in the amount of oxygen supplied from the third insulating layer to the semiconductor layer 230.

Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure consisting of a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer. The fourth insulating layer is the layer in contact with the semiconductor layer 230 among the two or more layers that the insulating layer 250 has.

It is preferable to use an insulating layer that has a barrier property against oxygen as the fourth insulating layer. Note that the same configuration as the layers used in the three-layer structure described above can be applied to the first to third insulating layers. The fourth insulating layer is a layer that is in contact with the semiconductor layer 230. The fourth insulating layer's barrier property against oxygen can prevent oxygen from being released from the semiconductor layer 230.

For example, an aluminum oxide film may be used as the fourth insulating layer. An aluminum oxide film has the function of capturing or adhering hydrogen, or has barrier properties against hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side.

The insulating layer 250 may be made of a material that can have ferroelectric properties. In this case, the insulating layer 250 may be made of a material that can be used for the ferroelectric layer 130.

The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also known as the S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

Furthermore, the film thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less. It is preferable that each layer constituting the insulating layer 250 has a region with the above-mentioned film thickness in at least a portion thereof.

[Conductive layer]
For the conductive layers (conductive layer 110, conductive layer 115, conductive layer 120, conductive layer 240a, conductive layer 240b, conductive layer 244, conductive layer 245, conductive layer 260, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain low electrical resistance even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, IZO (registered trademark), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

Conductive materials primarily composed of tungsten, copper, or aluminum are preferred due to their high conductivity.

Moreover, multiple conductive layers formed from the above materials may be stacked. For example, a layered structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen. Moreover, a layered structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen. Moreover, a layered structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

Note that when a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as the gate electrode preferably has a stacked structure that combines a material containing the metal element described above and a conductive material containing oxygen. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is more easily supplied to the channel formation region.

Since the conductive layer 120, the conductive layer 240a, and the conductive layer 240b are each conductive layers in contact with the semiconductor layer 230, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has the function of suppressing oxygen diffusion. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 120, the conductive layer 240a, and the conductive layer 240b.

By using a conductive material containing oxygen for the conductive layer 120, the conductive layer 120 can maintain its conductivity even when it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240a and the conductive layer 240b, the conductive layer 240a and the conductive layer 240b can maintain their conductivity even when they absorb oxygen. Furthermore, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 140, this is also preferable because the conductive layer 120 can maintain its conductivity. For example, ITO, ITSO, In-Zn oxide, or the like is preferably used for each of the conductive layer 120, the conductive layer 240a, and the conductive layer 240b.

When the conductive layer 120, the conductive layer 240a, and the conductive layer 240b each have a stacked structure, by using a conductive material containing oxygen for the layer in the stacked structure that has the largest contact area with the semiconductor layer 230, it is possible to reduce the contact resistance between the conductive layer 120 and the semiconductor layer 230, between the conductive layer 240a and the semiconductor layer 230, and between the conductive layer 240b and the semiconductor layer 230.

9A and 10B show an example in which the conductive layer 240a has a two-layer structure including a conductive layer 240a_1 and a conductive layer 240a_2 on the conductive layer 240a_1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240a_2 and a material having higher conductivity than the conductive layer 240a_1 for the conductive layer 240a_2. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) for the conductive layer 240a_2 and tungsten for the conductive layer 240a_1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240a_1. By using an oxide conductor for the conductive layer 240a_2, which is primarily in contact with the semiconductor layer 230, the contact resistance with the semiconductor layer 230 can be reduced. Furthermore, by using a material with higher conductivity than an oxide conductor for the layer that constitutes the conductive layer 240a, the conductivity of the conductive layer 240a can be increased.

Note that a conductive material containing oxygen can be used for the conductive layer 240a_1, and a material having higher conductivity than the conductive layer 240a_1 can be used for the conductive layer 240a_2. In this case, an oxide conductor is used for the layer of the conductive layer 240a closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and drain can be shortened, and the on-state current of the transistor 200 can be increased.

Figure 9A shows an example in which the conductive layer 240b has a two-layer structure including a conductive layer 240b_1 and a conductive layer 240b_2 on the conductive layer 240b_1. The conductive layer 240b_1 can be made of the same material as that used for the conductive layer 240a_1. The conductive layer 240b_2 can be made of the same material as that used for the conductive layer 240a_2.

The conductive layer 260 has a region that functions as a gate electrode. It is preferable to use a highly conductive material such as tungsten or ruthenium for the conductive layer 260. It is also preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion for the conductive layer 260. As mentioned above, examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

Furthermore, the conductive layer 260 preferably uses a conductive material containing oxygen and the metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may also be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In-Zn oxide, and ITSO may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may also be used. Using such a material may make it possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may make it possible to capture hydrogen introduced from an outer insulating layer, etc.

The conductive layer 260 shown in Figures 9A to 10A has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, it is preferable to use a titanium nitride film as the conductive layer 260_1 and a tungsten film as the conductive layer 260_2. Alternatively, it is preferable to use a tantalum nitride film as the conductive layer 260_1 and a copper film as the conductive layer 260_2. With such a structure, the conductivity of the conductive layer 260 can be increased.

The conductive layer 260 may also have a stacked structure of three or more layers. For example, the conductive layer 260 may have a three-layer structure of a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

The conductive layers 244 and 245 can be formed using materials that can be used for the conductive layers 240a and 240b. For the conductive layers 244 and 245, for example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. Using a low-resistance conductive material can reduce wiring resistance.

For example, Figure 9A shows an example in which the conductive layer 244 and the conductive layer 245 have a single-layer structure. Note that the conductive layer 244 and the conductive layer 245 can also have a stacked structure of two or more layers.

[substrate]
Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

In this specification, a semiconductor substrate made of silicon is referred to as a silicon substrate.

The above is a description of the materials that can be used in the semiconductor device of this embodiment.

<Example of Manufacturing Method of Semiconductor Device>
13A to 20C , an example of a manufacturing method for a semiconductor device of one embodiment of the present invention, specifically, a capacitor 100, will be described. In the drawings illustrating an example of a manufacturing method for a semiconductor device, unless otherwise specified, each figure (A) is a plan view. Each figure (B) is a cross-sectional view taken along dashed line A1-A2 in each figure (A). Each figure (C) is a cross-sectional view taken along dashed line B1-B2 in each figure (A).

The thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and ALD.

Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC (Direct Current) sputtering, which uses a direct current power supply; and pulsed DC sputtering, which varies the voltage applied to the electrode in pulses. RF sputtering is primarily used to deposit insulating films, while DC sputtering is primarily used to deposit metal conductive films. Pulsed DC sputtering is primarily used to deposit compounds such as oxides, nitrides, and carbides using reactive sputtering.

CVD methods can also be classified into plasma-enhanced CVD (PECVD), which uses plasma; thermal CVD (TCVD: Thermal CVD), which uses heat; and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD: Metal CVD) and metal-organic CVD (MOCVD: Metal Organic CVD), depending on the source gas used.

Plasma CVD can produce high-quality films at relatively low temperatures. Furthermore, because thermal CVD does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in semiconductor devices can become charged up by receiving electrical charge from the plasma. When this happens, the accumulated electrical charge can destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, thermal CVD, which does not use plasma, does not cause such plasma damage, and can therefore increase the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be produced.

Also available ALD methods include thermal ALD, in which the reaction between the precursor and reactant is carried out using only thermal energy, and PEALD, which uses plasma-excited reactants.

Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that, although the metal oxide film formation method of one embodiment of the present invention uses the ALD method, it employs a high substrate temperature during film formation and/or performs an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these conditions.

The ALD method differs from film formation methods in which particles emitted from a target or the like are deposited, in that a film is formed by a reaction on the surface of the workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios.

CVD and ALD are different from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. ALD, in particular, has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

In addition, CVD methods can deposit films of any composition by adjusting the flow rate ratio of the source gases. For example, CVD methods can deposit films with continuously changing compositions by changing the flow rate ratio of the source gases while depositing the film. When depositing a film while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to when depositing films using multiple deposition chambers, as no time is required for transport or pressure adjustment. This can potentially increase the productivity of semiconductor devices.

Also, with the ALD method, films of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, films of any composition can be formed by controlling the number of cycles for each precursor.

Furthermore, the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed by wet film formation methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife printing, slit coating, roll coating, curtain coating, or knife coating.

Furthermore, when processing the thin films that make up the semiconductor device, methods such as photolithography can be used. Alternatively, the thin films can be processed using methods such as nanoimprinting, sandblasting, or lift-off. Furthermore, island-shaped thin films can also be directly formed using a film-forming method that uses a shielding mask such as a metal mask.

There are two typical photolithography methods. One is to form a resist mask on the thin film to be processed, process the thin film by etching or other methods, and then remove the resist mask. The other is to form a photosensitive thin film, then expose and develop it to process the thin film into the desired shape.

In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. Electron beams can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

Dry etching, wet etching, sandblasting, etc. can be used to etch thin films.

Below, an example of a method for manufacturing the semiconductor device shown in Figures 2A, 5A, and 5B will be described.

First, as shown in Figures 13A, 13B, and 13C, an insulating layer 140 is formed on a substrate (not shown), and then a conductive layer 110 is formed on the insulating layer 140. The conductive layer 110 can be formed by forming a conductive film that will become the conductive layer 110 and then processing the conductive film. The conductive film that will become the conductive layer 110 can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a 20-nm-thick tungsten film can be formed as the conductive film that will become the conductive layer 110 using a sputtering method.

Next, as shown in Figures 13A, 13B, and 13C, an insulating layer 180 is formed on the conductive layer 110 and the insulating layer 140. The insulating layer 180 can be formed by sequentially forming insulating layers 180a, 180b, and 180c. The insulating layers 180a, 180b, and 180c can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. For example, a 5-nm-thick silicon nitride film can be formed by ALD as the insulating layer 180a. For example, a 370-nm-thick silicon oxide film can be formed by sputtering as the insulating layer 180b.

Insulating layer 180c may be formed using the same method as insulating layer 180a, or a different method. Furthermore, the thickness of insulating layer 180c may be different from that of insulating layer 180a. For example, if insulating layer 180a is formed by ALD and insulating layer 180c is formed by sputtering, the thickness of insulating layer 180a can be thinner than that of insulating layer 180c. For example, the thickness of insulating layer 180a can be 5 nm, and the thickness of insulating layer 180c can be 60 nm.

Here, it is preferable to perform planarization treatment such as CMP treatment on the upper surface of the insulating layer 180. For example, it is preferable to perform planarization treatment on the upper surface of the insulating layer 180b. For example, by forming a silicon oxide film with a thickness of 370 nm as the insulating layer 180b and then performing planarization treatment on the upper surface of the insulating layer 180b, the thickness of the insulating layer 180b in the region overlapping with the conductive layer 110 can be set to 350 nm. Note that when planarization treatment is performed on the upper surface of the insulating layer 180b, the insulating layer 180c can be formed on a flat surface.

Next, as shown in Figures 13A, 13B, and 13C, the insulating layer 180 is processed to form an opening 190 that reaches the conductive layer 110. Here, it is preferable to process the insulating layer 180 using a highly anisotropic etching method. Processing by dry etching is particularly preferable because it is suitable for fine processing. Note that a recess may be formed in the conductive layer 110 at a position that overlaps the opening 190. Figure 13B shows an example in which a region 101 with curved corners is formed in the conductive layer 110. For example, by adjusting the etching conditions, a region 101 with curved corners can be formed in the conductive layer 110.

Next, as shown in Figures 13A, 13B, and 13C, a conductive film 115f is formed to cover the opening 190. The conductive film 115f is formed along the sidewall of the opening 190, the top surface of the conductive layer 110, and the top surface of the insulating layer 180c.

Because the conductive film 115f is formed inside the opening 190, it is preferably formed using the CVD method or the ALD method. This allows the conductive film 115f to be formed with good coverage. For example, a titanium nitride film with a thickness of 5 nm can be formed as the conductive film 115f using the CVD method.

Subsequently, as shown in Figures 13A, 13B, and 13C, photoresist 131p is applied onto conductive film 115f. As photoresist 131p, for example, at least one of a resist film, an SOC (Spin On Carbon) film, and an SOG (Spin On Glass) film can be formed. As photoresist 131p, for example, an SOC film, an SOG film on the SOC film, and a resist film on the SOG film can be formed.

Next, as shown in Figures 14A, 14B, and 14C, anisotropic etching is performed on the entire surface of the photoresist 131p. This removes part of the photoresist 131p. For example, it is preferable to remove part of the photoresist 131p by dry etching. As a result, a resist mask 131 is formed inside the opening 190.

Anisotropic etching of the photoresist 131p can be performed, for example, until the upper surface of the conductive film 115f is exposed. For example, anisotropic etching of the photoresist 131p can be performed until a predetermined time has elapsed since the upper surface of the conductive film 115f is exposed. In this case, the height of the upper surface of the resist mask 131 from the reference plane can be made lower than the height of the upper surface 105 of the insulating layer 180 from the reference plane. Note that the upper surface 105 can specifically be the upper surface of the insulating layer 180c.

Subsequently, as shown in Figures 15A, 15B, and 15C, the conductive film 115f is subjected to an etching process. As a result, a conductive layer 115 is formed inside the opening 190. The etching process can be performed using a dry etching method or a wet etching method. In particular, processing using a dry etching method is preferable because it is suitable for fine processing.

The etching process for the conductive film 115f can be performed, for example, until the upper surface 105 is exposed. In this case, the conductive layer 115 can be formed so that the height of the upper end surface 103 of the conductive layer 115 from the reference plane is lower than the height of the upper surface 105 from the reference plane.

Here, it is preferable to form the conductive layer 115 so that the upper end surface 103 has a tapered shape. Specifically, the conductive layer 115 can be formed so that the height from the reference plane of the end of the upper end surface 103 on the resist mask 131 side is lower than the height from the reference plane of the end of the upper end surface 103 on the insulating layer 180 side. By forming the conductive layer 115 so that the upper end surface 103 has a tapered shape, as described above, it is possible to prevent electric field concentration in the ferroelectric layer 130, which will be formed in a later process, near the upper end surface 103. This makes it possible to prevent dielectric breakdown of the ferroelectric layer 130 and produce a highly reliable semiconductor device.

Figures 15B and 15C show an example in which a curved portion is formed in region 102 between the top surface of insulating layer 180 and the side surface of opening 190. During the etching process on conductive film 115f, a curved portion may be formed in region 102 of insulating layer 180c.

Next, as shown in Figures 16A, 16B, and 16C, the resist mask 131 is removed. The resist mask 131 can be removed using, for example, a chemical solution. Alternatively, the resist mask 131 may be removed using an etching method.

Subsequently, as shown in Figures 17A, 17B, and 17C, oxidation treatment is performed on the conductive layer 115. As a result, an oxide region 115ox is formed in the conductive layer 115. In the example shown in Figures 17A to 17C, an insulating layer 133 containing oxygen is formed so as to have a region in contact with the exposed surface of the conductive layer 115. As a result, at least a portion of the conductive layer 115 is oxidized by the oxygen contained in the insulating layer 133, forming the oxide region 115ox. The oxide region 115ox is formed so as to include the region of the conductive layer 115 in contact with the insulating layer 133. Note that the insulating layer 133 is formed so as to fill, for example, the opening 190. The insulating layer 133 is also formed so as to have a region located on the upper surface 105.

An oxide insulating film, for example, a silicon oxide film, can be formed as the insulating layer 133. In particular, it is preferable to form a silicon oxide film as the insulating layer 133 by a CVD method using TEOS (Tetra-Ethyl- _Ortho -Silicate, chemical formula: Si( _OC2H5 ) ₄ ), since this allows semiconductor devices to be manufactured with high productivity.

The insulating layer 133 may be formed using the ALD method. For example, an insulating film with a low dielectric constant, such as a silicon oxide film, may be formed using the ALD method. In this case, the insulating layer 133 can be formed inside the opening 190 along the side and top surfaces of the conductive layer 115. When a silicon oxide film is formed as the insulating layer 133 using the ALD method, the film thickness of the insulating layer 133 is preferably 1 nm to 30 nm, more preferably 2 nm to 20 nm, and even more preferably 3 nm to 10 nm.

When the above-described oxidation treatment is performed by forming the insulating layer 133, as shown in Figures 18A, 18B, and 18C, the insulating layer 133 is removed after the oxide region 115ox is formed. This exposes the surface of the conductive layer 115, specifically the surface of the oxide region 115ox. The upper surface 105 is also exposed. The insulating layer 133 can be removed using, for example, wet etching. The insulating layer 133 may also be removed using dry etching.

17A to 18C, it is preferable to form the insulating layer 180c using a material with a high etching selectivity with respect to the insulating layer 133. This prevents at least a portion of the insulating layer 180c from being removed when the insulating layer 133 is removed. This prevents the insulating layer 180 from becoming thin. For example, when a silicon oxide film is formed as the insulating layer 133, a silicon nitride film can be formed as the insulating layer 180c. Note that by forming the insulating layer 180c on the insulating layer 180b, the insulating layer 180b can be formed using a material with a low etching selectivity with respect to the insulating layer 133. The insulating layer 180b can be formed using, for example, the same material as the insulating layer 133. For example, both the insulating layer 180b and the insulating layer 133 can be silicon oxide films. As described above, forming the insulating layer 180c on the insulating layer 180b broadens the range of materials that can be used for the insulating layer 180b.

17A to 18C . For example, heat treatment may be performed in an atmosphere containing oxygen. Alternatively, plasma treatment or microwave treatment may be performed in an atmosphere containing oxygen. Note that the atmosphere containing oxygen includes not only oxygen gas (O ₂ ) but also an atmosphere containing a gas of a compound containing oxygen, such as ozone (O ₃ ) or nitrous oxide (N ₂ O).

Here, as shown in Figures 6A and 6B, an insulating layer 116 may be formed to cover the conductive layer 115 without performing an oxidation treatment on the conductive layer 115. For example, a silicon nitride film, a titanium nitride film, or a hafnium oxynitride film may be formed as the insulating layer 116.

Next, as shown in Figures 19A, 19B, and 19C, the ferroelectric layer 130 is formed so as to have a region in contact with the oxide region 115ox. Because the ferroelectric layer 130 is formed inside the opening 190, it is preferably formed using the CVD method or the ALD method. This allows the ferroelectric layer 130 to be formed with good coverage. The ferroelectric layer 130 is formed to contain oxygen, and specifically, a metal oxide film or a metal oxynitride film is formed. For example, a 10 nm thick hafnium zirconium oxide film can be formed as the ferroelectric layer 130 using the ALD method.

By forming the oxide region 115ox in the conductive layer 115 and then forming the ferroelectric layer 130 so that it has a region in contact with the oxide region 115ox, it is possible to prevent oxygen contained in the ferroelectric layer 130 from being absorbed into the conductive layer 115, compared to when the ferroelectric layer 130 is formed without forming the oxide region 115ox. This prevents oxygen from being released from the ferroelectric layer 130, which would otherwise reduce the reliability of the ferroelectric memory. As described above, one aspect of the present invention makes it possible to manufacture a highly reliable semiconductor device.

Next, as shown in Figures 19A, 19B, and 19C, a conductive film 120f, which will become the conductive layer 120 in a later process, is formed on the ferroelectric layer 130. The conductive film 120f is formed so as to have a region located inside the opening 190. The conductive film 120f can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc.

Figures 19A, 19B, and 19C show an example in which a conductive film 120f_1 and a conductive film 120f_2 over the conductive film 120f_1 are formed as the conductive film 120f. The conductive film 120f_1 is a film that will become the conductive layer 120_1 in a later step. The conductive film 120f_2 is a film that will become the conductive layer 120_2 in a later step. The conductive film 120f_1 can be formed to fill the opening 190.

Figures 19A and 19B show the width D of the opening 190. By making the film thickness of the conductive film 120f_1 thicker than the film thickness of the conductive layer 115, the film thickness of the ferroelectric layer 130, and the width D, the conductive film 120f_1 can be formed to fill the opening 190.

When forming conductive film 120f_1 to fill opening 190, it is preferable to form conductive film 120f_1 using a conductive material with a larger thermal expansion coefficient than conductive film 120f_2. This makes it easier for tensile stress to be applied from conductive film 120f_1 to ferroelectric layer 130 when the temperature is lowered after heat treatment. This increases the amount of remanent polarization in ferroelectric layer 130, allowing for the manufacture of a highly reliable semiconductor device.

The conductive film 120f_2 is preferably formed using a material with high conductivity, for example, a material with higher conductivity than the conductive film 120f_1. This enables the manufacture of a semiconductor device that operates at high speed.

As the conductive film 120f_1, for example, a titanium nitride film with a thickness of 30 nm can be deposited using the CVD method. As the conductive film 120f_2, for example, a tungsten film with a thickness of 40 nm can be deposited using the CVD method.

The upper surface of the conductive film 120f may be subjected to planarization treatment such as CMP treatment. For example, the upper surface of the conductive film 120f_2 may be subjected to planarization treatment. For example, a film may be formed on the conductive film 120f_2, and planarization treatment may be performed on the film on the conductive film 120f_2 until the upper surface of the conductive film 120f_2 is exposed, thereby enabling the planarization treatment to be performed on the upper surface of the conductive film 120f_2.

Subsequently, as shown in Figures 20A, 20B, and 20C, the conductive film 120f is processed to form the conductive layer 120. Specifically, the conductive film 120f_2 is processed to form the conductive layer 120_2, and the conductive film 120f_1 is processed to form the conductive layer 120_1. For example, a resist mask is formed by photolithography, and then the conductive films 120f_2 and 120f_1 are processed according to the pattern of the resist mask to form the conductive layers 120_2 and 120_1, respectively. This processing can be performed using, for example, an etching process, and is preferably performed using dry etching, which facilitates fine processing.

20A, 20B, and 20C show an example in which not only the conductive film 120f but also the ferroelectric layer 130 is processed. The ferroelectric layer 130 can be processed using the same resist mask as that used to process the conductive film 120f. Alternatively, after processing the conductive film 120f to form the conductive layer 120, the resist mask may be removed and the ferroelectric layer 130 may be processed using the conductive layer 120 as a hard mask. When processing the ferroelectric layer 130 using the above method, the upper end of the ferroelectric layer 130 can be aligned with the lower end of the conductive layer 120, specifically, with the lower end of the conductive layer 120_1. By processing the ferroelectric layer 130, at least a portion of the upper surface of the insulating layer 180 can be exposed.

After forming the conductive layer 120, it is preferable to perform a heat treatment. This makes it easier for tensile stress to be applied from the conductive layer 120_1 to the ferroelectric layer 130 when the temperature is lowered after the heat treatment. This increases the amount of remanent polarization in the ferroelectric layer 130, resulting in a highly reliable semiconductor device. The heat treatment temperature can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. A typical temperature is 400°C ± 25°C (375°C to 425°C). The treatment time can be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When using an RTA (Rapid Thermal Annealing) device, the treatment time can be, for example, 1 second to 5 minutes.

This allows for the formation of a capacitance of 100.

11A and 11B, after performing the processes shown in FIGS. 13A to 20C, an insulating layer 280, a conductive layer 240a, and a conductive layer 240b are formed, and a groove 290 is formed in the insulating layer 280. Next, a semiconductor layer 230, an insulating layer 250, a conductive layer 260, an insulating layer 283, and an insulating layer 285 are formed. Next, an opening 270a reaching the conductive layer 240a and an opening 270b reaching the conductive layer 240b are formed in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230, respectively. Next, a conductive layer 244a is formed to fill the opening 270a, and a conductive layer 244b is formed to fill the opening 270b. Then, a conductive layer 245 is formed on the insulating layer 285, the conductive layer 244a, and the conductive layer 244b. As described above, a memory cell 150 having a capacitor 100 and a transistor 200 can be fabricated. Note that although Figures 20A to 20C show an example in which the conductive layer 120 is formed to extend in the X direction, when forming the memory cell 150, the conductive layer 120 is formed so as not to extend in the X direction, for example.

<Configuration Example 3 of Semiconductor Device>
An example of the configuration of a semiconductor device having a plurality of memory cells 150 will be described below.

Figure 21A is a circuit diagram showing an example configuration of 2 x 2 memory cells 150. Figure 21A shows example configurations of the 2 x 2 memory cells 150, including memory cell 150[1,1], memory cell 150[1,2], memory cell 150[2,1], and memory cell 150[2,2].

In the example shown in FIG. 21A, memory cell 150[1,1], memory cell 150[1,2], memory cell 150[2,1], and memory cell 150[2,2] have the same configuration as memory cell 150 shown in FIG. 7A. Here, in the example shown in FIG. 21A, wiring BL[1] is connected to memory cell 150[1,1] and memory cell 150[2,1] as wiring BL, and wiring BL[2] is connected to memory cell 150[1,2] and memory cell 150[2,2] as wiring BL. Furthermore, wiring WL[1] is connected to memory cell 150[1,1] and memory cell 150[1,2] as wiring WL, and wiring WL[2] is connected to memory cell 150[2,1] and memory cell 150[2,2] as wiring WL.

Figure 21B is a plan view showing a specific configuration example of the semiconductor device shown in Figure 21A. Figure 22 is a cross-sectional view taken along dashed line D1-D2 in Figure 21B. Note that in Figures 21B and 22, conductive layers 240a and 240b are collectively referred to as conductive layer 240. Furthermore, conductive layers 240a_1 and 240b_1 are collectively referred to as conductive layer 240_1. Furthermore, conductive layers 240a_2 and 240b_2 are collectively referred to as conductive layer 240_2.

As described above, the conductive layer 110 has a region that functions as a wiring PL. The conductive layer 260 has a region that functions as a wiring WL. The conductive layer 245 has a region that functions as a wiring BL. In Figures 21B and 22, the conductive layer 260 having a region that functions as a wiring WL[1] is shown as a conductive layer 260[1], and the conductive layer 260 having a region that functions as a wiring WL[2] is shown as a conductive layer 260[2]. In Figures 21B and 22, the conductive layer 245 having a region that functions as a wiring BL[1] is shown as a conductive layer 245[1], and the conductive layer 245 having a region that functions as a wiring BL[2] is shown as a conductive layer 245[2].

Figures 21B and 22 show an example in which conductive layer 245[1] and conductive layer 245[2] extend in the X direction. Figures 21B and 22 also show an example in which conductive layer 110, conductive layer 260[1], and conductive layer 260[2] extend in the Y direction.

As shown in Figures 21B and 22, a conductive layer 240 can be shared between two memory cells 150 adjacent in the X direction. For example, one conductive layer 240 can be shared between memory cell 150[1,1] and memory cell 150[1,2]. Also, one conductive layer 240 can be shared between memory cell 150[2,1] and memory cell 150[2,2]. Furthermore, multiple conductive layers 240 provided in the X direction can be connected to each other by a conductive layer 245 extending in the X direction. For example, conductive layer 245[1] can be shared between memory cell 150[1,1] and memory cell 150[1,2]. Also, conductive layer 245[2] can be shared between memory cell 150[2,1] and memory cell 150[2,2].

The conductive layer 260 extending in the Y direction can be shared among multiple memory cells 150 arranged in the Y direction. For example, the conductive layer 260[1] can be shared between memory cell 150[1,1] and memory cell 150[2,1], and the conductive layer 260[2] can be shared between memory cell 150[1,2] and memory cell 150[2,2].

Furthermore, as shown in Figures 21B and 22, the semiconductor layer 230 can be shared between multiple memory cells 150 adjacent in the X direction. Furthermore, as shown in Figure 21B, multiple semiconductor layers 230 can be provided in one groove portion 290.

A memory cell array can be formed by arranging memory cells 150 in a three-dimensional matrix.

The semiconductor device shown in FIG. 23 has n memory layers 160 (n is an integer of 2 or greater; in the example shown in FIG. 23, n is an integer of 3 or greater). Specifically, memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are further provided on memory layer 160[2]. Here, memory layer 160[n] is provided at the top. The number of memory cells 150 included in one memory layer 160 is not particularly limited, and two or more memory cells 150 can be included. For example, conductive layer 247 connects the memory cells 150 included in the n memory layers 160 to a sense amplifier (not shown) provided below memory layer 160[1]. In this way, stacking multiple memory cells 150 on top of each other can increase the storage capacity per unit area.

For example, the conductive layer 247 may function as a plug or wiring for connecting circuit elements, wiring, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistors, and diodes to the memory cell 150.

The conductive layer 247 is provided inside the opening 251 formed in the insulating layer 140, the insulating layer 180, the insulating layer 280a, the insulating layer 280b, the insulating layer 280c, the insulating layer 250, the insulating layer 283, the insulating layer 285, etc. Note that the conductive layer 247 can be made of a conductive material that can be used for the conductive layer 240a and the conductive layer 240b, etc.

Figure 23 shows an example in which the upper end of the ferroelectric layer 130 coincides or approximately coincides with the lower end of the conductive layer 120. In this case, the insulating layer 140, insulating layer 180, insulating layer 280a, insulating layer 280b, insulating layer 280c, insulating layer 250, insulating layer 283, insulating layer 285, etc. have areas that do not overlap with the ferroelectric layer 130. Therefore, openings 251 can be formed in these areas, eliminating the need to form openings 251 in the ferroelectric layer 130. This makes it easy to form openings 251 with a high aspect ratio.

As shown in Figure 23, by stacking multiple memory cells 150, cells can be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a 3D memory cell array can be constructed. This allows for a larger memory capacity per unit area.

Figure 24 is a cross-sectional view showing an example of the configuration of a semiconductor device, showing an example in which a transistor 300 is provided below a memory cell 150. The transistor 300 can be provided so as to have a region that overlaps with the memory cell 150. The transistor 300 can be provided in a driver circuit that has a function of driving the memory cell 150. The transistor 300 can be, for example, a transistor included in a sense amplifier.

By configuring the sense amplifier so that it overlaps the memory cell 150, for example, the bit line connecting the sense amplifier to the memory cell 150 can be shortened. This reduces the bit line capacitance, enabling the semiconductor device to operate at high speed.

The semiconductor device shown in FIG. 24 can correspond to the semiconductor device 900 described in embodiment 3. Specifically, the transistor 300 corresponds to the transistor included in the sense amplifier 927 in the semiconductor device 900. Furthermore, the memory cell 150 corresponds to the memory cell 950.

The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as source and drain regions. The transistor 300 may be either a p-channel or n-channel type. The substrate 311 preferably contains a silicon-based semiconductor, and more specifically, preferably contains single-crystal silicon.

Here, in the transistor 300 shown in Figure 24, the semiconductor region 313 (part of the substrate 311) where the channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that contacts the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

Note that the transistor 300 shown in Figure 24 is just an example, and the structure is not limited to this, and an appropriate transistor can be used depending on the circuit configuration or driving method.

A wiring layer containing an interlayer insulating film, wiring, plugs, etc. may be provided between each structure. Multiple wiring layers may be provided depending on the design. Here, the same reference numeral may be used to refer to multiple structures of a conductive layer that functions as a plug or wiring. In this specification, the wiring and the plug connecting to the wiring may be integrated. In other words, there are cases where a portion of the conductive layer functions as the wiring, and cases where a portion of the conductive layer functions as the plug.

For example, insulating layer 320, insulating layer 322, insulating layer 324, and insulating layer 326 are stacked in this order on transistor 300 as an interlayer insulating film. In addition, conductive layer 328 is embedded in insulating layer 320 and insulating layer 322, and conductive layer 330 is embedded in insulating layer 324 and insulating layer 326. Conductive layer 328 and conductive layer 330 function as plugs or wiring.

Furthermore, the insulating layer that functions as an interlayer insulating film may also function as a planarizing film that covers the underlying unevenness. For example, the upper surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve flatness.

A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in FIG. 24, insulating layer 350, insulating layer 352, and insulating layer 354 are stacked in this order. In addition, conductive layer 356 is formed on insulating layer 350, insulating layer 352, and insulating layer 354. Conductive layer 356 functions as a plug or wiring.

The insulating layers 352 and 354, which function as interlayer insulating films, can be the same insulating layers that can be used in the semiconductor device described above.

Conductive layers that function as plugs or wirings, such as conductive layer 328, conductive layer 330, and conductive layer 356, can be made of conductive materials that can be used for conductive layer 240a and conductive layer 240b. High-melting-point materials that are both heat-resistant and conductive, such as tungsten or molybdenum, are preferably used, and tungsten is preferred. Alternatively, they are preferably made of low-resistance conductive materials such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.

The conductive layers 240a and 240b of the transistor 200 are connected to the low-resistance region 314b, which functions as the source or drain region of the transistor 300, via the conductive layers 643, 645, 646, 356, 330, and 328.

Conductive layer 643 is embedded in insulating layer 285, insulating layer 283, insulating layer 250, insulating layer 280c, insulating layer 280b, insulating layer 280a, and insulating layer 180. Conductive layer 645 is embedded in insulating layer 180. Conductive layer 645 can be manufactured using the same material and process as conductive layer 110. Conductive layer 646 is embedded in insulating layer 649. The insulating layer 649 insulates the transistor 300 from the conductive layer 110.

<Hysteresis characteristics of ferroelectrics>
Ferroelectrics have hysteresis characteristics. FIG. 25 is a diagram showing an example of the hysteresis characteristics of a ferroelectric. The hysteresis characteristics can be measured using a ferroelectric capacitor. In FIG. 25, the horizontal axis represents the voltage (electric field) applied to the ferroelectric layer. This voltage is the potential difference between one electrode and the other electrode in the ferroelectric capacitor. The electric field strength can be found by dividing this potential difference by the thickness of the ferroelectric layer.

In Figure 25, the vertical axis represents the polarization of the ferroelectric. When the polarization is positive, it indicates that the positive charge in the ferroelectric layer is biased toward one electrode of the ferroelectric capacitor, and the negative charge is biased toward the other electrode of the ferroelectric capacitor. On the other hand, when the polarization is negative, it indicates that the negative charge in the ferroelectric layer is biased toward one electrode of the ferroelectric capacitor, and the positive charge is biased toward the other electrode of the ferroelectric capacitor.

Furthermore, the polarization shown on the vertical axis of Figure 25 can be considered positive when negative charges are biased toward one electrode of the ferroelectric capacitor and positive charges are biased toward the other electrode of the ferroelectric capacitor, or negative when positive charges are biased toward one electrode of the ferroelectric capacitor and negative charges are biased toward the other electrode of the ferroelectric capacitor.

As shown in Figure 25, the hysteresis characteristics of a ferroelectric material can be represented by curve 401 and curve 402. The voltages at the intersections of curve 401 and curve 402 are called the saturated polarization voltage +VSP (also called "+VSP") and the saturated polarization voltage -VSP (also called "-VSP"). +VSP and -VSP can be said to have opposite polarities.

After applying a voltage equal to or less than -VSP to the ferroelectric layer, if the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 401. On the other hand, after applying a voltage equal to or greater than +VSP to the ferroelectric layer, if the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 402. Note that +VSP may be referred to as the "positive saturation polarization voltage" or "first saturation polarization voltage." Furthermore, -VSP may be referred to as the "negative saturation polarization voltage" or "second saturation polarization voltage." The absolute values of the first saturation polarization voltage and the second saturation polarization voltage may be the same or different.

When the polarization of the ferroelectric layer changes according to curve 401, the voltage at which the polarization becomes 0 is called the coercive voltage +Vc. When the polarization of the ferroelectric layer changes according to curve 402, the voltage at which the polarization becomes 0 is called the coercive voltage -Vc. The values of +Vc and -Vc are between +VSP and -VSP. Note that +Vc may be called the "positive coercive voltage" or "first coercive voltage," and -Vc may be called the "negative coercive voltage" or "second coercive voltage." The absolute values of the first coercive voltage and the second coercive voltage may be the same or different.

Furthermore, the maximum value of polarization when no voltage is applied to the ferroelectric layer (when the voltage is 0V) is called "residual polarization +Pr" or "residual polarization Pr1," and the minimum value is called "residual polarization -Pr" or "residual polarization Pr2." Furthermore, the absolute value of the difference between remanent polarization +Pr and remanent polarization -Pr is called "residual polarization 2Pr." The larger the remanent polarization 2Pr, the greater the fluctuation range of the capacitance value of the ferroelectric capacitor due to polarization reversal. The larger the remanent polarization 2Pr, the more preferable it is.

This embodiment can be combined with other embodiments and examples as appropriate. Furthermore, in this specification, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

(Embodiment 2)
In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

Note that in this specification and the like, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). For example, examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be described below. Fig. 26A is a schematic diagram showing the carrier concentration dependence of the Hall mobility for silicon (Si) and indium oxide (InO _x ), and Fig. 26B is a schematic diagram showing the carrier concentration dependence of the Hall mobility for IGZO.

First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as indicated by the arrows in Figure 26B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as indicated by the arrows in Figure 26A (see Non-Patent Document 7). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties closer to silicon. Note that the characteristics of indium oxide shown in Figure 26A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 26A.

26A , the low carrier concentration range R1 has extremely high hole mobility, and can therefore be considered a carrier concentration range suitable for, for example, a transistor channel formation region. For example, in the case of indium oxide, range R1 is a range including a carrier concentration value of 1×10 ¹⁵ cm ⁻³ , for example, a range of 1×10 ¹⁴ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less. By sufficiently reducing the carrier concentration, it is expected that the hole mobility value can be increased to approximately 270 cm ² /(V·s).

In addition, in indium oxide, the region where the carrier concentration is in range R1 can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

On the other hand, the range R2 of high carrier concentration has low electrical resistance and can be said to be a range of carrier concentration suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. Range R2 is a range of carrier concentration values that includes 1×10 ²⁰ cm ⁻³ , for example, a range of 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. By sufficiently increasing the carrier concentration, it is expected that the resistivity can be reduced to 1×10 ⁻⁴ Ω·cm or less.

Note that in indium oxide, the region where the carrier concentration is in range R2 can contain elements that increase the carrier concentration. For example, it is preferable that the region contains elements that are common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. It is particularly preferable to use elements whose oxides have conductive or semiconductive properties.

In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be considered an oxide capable of valence electron control. Note that with IGZO, strain may form in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so strain does not need to be formed in the film as with IGZO. Minimizing strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in range R1 and range R2 shown in Figure 26A within an indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in silicon-based transistors is generally known. However, valence electron control in indium oxide-based transistors is a novel technological concept that would not normally be conceived.

By using the above technical concept, the transistor containing indium oxide in this specification has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) A high on-state current (in other words, high mobility). (2) A low off-state current. (3) Normally-off operation is possible. (4) High reliability. (5) A high cutoff frequency (fT). For example, the transistor containing indium oxide in this specification has high mobility, a low off-state current, and is normally-off operation. This transistor has high mobility and is different from a normally-on transistor.

Next, we will explain indium oxide films used in transistors. It is preferable that the indium oxide film be crystalline (i.e., have crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities that impede carrier flow (typically, insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. Using a single-crystal film can suppress carrier scattering at grain boundaries, resulting in a transistor with high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and as few crystal grain boundaries as possible. Note that in a transistor using a polycrystalline film of indium oxide, if there are no crystal grain boundaries in the channel formation region or no crystal grain boundaries are observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to use single-crystal indium oxide.

The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

Furthermore, in this specification, a semiconductor layer in which no crystal grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained in a single crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Furthermore, a semiconductor layer in which, within a single crystal grain in the channel formation region, the direction of the other crystal axis changes continuously around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

Note that the channel formation region refers to the region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, source electrode, and drain electrode.

The lower the impurity concentration of the indium oxide film in the channel formation region, the better. Impurities in the indium oxide film in the channel formation region can act as a scattering source for carriers, which can reduce field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Impurities in the indium oxide film include boron and silicon. The indium oxide film preferably has a concentration of each of these impurities of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, and other elements may be contained in the film formation gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above impurities.

Note that the indium oxide film in the channel formation region may contain elements that can become the same trivalent cations as indium, as long as the crystals maintain a cubic crystal structure (bixbyite type). Examples include elements in Group 13 of the periodic table, such as gallium and aluminum, and elements in Group 3 of the periodic table. These elements exist primarily as trivalent cations in oxides, allowing the carrier concentration of indium oxide to be maintained low.

By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm ² /(V·s) or more, preferably 100 cm ² /(V·s) or more, more preferably 150 cm ² /(V·s) or more, even more preferably 200 cm ² /(V·s) or more, and still more preferably 250 cm ² /(V·s) or more.

One of the features of an indium oxide film is its high oxygen permeability (diffusibility) compared to an IGZO film. As shown in FIG. 26C, oxygen (O) diffusing into an indium oxide film (denoted as _InOX ) passes through the indium oxide film and is released as oxygen molecules (O ₂ ). It may also react with hydrogen contained in the film and be released as water molecules (H ₂ O). Furthermore, if oxygen vacancies ( _VO ) exist in the film, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses into an indium oxide film, it can also be said that oxygen vacancies are more easily compensated for compared to an IGZO film.

As such, indium oxide films are easier to reduce oxygen vacancies in than IGZO films, so by applying such indium oxide films to transistors, it is possible to achieve transistors that exhibit extremely high reliability.

26C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and is released as hydrogen molecules (H ₂ ). Alternatively, hydrogen reacts with oxygen contained in the film and is released as water molecules.

Transistors using indium oxide films are accumulation-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is a constant value, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, using indium oxide, which has a small effective electron mass, in a transistor can increase the on-state current or field-effect mobility of the transistor.

Table 1 shows the effective masses of single-crystal indium oxide (here, In ₂ O ₃ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Furthermore, the effective mass of electrons in indium oxide is characterized by being almost independent of the crystal orientation. Therefore, by using crystalline indium oxide for a transistor, a transistor with high field-effect mobility and high frequency characteristics (also referred to as f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely low off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-state current per 1 μm of channel width can be 1 fA (1×10 ⁻¹⁵ A) or less or 1 aA (1×10 ⁻¹⁸ A) or less in an environment of 125° C., and 1 aA (1×10 ⁻¹⁸ A) or less or 1 zA (1×10 ⁻²¹ A) or less in an environment of room temperature (25° C.). Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

It is preferable to provide a seed layer so that it is in contact with at least a portion of the crystalline indium oxide film. For the seed layer, it is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, an indium oxide film) with respect to the crystals of the seed layer is calculated by Δa = (( _L1 - _L2 ) / _L2 ) × 100, where _L1 is the length or lattice constant of the unit lattice vector of the crystals of the formed film, and _L2 is the length or lattice constant of the unit lattice vector of the crystals of the seed layer.

The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the better, with 0 being most preferable. For example, Δa can be set to between -5% and 5%, preferably between -4% and 4%, more preferably between -3% and 3%, and even more preferably between -2% and 2%.

Here, the indium oxide crystals have a cubic crystal structure (bixbyite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystals with the cubic YSZ crystals is within the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

Note that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure can be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to [001] and the crystal orientation of the underside of the indium oxide film to [111], the requirements regarding the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or _trigonal crystals include a _wurtzite structure, _{a YbFe2O4} structure, _{a Yb2Fe3O7} structure, and modified structures thereof. An example of a crystal having _{a YbFe2O4} structure or _{a Yb2Fe3O7} structure is IGZO.

This embodiment can be combined with other embodiments and examples as appropriate. Furthermore, in this specification, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

(Embodiment 3)
In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described.

Figure 27 shows a block diagram illustrating an example configuration of a semiconductor device 900. The semiconductor device 900 shown in Figure 27 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Figure 27 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

For example, the memory cell 150 described in embodiment 1 can be applied to the memory cell 950.

The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

In the semiconductor device 900, each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal.

Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by control circuit 912.

The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

The row decoder 941 and column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying the row to be accessed, and the column decoder 942 is a circuit for specifying the column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell 950, reading data from the memory cell 950, and retaining the read data.

The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. The output circuit 926 also has the function of outputting Dout externally from the semiconductor device 900. The data output from the output circuit 926 is the signal RDA.

The PSW 931 has a function of controlling the supply of _VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of _VHM to the row driver 923. In this example, the high power supply potential of the semiconductor device 900 is _VDD , and the low power supply potential is GND (ground potential). _VHM is a high power supply potential used to set the word line to a high level and is higher than _VDD . The on/off of the PSW 931 is controlled by a signal PON1, and the on/off of the PSW 932 is controlled by a signal PON2. In FIG. 27, the number of power domains to which _VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch can be provided for each power domain.

The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in Figure 28A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in Figure 28B, the memory array 920 may be provided in multiple layers on top of the driver circuit 910.

Next, we will explain an example of a processing device that can be equipped with the above-mentioned semiconductor device.

Figure 29 shows a block diagram of the arithmetic unit 960. The arithmetic unit 960 shown in Figure 29 can be applied to a CPU, for example. The arithmetic unit 960 can also be applied to processors such as a GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), and NPU (Neural Processing Unit), which have a larger number (tens to hundreds) of processor cores capable of parallel processing than a CPU.

The arithmetic device 960 shown in FIG. 29 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 969 and the cache interface 969i may also be provided on separate chips.

Cache 969 is connected to main memory provided on a separate chip via cache interface 969i. Cache interface 969i has the function of supplying part of the data held in main memory to cache 969. Cache interface 969i also has the function of outputting part of the data held in cache 969 to ALU 962, register 966, etc. via bus interface 968.

As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have the function of supplying data held in the memory array 920 to the cache 969. In this case, it is also preferable that a drive circuit 910 be included as part of the cache interface 969i.

It is also possible to use only the memory array 920 as a cache without providing the cache 969.

The arithmetic device 960 shown in FIG. 29 is merely one example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 29 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The more cores there are, the more preferable it is, and for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more cores are preferable. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

Instructions input to the arithmetic unit 960 via the bus interface 968 are input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965.

The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals to control the operation of the ALU 962. Furthermore, while the arithmetic unit 960 is executing a program, the interrupt controller 964 determines and processes interrupt requests from external input/output devices, peripheral circuits, etc. based on their priority, mask status, etc. The register controller 967 generates the address of the register 966 and reads and writes to the register 966 depending on the state of the arithmetic unit 960.

The timing controller 965 also generates signals that control the timing of the operations of the ALU 962, ALU controller 962c, instruction decoder 963, interrupt controller 964, and register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

In the arithmetic unit 960 shown in FIG. 29, the register controller 967 selects the holding operation in the register 966 in accordance with instructions from the ALU 962. That is, it selects whether the memory cells in the register 966 will hold data using flip-flops or capacitors. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 966. If holding data in capacitors is selected, the data is rewritten to the capacitors, and the supply of power supply potential to the memory cells in the register 966 can be stopped.

The memory array 920 and the computing device 960 can be provided overlapping each other. Figures 30A and 30B show perspective views of a semiconductor device 970A. The semiconductor device 970A has a layer 930 on which a memory array is provided above the computing device 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The computing device 960 and each memory array have overlapping areas. To make the configuration of the semiconductor device 970A easier to understand, Figure 30B shows the computing device 960 and layer 930 separated.

By stacking the layer 930 having the memory array and the computing device 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

As a method for stacking the layer 930 having a memory array and the computing device 960, a method of stacking the layer 930 having a memory array directly on the computing device 960 (also called monolithic stacking) may be used, or a method of forming the computing device 960 and the layer 930 on different substrates, bonding the two substrates together, and connecting them using through-vias or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore not only can it reduce the chip size but also manufacturing costs.

Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, memory array 920L1 can be used as an L1 cache (also called a level 1 cache), memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 920L3 has the largest capacity and is accessed least frequently. Furthermore, memory array 920L1 has the smallest capacity and is accessed most frequently.

Note that when the cache 969 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in layer 930 can be used as a lower-level cache or main memory. Main memory has a larger capacity than the cache and is accessed less frequently.

Also, as shown in FIG. 30B, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

Note that while three memory arrays functioning as caches are shown here, the number may be one, two, or four or more.

When the memory array 920L1 is used as a cache, the drive circuit 910L1 may function as part of the cache interface 969i, or the drive circuit 910L1 may be configured to be connected to the cache interface 969i. Similarly, the drive circuit 910L2 and the drive circuit 910L3 may also function as part of the cache interface 969i, or may be configured to be connected to it.

Whether the memory array 920 functions as a cache or as main memory is determined by the control circuit 912 of each drive circuit 910. Based on a signal supplied from the arithmetic device 960, the control circuit 912 can cause some of the multiple memory cells 950 in the semiconductor device 900 to function as RAM.

The semiconductor device 900 can cause some of the multiple memory cells 950 to function as cache, and the other part to function as main memory. In other words, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.

Alternatively, a layer 930 having one memory array 920 may be provided over the computing device 960. Figure 31A shows a perspective view of the semiconductor device 970B.

In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for different functions. Figure 31A shows an example in which area L1 is used as an L1 cache, area L2 as an L2 cache, and area L3 as an L3 cache.

Furthermore, in semiconductor device 970B, the capacity of each of areas L1 to L3 can be changed depending on the situation. For example, if you want to increase the capacity of the L1 cache, you can achieve this by increasing the area of area L1. With this configuration, it is possible to improve the efficiency of calculation processing and increase processing speed.

Alternatively, multiple memory arrays may be stacked. Figure 31B shows a perspective view of semiconductor device 970C.

Semiconductor device 970C has a layer 930L1 having memory array 920L1 stacked on top of which is a layer 930L2 having memory array 920L2, and a layer 930L3 having memory array 920L3 stacked on top of that. Memory array 920L1, which is physically closest to the computing device 960, can be used as a higher-level cache, and memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory array can be increased, thereby further improving processing power.

This embodiment can be combined with other embodiments and examples as appropriate. Furthermore, in this specification, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

(Fourth embodiment)
In this embodiment, an example of the applicability of a semiconductor device of one embodiment of the present invention will be described.

Semiconductor devices such as computers use a variety of memory devices depending on the application. Figure 32 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices. In Figure 32, the conceptual diagram explaining the hierarchy of memory devices is represented by triangles, with memory devices located higher in the triangle requiring faster operating speeds, and memory devices located lower in the triangle requiring larger memory capacities and higher recording densities.

In Figure 32, from the top layer of the triangle, there are shown memory integrated as registers in the CPU, GPU, and NPU processing units, cache memory (sometimes simply referred to as cache, and typically L1, L2, and L3 caches), main memory such as DRAM, and storage memory such as 3D NAND and hard disks (also known as HDDs: hard disk drives).

Memory integrated as registers into arithmetic processing units such as CPUs, GPUs, and NPUs is used for temporary storage of calculation results, and is therefore frequently accessed by the arithmetic processing unit. Therefore, fast operating speeds are required rather than large storage capacities. Registers also have the function of storing setting information for the arithmetic processing unit.

Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the speed of accessing the data can be increased. Cache memory requires a smaller storage capacity than DRAM, but a faster operating speed than DRAM. Data rewritten in cache memory is duplicated and supplied to DRAM. Note that although only the L3 cache is shown in Figure 32, the cache memory is not limited to this. For example, a memory device using an oxide semiconductor according to one embodiment of the present invention can also be suitably used for a last level cache (LLC) or final level cache (FLC), which are located at the lowest level of the cache.

DRAM has the function of storing programs, data, etc. read from 3D NAND.

3D NAND has the ability to store data that requires long-term storage, various programs used in computing devices (for example, artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speeds.

Hard disks have large storage capacity and are non-volatile. Alternatively, solid-state drives (SSDs) can be used instead of hard disks.

A memory device (OS memory) using an oxide semiconductor according to one embodiment of the present invention can retain data for a long period of time. Therefore, it can be suitably used in the region of Target 1 shown in FIG. 32 . Note that, as indicated by the diagonal hatching in FIG. 32 , Target 1 also includes part of the cache (L1, L2, L3) and part of the 3D NAND. In other words, Target 1 includes the boundary region between the DRAM and the 3D NAND, and the boundary region between the DRAM and the cache (L1, L2, L3). Furthermore, the memory device using an oxide semiconductor according to one embodiment of the present invention has high operating speed and can therefore achieve excellent write and read operations. Therefore, it can be suitably used in the region of Target 2 shown in FIG. 32 .

For example, it is preferable to replace the DRAM shown in FIG. 32 with a memory device using an oxide semiconductor according to one embodiment of the present invention. Here, DRAM requires a refresh operation and is a destructive readout memory device, so it consumes more power than other memory devices. Therefore, a configuration without DRAM can reduce power consumption. This configuration can reduce power consumption to one-hundredth or one-thousandth or less of that of a configuration using DRAM. Therefore, by deploying information processing devices including supercomputers (also called high performance computers (HPCs)), computers, servers, and the like that employ such a configuration worldwide, global warming can be mitigated.

In this way, a memory device using an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs, to memories in the boundary area between DRAM and 3D NAND.

This embodiment can be combined with other embodiments and examples as appropriate. Furthermore, in this specification, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

Fifth Embodiment
In this embodiment, application examples of the semiconductor device of one embodiment of the present invention will be described.

A semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframe computers, space equipment, data centers (also referred to as DCs), and various electronic devices. By using a semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved in electronic components, mainframe computers, space equipment, data centers, and various electronic devices.

The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[Electronic Components]
FIG. 33A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 33A has a semiconductor device 981 inside a mold 984. FIG. 33A omits some details in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are electrically connected to electrode pads 986, and the electrode pads 986 are electrically connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and electrically connected on the printed circuit board 988 to complete the mounting substrate 989.

The semiconductor device 981 also has a drive circuit layer 982 and a memory layer 983. The memory layer 983 is configured by stacking multiple memory cell arrays. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, it is possible to achieve a so-called on-chip memory configuration, in which the memory is formed directly on the processor, for example. The on-chip memory configuration makes it possible to increase the operation speed of the interface between the processor and the memory.

Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also known as memory bandwidth).

Furthermore, it is preferable that the multiple memory cell arrays included in the memory layer 983 are formed using OS transistors and that the multiple memory cell arrays are monolithically stacked. By configuring the multiple memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to achieve a monolithic stack configuration than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stack configuration.

The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

Next, Figure 33B shows a perspective view of electronic component 990. Electronic component 990 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and multiple semiconductor devices 981 provided on interposer 991.

Electronic component 990 shows an example in which semiconductor device 981 is used as a high bandwidth memory (HBM). Furthermore, semiconductor device 994 can be used in integrated circuits such as a CPU, GPU, or FPGA (Field Programmable Gate Array).

The package substrate 992 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 991 can be, for example, a silicon interposer or a resin interposer.

The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and package substrate 992 are connected using these through electrodes. In addition, with silicon interposers, TSVs can also be used as through electrodes.

HBM requires the connection of many wires to achieve a wide memory bandwidth. For this reason, the interposer on which the HBM is mounted must have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is less likely. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. It is particularly preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, space is required to accommodate the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may become difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure may be used that combines a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

A heat sink (heat sink) may also be provided on top of the electronic component 990. When a heat sink is provided, it is preferable to align the height of the integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. Figure 33B shows an example in which the electrodes 993 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

Electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[Large computer]
Next, Fig. 34A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 34A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

The computer 5620 can have the configuration shown in the perspective view in Figure 34B, for example. In Figure 34B, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

PC card 5621 shown in Figure 34C is an example of a processing board equipped with a CPU, GPU, memory device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 34C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, please refer to the descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.

The connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. The connection terminal 5629 may conform to, for example, PCIe.

Connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to PC card 5621, inputting signals, etc. They can also be, for example, interfaces for outputting signals calculated by PC card 5621. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Also, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).

The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting these terminals into sockets (not shown) provided on the board 5622.

The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 can be connected to the board 5622 by soldering the terminals to wiring on the board 5622, for example, using a reflow soldering method. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, artificial intelligence learning and inference.

[Space equipment]
The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. In other words, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, mesosphere, and stratosphere.

Figure 34D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 34D also shows a planet 6804 in space.

Although not shown in Figure 34D, the secondary battery 6805 may be provided with a battery management system (also referred to as BMS) or a battery control circuit. Using an OS transistor in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in space.

In addition, outer space is an environment with radiation levels more than 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

When sunlight is irradiated onto the solar panel 6802, the power required for the satellite 6800 to operate is generated. However, for example, in situations where sunlight is not irradiated onto the solar panel, or where the amount of sunlight irradiating the solar panel is low, the amount of power generated is small. Therefore, there is a possibility that the power required for the satellite 6800 to operate will not be generated. In order to operate the satellite 6800 even in situations where the amount of power generated is low, it is recommended to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel is sometimes called a solar cell module.

Satellite 6800 can generate a signal. The signal is transmitted via antenna 6803, and can be received, for example, by a receiver located on the ground or by another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be determined. As described above, satellite 6800 can constitute a satellite positioning system.

The control device 6807 also has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

Furthermore, the artificial satellite 6800 can be configured to include a sensor. For example, by configuring the artificial satellite 6800 with a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground. Or, by configuring the artificial satellite 6800 with a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an Earth observation satellite.

Note that although an artificial satellite is used as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, a semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

As explained above, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance compared to Si transistors.

[Data Center]
The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage devices and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, the power required to store data can be reduced and the semiconductor device that stores data can be made smaller. This allows for the storage system to be made smaller, the power supply for storing data to be made smaller, and the cooling equipment to be made smaller. This allows for space savings in the data center.

Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows for reduced heat generation from the circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

Figure 34E shows a storage system that can be used in a data center. The storage system 7010 shown in Figure 34E has multiple servers 7001sb as hosts 7001. It also has multiple storage devices 7003md as storage 7003. The host 7001 and storage 7003 are shown connected via a storage area network 7004 and a storage control circuit 7002.

The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

Storage 7003 uses flash memory to reduce data access speed, i.e., the time required to store and output data, but this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the slow access speed of storage 7003, storage systems typically provide cache memory within the storage to reduce the time required to store and output data.

The aforementioned cache memory is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory within the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.

By using OS transistors as transistors for storing data in the cache memory and maintaining a potential corresponding to the data, the frequency of refreshes can be reduced, and power consumption can be lowered. Furthermore, by stacking the memory cell array, miniaturization is possible.

Note that power consumption can be reduced by applying the semiconductor device of one embodiment of the present invention to one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO ₂ ). Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming due to its low power consumption.

This embodiment can be combined with other embodiments and examples as appropriate. Furthermore, in this specification, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

In this example, Sample A and Sample B, each including a ferroelectric capacitor, Capacitor 100, were fabricated, and the results of cross-sectional observation are described. The results of endurance tests and evaluation of I-V characteristics for Sample A and Sample B are also described.

Sample A was fabricated by the method shown in Figures 13A to 20C of embodiment 1. First, as shown in Figures 13A to 13C, a tungsten film with a thickness of 20 nm was formed as the conductive layer 110 on a silicon substrate (not shown) by sputtering. The substrate temperature was set to 130°C.

Next, a 5 nm thick silicon nitride film was deposited as the insulating layer 180a using the ALD method. The substrate temperature was set to 400°C.

Next, a silicon oxide film with a thickness of 370 nm was deposited as insulating layer 180b by sputtering. The substrate temperature was set to 170°C. Oxygen gas and argon gas were used as the deposition gas, and the oxygen flow rate ratio in the deposition gas was set to 50%. Next, a planarization process was performed on insulating layer 180b by CMP, resulting in a thickness of 350 nm for insulating layer 180b.

Then, a 60 nm thick silicon nitride film was deposited as insulating layer 180c by sputtering. The substrate temperature was set to 200°C. Nitrogen gas and argon gas were used as the deposition gas, with the nitrogen flow rate ratio in the deposition gas set to 74%.

Next, an SOC film, an SOG film, and a resist film were formed in that order using a coating method. A resist pattern was then formed using photolithography, and the SOG film and SOC film were processed using the resist pattern.

Next, based on the resist pattern, dry etching was performed on insulating layer 180c, insulating layer 180b, and insulating layer 180a. This resulted in openings 190 with a design width of 60 nm being formed in insulating layer 180c, insulating layer 180b, and insulating layer 180a. The SOC film, SOG film, and resist film were then removed.

Next, a 5 nm-thick titanium nitride film was formed as the conductive film 115f by CVD. _TiCl4 gas at 50 sccm and _NH3 gas at 2700 sccm were used as the film formation gas. The substrate temperature was 400°C, and the film formation gas pressure was 667 Pa. After that, a 300 nm-thick resist film was applied as the photoresist 131p.

Next, as shown in Figures 14A to 14C, anisotropic etching was performed on the entire surface of the photoresist 131p using a dry etching process. This formed a resist mask 131. The dry etching process was performed using 200 sccm of oxygen gas as the etching gas. The substrate temperature was 40°C, the etching gas pressure was 3.00 Pa, and the bias power was 150 W. The dry etching process was performed until the top surface of the conductive film 115f was exposed, and was continued for an additional 5 seconds after exposure. In other words, over-etching was performed for 5 seconds, with the conductive film 115f as the end point.

15A to 15C, the conductive film 115f was subjected to dry etching using the resist mask 131. As a result, the conductive layer 115 was formed. The dry etching was performed using chlorine gas at 45 sccm, _CF4 gas at 55 sccm, and oxygen gas at 55 sccm as etching gas. The substrate temperature was 40° C., the etching gas pressure was 0.67 Pa, and the bias power was 50 W. The processing time was 15 seconds.

Next, as shown in FIGS. 16A to 16C, an ashing process was performed to remove the resist mask 131. Next, as shown in FIGS. 17A to 17C, a 300 nm-thick silicon oxide film was deposited by CVD as the insulating layer 133. The silicon oxide film was deposited using TEOS as the deposition gas. Specifically, a gas with a flow ratio of ozone gas to TEOS of 8:1 was used as the deposition gas. The substrate temperature was set to 450°C. Thereafter, as shown in FIGS. 18A to 18C, a wet etching process was performed to remove the insulating layer 133.

Next, as shown in Figures 19A to 19C, a hafnium zirconium oxide film with a thickness of 10 nm was deposited by the ALD method as the ferroelectric layer 130. The substrate temperature was set to 300°C.

Subsequently, a titanium nitride film having a thickness of 30 nm was formed as the conductive film 120f_1 by a CVD method. _TiCl4 gas (50 sccm) and _NH3 gas (2700 sccm) were used as the film formation gas. The substrate temperature was 400° C., and the film formation gas pressure was 667 Pa.

Subsequently, a tungsten film having a thickness of 50 nm was deposited as the conductive film 120f_2 by a CVD method. The deposition gases used were _WF6 gas (250 sccm), hydrogen gas (2200 sccm), argon gas (2000 sccm), and nitrogen gas (200 sccm). The substrate temperature was 400° C., and the deposition gas pressure was 10666 Pa.

Subsequently, a titanium nitride film with a thickness of 50 nm was formed on the conductive film 120f_2 by CVD. Then, the titanium nitride film on the conductive film 120f_2 and the conductive film 120f_2 were subjected to planarization treatment by CMP. As a result, the titanium nitride film on the conductive film 120f_2 was removed, and the thickness of the conductive film 120f_2 was reduced to 40 nm.

Next, an SOC film, an SOG film, and a resist film were formed in that order using a coating method. A resist pattern was then formed using photolithography, and the SOG film and SOC film were processed using the resist pattern.

Subsequently, based on the resist pattern, dry etching was performed on the conductive film 120f_2, the conductive film 120f_1, and the ferroelectric layer 130. As a result, as shown in FIGS. 20A to 20C, the conductive layer 120_2 and the conductive layer 120_1 were formed. As a result, the conductive layer 120 composed of the conductive layer 120_1 and the conductive layer 120_2 on the conductive layer 120_1 was formed.

The dry etching treatment for the conductive film 120f_2 was performed using 200 sccm of _BCl3 gas as the etching gas. The treatment time was 33 seconds. The etching gas pressure was 0.67 Pa, and the bias power was 50 W. The dry etching treatment for the conductive film 120f_1 was performed using 200 sccm of oxygen gas as the etching gas. The treatment time was 60 seconds. The etching gas pressure was 0.67 Pa, and the bias power was 50 W. The dry etching treatment for the ferroelectric layer 130 was performed using 200 sccm of oxygen gas as the etching gas. The treatment time was 15 seconds. The etching gas pressure was 12.0 Pa, and the bias power was 0 W. Here, in the dry etching treatment for the conductive film 120f_2, the conductive film 120f_1, and the ferroelectric layer 130, the substrate temperature was 40° C.

After forming conductive layer 120_2 and conductive layer 120_1, the SOC film, SOG film, and resist film were removed. In this way, capacitor 100 was formed.

Sample A was prepared in this way.

In the fabrication of sample B, the steps shown in Figures 13A to 16C were first performed, followed by the steps shown in Figures 19A to 20C. The conditions for each step were the same as for sample A. In other words, sample B is a sample obtained by omitting the steps of forming and removing insulating layer 133 from the fabrication process of sample A.

Figure 35A is a cross-sectional scanning transmission electron microscope (STEM) image of sample A. In Figure 35, silicon substrate 111 is shown as the silicon substrate. Figure 35B is an image of region R shown in Figure 35A at a higher overall magnification. The cross-sectional STEM image was taken using a Hitachi High-Technologies Corporation HD-2700 scanning transmission electron microscope at an acceleration voltage of 200 kV.

As shown in Figures 35A and 35B, it was confirmed that in sample A, a capacitor 100 having a conductive layer 115, a ferroelectric layer 130, and a conductive layer 120 was formed. It was also confirmed that the capacitor 100 was formed so that the height of the upper end surface 103 of the conductive layer 115 from the upper surface of the silicon substrate 111 was lower than the height of the upper surface 105 of the insulating layer 180c from the upper surface of the silicon substrate 111. It was also confirmed that a conductive layer 120_1 was formed to fill the opening 190.

Figures 36A and 36B show input voltage waveforms in a rewrite endurance test. In Figures 36A and 36B, the vertical axis represents voltage V, and the horizontal axis represents time t. Voltage V represents the potential difference between conductive layer 115 and conductive layer 120.

In the rewrite endurance test, first, one cycle was defined as the application of one period of the trapezoidal wave shown in Figure 36A, and this trapezoidal wave was repeatedly applied until the specified number of cycles was reached. Next, the P-V characteristics were evaluated every specified number of cycles using the triangular wave double pulse method shown in Figure 36B. This resulted in obtaining the remanent polarization 2Pr. The frequency of the applied trapezoidal wave was 100 kHz, and the voltage was ±2.5 V. Note that in Figure 36A, a positive trapezoidal wave is indicated by "P" and a negative trapezoidal wave is indicated by "N".

In the triangular wave double pulse technique shown in Figure 36B, two positive triangular wave pulses are applied, followed by two negative triangular wave pulses, and the response charge is measured. The applied triangular wave has a frequency of 1 kHz and a voltage ranging from -2.5 V to +2.5 V. As shown in Figure 36B, a negative triangular wave pulse (poling) is applied before the above-mentioned positive triangular wave pulse is applied. In this specification, the triangular wave double pulse technique is sometimes referred to as the Triangle-PUND (Positive-up-negative-down) technique. Note that in Figure 36B, the two positive triangular wave pulses are indicated by "P" and "U", respectively. Also, in Figure 36B, the two negative triangular wave pulses are indicated by "N" and "D", respectively.

37A is a diagram showing the results of the rewrite endurance test for each of Sample A and Sample B. In Fig. 37A, the vertical axis represents the remanent polarization 2Pr [μC/cm ² ], and the horizontal axis represents the number of cycles [times].

37A , in sample A, no dielectric breakdown occurred even when the number of cycles reached 1×10 ^10. On the other hand, in sample B, dielectric breakdown occurred when the number of cycles reached 1×10 ^8. This suggests that the formation of insulating layer 133 oxidized conductive layer 115, and therefore absorption of oxygen contained in ferroelectric layer 130 by conductive layer 115 was more suppressed than in sample B.

Figure 37B shows the evaluation results of the I-V characteristics of Sample A and Sample B. In Figure 37B, the vertical axis represents current I [A], and the horizontal axis represents voltage V [V]. Here, current I represents the current that passes through ferroelectric layer 130 and flows between conductive layer 115 and conductive layer 120. Furthermore, voltage V represents the potential difference between conductive layer 115 and conductive layer 120, as described above.

As shown in Figure 37B, in sample A, when the voltage V was 1.4 V or more and 5.5 V or less, the magnitude of the current I was smaller than that of sample B when the voltage V was the same. Therefore, it was confirmed that sample A had a higher withstand voltage than sample B. This suggests that, as mentioned above, sample A was able to suppress the absorption of oxygen contained in the ferroelectric layer 130 into the conductive layer 115 more effectively than sample B.

In this example, samples C1, C2, C3, C4, and C5 were fabricated, each including a capacitor 100 that is a ferroelectric capacitor, and the results of a rewrite endurance test will be described.

Samples C1 to C5 were fabricated by the method shown in Figures 13A to 20C of embodiment 1. First, as shown in Figures 13A to 13C, a 20-nm-thick tungsten film was formed as the conductive layer 110 on a silicon substrate (not shown) by sputtering. The substrate temperature was set to 130°C.

Next, a 5 nm thick silicon nitride film was deposited as the insulating layer 180a using the ALD method. The substrate temperature was set to 400°C.

Next, a silicon oxide film with a thickness of 370 nm was deposited as insulating layer 180b by sputtering. The substrate temperature was set to 170°C. Oxygen gas and argon gas were used as the deposition gas, and the oxygen flow rate ratio in the deposition gas was set to 50%. Next, a planarization process was performed on insulating layer 180b by CMP, resulting in a thickness of 350 nm for insulating layer 180b.

Then, a 60 nm thick silicon nitride film was deposited as insulating layer 180c by sputtering. The substrate temperature was set to 200°C. Nitrogen gas and argon gas were used as the deposition gas, with the nitrogen flow rate ratio in the deposition gas set to 74%.

Next, an SOC film, an SOG film, and a resist film were formed in that order using a coating method. A resist pattern was then formed using photolithography, and the SOG film and SOC film were processed using the resist pattern.

Next, based on the resist pattern, dry etching was performed on insulating layer 180c, insulating layer 180b, and insulating layer 180a. This resulted in openings 190 with a design width of 60 nm being formed in insulating layer 180c, insulating layer 180b, and insulating layer 180a. The SOC film, SOG film, and resist film were then removed.

Next, a 5 nm-thick titanium nitride film was formed as the conductive film 115f by CVD. _TiCl4 gas at 50 sccm and _NH3 gas at 2700 sccm were used as the film formation gas. The substrate temperature was 400°C, and the film formation gas pressure was 667 Pa. After that, a 300 nm-thick resist film was applied as the photoresist 131p.

Next, as shown in Figures 14A to 14C, anisotropic etching was performed on the entire surface of the photoresist 131p using a dry etching process. This formed a resist mask 131. The dry etching process was performed using 200 sccm of oxygen gas as the etching gas. The substrate temperature was 40°C, the etching gas pressure was 3.00 Pa, and the bias power was 0 W. The dry etching process was performed until the top surface of the conductive film 115f was exposed, and was continued for an additional 5 seconds after exposure. In other words, over-etching was performed for 5 seconds, with the conductive film 115f as the end point.

15A to 15C, the conductive film 115f was subjected to dry etching using the resist mask 131. As a result, the conductive layer 115 was formed. The dry etching was performed using chlorine gas at 45 sccm, _CF4 gas at 55 sccm, and oxygen gas at 55 sccm as etching gas. The substrate temperature was 40° C., the etching gas pressure was 0.67 Pa, and the bias power was 50 W. The processing time was 15 seconds.

Next, as shown in Figures 16A to 16C, the resist mask 131 was removed. Next, as shown in Figures 17A to 17C, a 300 nm thick silicon oxide film was deposited by CVD as the insulating layer 133. The silicon oxide film was deposited using TEOS as the deposition gas. Specifically, a gas with a flow ratio of ozone gas to TEOS of 8:1 was used as the deposition gas. The substrate temperature was set to 350°C. After that, as shown in Figures 18A to 18C, a wet etching process was performed to remove the insulating layer 133.

19A to 19C, a hafnium zirconium oxide film having a thickness of 10 nm was formed as the ferroelectric layer 130 by the ALD method. _HfCl4 and _ZrCl4 were used as precursors. Water was used as an oxidizing agent. The substrate temperature was set to 300°C.

Subsequently, a titanium nitride film having a thickness of 30 nm was formed as the conductive film 120f_1 by a CVD method. _TiCl4 gas (50 sccm) and _NH3 gas (2700 sccm) were used as the film formation gas. The substrate temperature was 400° C., and the film formation gas pressure was 667 Pa.

Subsequently, a tungsten film having a thickness of 50 nm was deposited as the conductive film 120f_2 by a CVD method. The deposition gases used were _WF6 gas (250 sccm), hydrogen gas (2200 sccm), argon gas (2000 sccm), and nitrogen gas (200 sccm). The substrate temperature was 400° C., and the deposition gas pressure was 10666 Pa.

Subsequently, a titanium nitride film with a thickness of 50 nm was formed on the conductive film 120f_2 by CVD. Then, the titanium nitride film on the conductive film 120f_2 and the conductive film 120f_2 were subjected to planarization treatment by CMP. As a result, the titanium nitride film on the conductive film 120f_2 was removed, and the thickness of the conductive film 120f_2 was reduced to 40 nm.

Next, an SOC film, an SOG film, and a resist film were formed in that order using a coating method. A resist pattern was then formed using photolithography, and the SOG film and SOC film were processed using the resist pattern.

Subsequently, based on the resist pattern, dry etching was performed on the conductive film 120f_2, the conductive film 120f_1, and the ferroelectric layer 130. As a result, as shown in FIGS. 20A to 20C, the conductive layer 120_2 and the conductive layer 120_1 were formed. As a result, the conductive layer 120 composed of the conductive layer 120_1 and the conductive layer 120_2 on the conductive layer 120_1 was formed.

The dry etching treatment for the conductive film 120f_2 was performed using 200 sccm of _BCl3 gas as the etching gas. The treatment time was 33 seconds. The etching gas pressure was 0.67 Pa, and the bias power was 50 W. The dry etching treatment for the conductive film 120f_1 was performed using 200 sccm of oxygen gas as the etching gas. The treatment time was 60 seconds. The etching gas pressure was 0.67 Pa, and the bias power was 50 W. The dry etching treatment for the ferroelectric layer 130 was performed using 200 sccm of oxygen gas as the etching gas. The treatment time was 15 seconds. The etching gas pressure was 12.0 Pa, and the bias power was 0 W. Here, in the dry etching treatment for the conductive film 120f_2, the conductive film 120f_1, and the ferroelectric layer 130, the substrate temperature was 40° C.

After forming conductive layer 120_2 and conductive layer 120_1, the SOC film, SOG film, and resist film were removed. In this way, capacitor 100 was formed.

Subsequently, heat treatment was performed at 400° C. under a vacuum in which the internal pressure was reduced to approximately 1.5×10 ⁻⁵ Pa. The heat treatment times were 2 minutes, 5 minutes, 10 minutes, 30 minutes, and 60 minutes for Samples C1, C2, C3, C4, and C5, respectively.

Samples C1 to C5 were prepared in this manner.

38 is a diagram showing the results of the rewrite endurance test for samples C1 to C5, in which the vertical axis represents the remanent polarization 2Pr [μC/cm ² ] and the horizontal axis represents the number of cycles [times].

As shown in Figure 38, no dielectric breakdown occurred in any of Samples C1 to C5, even when the number of cycles was 1 x ^108. Furthermore, at least when the number of cycles was 1 x ¹⁰⁵ or less, the remanent polarization 2Pr was largest in Samples C5, C4, C3, C2, and C1. Therefore, the longer the heat treatment time after forming the capacitor 100, the larger the remanent polarization 2Pr. In particular, by setting the heat treatment time to 60 minutes, the remanent polarization 2Pr increased significantly. From the above, it was confirmed that the heat treatment time after forming the capacitor 100 is preferably longer than 30 minutes.

This is thought to be because hydrogen originating from water used as an oxidizing agent is mixed into the ferroelectric layer 130 during deposition of the ferroelectric layer 130, and this hydrogen is then released by the heat treatment.

100: Capacitor, 101: Region, 102: Region, 103: End surface, 105: Top surface, 110: Conductive layer, 115: Conductive layer, 115f: Conductive film, 115ox: Oxide region, 116: Insulating layer, 120: Conductive layer, 120_1: Conductive layer, 120_2: Conductive layer, 120_3: Conductive layer, 120f: Conductive film, 120f_1: Conductive film, 120f_2: Conductive film, 130: Ferroelectric layer, 131: Resist mask, 131p: Photoresist, 133: Insulating layer, 140: Insulating layer, 150[1,1]: Metal memory cell, 150[1,2]: memory cell, 150[2,1]: memory cell, 150[2,2]: memory cell, 150: memory cell, 160[1]: memory layer, 160[2]: memory layer, 160[n]: memory layer, 160: memory layer, 180: insulating layer, 180a: insulating layer, 180b: insulating layer, 180c: insulating layer, 190: opening, 200: transistor, 230: semiconductor layer, 240: conductive layer, 240_1: conductive layer, 240_2: conductive layer, 240a: conductive layer, 240a_1 : Conductive layer, 240a_2: Conductive layer, 240b: Conductive layer, 240b_1: Conductive layer, 240b_2: Conductive layer, 244: Conductive layer, 244a: Conductive layer, 244b: Conductive layer, 245[1]: Conductive layer, 245[2]: Conductive layer, 245: Conductive layer, 247: Conductive layer, 250: Insulating layer, 251: Opening, 260[1]: Conductive layer, 260[2]: Conductive layer, 260: Conductive layer, 260_1: Conductive layer, 260_2: Conductive layer, 270: Opening, 270a: Opening, 270b: Opening, 280: Insulating layer, 280a: insulating layer, 280b: insulating layer, 280c: insulating layer, 283: insulating layer, 285: insulating layer, 290: groove portion, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 350: insulating layer, 352: insulating layer, 354: insulating layer, 356: conductive layer, 401: curve, 402: curve, 6 43: conductive layer, 645: conductive layer, 646: conductive layer, 649: insulating layer, 900: semiconductor device, 910: driver circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 960: operation Device, 961: substrate, 962: ALU, 962c: ALU controller, 963: instruction decoder, 964: interrupt controller, 965: timing controller, 966: register, 967: register controller, 968: bus interface, 969: cache, 969i: cache interface, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 980: electronic component, 981: semiconductor device, 982: drive circuit path layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989: mounting board, 990: electronic component, 991: interposer, 992: package board, 993: electrode, 994: semiconductor device, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: Semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7004: storage area network, 7010: storage system

Claims (13)

a substrate, a first insulating layer, a first conductive layer, a second conductive layer, and a ferroelectric layer;
the first insulating layer, the first conductive layer, the second conductive layer, and the ferroelectric layer are provided on the substrate;
the first insulating layer has an opening;
the first conductive layer has a region along a side surface of the opening of the first insulating layer,
an upper end surface of the first conductive layer is lower in height from the substrate than an upper surface of the first insulating layer;
the ferroelectric layer has a region in contact with the first conductive layer in the opening,
the second conductive layer has a region facing the first conductive layer with the ferroelectric layer interposed therebetween in the opening;
the first conductive layer has an oxide region;
the oxide region includes a region in contact with the ferroelectric layer,
The ferroelectric layer contains oxygen. In claim 1,
The oxide region includes an oxide of an element contained in the first conductive layer. In claim 1,
A semiconductor device in which the angle of the top surface of the first conductive layer with respect to the top surface of the substrate is greater than 0°. In claim 1,
the second conductive layer includes a first layer and a second layer on the first layer;
the first layer is provided to fill the opening,
A semiconductor device in which the thermal expansion coefficient of the first layer is greater than the thermal expansion coefficient of the second layer. In claim 4,
the first layer comprises titanium nitride;
The semiconductor device wherein the second layer comprises tungsten. In any one of claims 1 to 5,
a second insulating layer, a third insulating layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;
the second insulating layer is located on the second conductive layer and on the first insulating layer;
the third conductive layer and the fourth conductive layer are located on the second insulating layer;
the second insulating layer has a groove portion that overlaps a region between the third conductive layer and the fourth conductive layer and has a region that reaches the second conductive layer;
the semiconductor layer has a region in contact with the second conductive layer, a region in contact with the third conductive layer, a region in contact with the fourth conductive layer, and a region along a part of a side surface of the second insulating layer in the groove portion;
the third insulating layer is provided on the semiconductor layer so as to have a region located inside the groove;
The fifth conductive layer has a region inside the groove that faces the semiconductor layer with the third insulating layer sandwiched therebetween. In claim 6,
a fourth insulating layer and a sixth conductive layer;
the fourth insulating layer is located on the third to fifth conductive layers;
the sixth conductive layer is located on the fourth insulating layer;
The sixth conductive layer is electrically connected to the third conductive layer and the fourth conductive layer. In claim 7,
the groove and the fifth conductive layer extend in a first direction;
the sixth conductive layer extends in a second direction;
The second direction is perpendicular to the first direction. In claim 6,
The semiconductor device, wherein the semiconductor layer contains indium. forming a first insulating layer on a substrate;
forming an opening in the first insulating layer;
forming a conductive film so as to cover the opening;
A photoresist is applied onto the conductive film;
anisotropically etching the photoresist to form a resist mask in the opening;
forming a first conductive layer along a side surface of the opening of the first insulating layer by processing the conductive film;
removing the resist mask;
performing an oxidation treatment on the first conductive layer to form an oxide region in the first conductive layer;
forming a ferroelectric layer containing oxygen so as to have a region in contact with the oxide region;
forming a second conductive layer on the ferroelectric layer so as to have a region located in the opening;
A method for manufacturing a semiconductor device, wherein the first conductive layer is formed so that a height of an upper surface of the first conductive layer from the substrate is lower than a height of an upper surface of the first insulating layer from the substrate. In claim 10,
In the oxidation treatment, a second insulating layer containing oxygen is formed so as to have a region in contact with the first conductive layer, and then the second insulating layer is removed. In claim 10,
forming a first layer filling the opening and a second layer on the first layer as the second conductive layer;
A method for manufacturing a semiconductor device, wherein the first layer has a larger thermal expansion coefficient than the second layer. In claim 12,
The first layer is formed to include titanium nitride;
The second layer is formed to contain tungsten.