WO2025181637A1 - Semiconductor device - Google Patents

Abstract

Provided is a novel semiconductor device. A vertical transistor is provided so as to overlap a capacitive element. The vertical transistor is provided so as to overlap an opening penetrating an insulating layer. A semiconductor layer of the vertical transistor includes a channel formation region extending along a side surface of the insulating layer in the opening. In a plan view, the length of the opening in a first direction is different from the length of the opening in a second direction orthogonal to the first direction.

Description

Semiconductor Devices

One aspect of the present invention relates to a semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. Examples of technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input/output devices, and driving methods thereof or manufacturing methods thereof.

In recent years, development of semiconductor devices such as LSIs, CPUs, and memory (storage devices) has progressed. These semiconductor devices are used in a variety of electronic devices, including computers and personal digital assistants. Furthermore, various memory storage methods have been developed to suit different applications, such as temporary storage during processing and long-term data storage. Typical memory storage methods include DRAM, SRAM, and flash memory.

Furthermore, as the amount of data handled increases, there is a demand for memory devices with larger storage capacities. Patent Document 1 and Non-Patent Document 1 disclose memory cells formed by stacking transistors. In addition, there is a demand for memory devices with improved data write and read speeds.

International Publication No. 2021/053473

M. Oota et. al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

An object of one embodiment of the present invention is to provide a storage device with a large storage capacity. Alternatively, an object is to provide a storage device with a small occupation area. Alternatively, an object is to provide a storage device with high storage density. Alternatively, an object is to provide a storage device with high operating speed. Alternatively, an object is to provide a storage device with high reliability. Alternatively, an object is to provide a storage device with low power consumption. Alternatively, an object is to provide a novel storage device.

Note that the description of the above problems does not preclude the existence of other problems. Those skilled in the art would naturally find these other problems from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that one aspect of the present invention does not necessarily need to solve all of these problems (the above problems and other problems).

(1) One aspect of the present invention is a semiconductor device having a first capacitance element and a first transistor, comprising: a first insulating layer provided on a first conductive layer; a first opening penetrating the first insulating layer and reaching the first conductive layer; a second conductive layer having a region overlapping the first conductive layer and a region overlapping a side surface of the first insulating layer in the first opening; a second insulating layer provided on the second conductive layer; a third conductive layer having a region overlapping the second conductive layer via a portion of the second insulating layer and a region overlapping a side surface of the first insulating layer via another portion of the second insulating layer; a third insulating layer provided on the third conductive layer; The semiconductor device includes a fourth conductive layer provided on the edge layer, a second opening that penetrates the third insulating layer and reaches the third conductive layer, a semiconductor layer having a region electrically connected to the third conductive layer, a region electrically connected to the fourth conductive layer, and a channel formation region along the side of the third insulating layer in the second opening, a fourth insulating layer provided on the semiconductor layer, and a fifth conductive layer having a region that overlaps with the channel formation region of the transistor via a portion of the fourth insulating layer, and the first opening and the second opening have different lengths in a first direction and a second direction perpendicular to the first direction when viewed in plan.

Furthermore, in (1), for example, the second conductive layer functions as one electrode of the first capacitance element, the third conductive layer functions as the other electrode of the first capacitance element, the third conductive layer functions as one of the source electrode or drain electrode of the first transistor, and the fourth conductive layer functions as the other of the source electrode or drain electrode of the first transistor.

Furthermore, in (1), it is preferable that the length in the second direction is between two and five times the length in the first direction. It is preferable that the first capacitive element and the first transistor have regions that overlap each other in a planar view.

(2) Another aspect of the present invention is a semiconductor device having a first capacitive element, a first transistor, and a second transistor, the semiconductor device including: a first insulating layer provided on the first conductive layer; a second conductive layer having a region overlapping with the first conductive layer and a region overlapping with a side surface of the first insulating layer; a second insulating layer provided on the second conductive layer; a third conductive layer having a region overlapping with the second conductive layer via a portion of the second insulating layer; a third insulating layer provided on the third conductive layer; a fourth conductive layer provided on the third insulating layer; a semiconductor layer having a region electrically connected to the third conductive layer, a region electrically connected to the fourth conductive layer, a channel formation region of the first transistor, and a channel formation region of the second transistor; a fourth insulating layer provided on the semiconductor layer; and a fifth conductive layer having a region overlapping with the channel formation region of the first transistor via a portion of the fourth insulating layer and a channel formation region of the second transistor via another portion of the fourth insulating layer.

Furthermore, in (2), for example, the second conductive layer functions as one electrode of the first capacitance element, the third conductive layer functions as the other electrode of the first capacitance element, the third conductive layer functions as one of the source electrodes or drain electrodes of each of the first transistor and the second transistor, and the fourth conductive layer functions as the other of the source electrodes or drain electrodes of each of the first transistor and the second transistor.

Furthermore, in (2), it is preferable that the first capacitive element has a first region that overlaps with the first transistor in a planar view, and a second region that overlaps with the second transistor in a planar view.

Furthermore, in (1) or (2), it is preferable that the semiconductor layer contains an oxide semiconductor.

According to one aspect of the present invention, it is possible to provide a storage device with a large storage capacity. Or, it is possible to provide a storage device with a small footprint. Or, it is possible to provide a storage device with a high storage density. Or, it is possible to provide a storage device with a high operating speed. Or, it is possible to provide a storage device with high reliability. Or, it is possible to provide a storage device with low power consumption. Or, it is possible to provide a novel storage device.

Note that the description of the above effects does not preclude the existence of other effects. Those skilled in the art would naturally find these other effects from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above effects and other effects).

Fig. 1A is a plan view showing an example of a semiconductor device, Fig. 1B is a perspective view showing an example of a semiconductor device, Fig. 1C and Fig. 1D are cross-sectional views showing an example of a semiconductor device, and Fig. 1E is an equivalent circuit diagram of the semiconductor device.
Fig. 2A is a plan view showing an example of a semiconductor device, Fig. 2B is a perspective view showing an example of a semiconductor device, Fig. 2C and Fig. 2D are cross-sectional views showing an example of a semiconductor device, and Fig. 2E is an equivalent circuit diagram of the semiconductor device.
Fig. 3A is a plan view showing an example of a semiconductor device, Fig. 3B is a perspective view showing an example of a semiconductor device, Fig. 3C and Fig. 3D are cross-sectional views showing an example of a semiconductor device, and Fig. 3E is an equivalent circuit diagram of the semiconductor device.
Fig. 4A is a plan view showing an example of a semiconductor device, Fig. 4B is a perspective view showing an example of a semiconductor device, Fig. 4C and Fig. 4D are cross-sectional views showing an example of a semiconductor device, and Fig. 4E is an equivalent circuit diagram of the semiconductor device.
5A1, 5B1, and 5C1 are plan views showing an example of a semiconductor device, and FIGS. 5A2, 5B2, and 5C2 are perspective views showing an example of a semiconductor device.
6A and 6B are plan and cross-sectional views illustrating an example of a semiconductor device.
7A and 7B are cross-sectional views showing an example of a semiconductor device.
8A and 8B are plan and cross-sectional views illustrating an example of a semiconductor device.
9A and 9B are cross-sectional views showing an example of a semiconductor device.
10A to 10F are diagrams showing examples of the planar shape of the opening.
FIG. 11 is a block diagram illustrating an example of the configuration of a semiconductor device.
12A and 12B are diagrams showing configuration examples of memory cells.
13A and 13B are diagrams showing configuration examples of memory cells.
14A to 14G are diagrams illustrating examples of the circuit configuration of a memory cell.
15A and 15B are perspective views illustrating a configuration example of a semiconductor device.
FIG. 16 is a block diagram illustrating the CPU.
17A and 17B are perspective views of a semiconductor device.
18A and 18B are perspective views of a semiconductor device.
FIG. 19 is a conceptual diagram illustrating the hierarchy of a storage device.
20A and 20B are diagrams showing configuration examples of electronic components.
21A to 21C are diagrams showing examples of the configuration of a mainframe computer.
Fig. 22A is a diagram illustrating an example of the configuration of a space equipment, and Fig. 22B is a diagram illustrating an example of the configuration of a storage system.

Embodiments will be described below with reference to the drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

In this specification, a semiconductor device is a device that utilizes semiconductor properties, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components that house chips in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

In the drawings and other information pertaining to this specification, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the sizes or aspect ratios are not necessarily limited. Note that the drawings are schematic illustrations of ideal examples, and the shapes or values shown in the drawings are not limited.

In the configuration of the invention of the embodiments, the same parts or parts with similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in plan views, perspective views, etc.

In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components or the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the relative positions of components with reference to the drawings. Furthermore, the relative positions of components will change as appropriate depending on the direction in which each configuration is depicted. Therefore, terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require electrode B to be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

In this specification, terms such as "overlap" do not limit the state of the stacking order of components. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A.

In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer." Or, depending on the situation or circumstances, terms such as "film" and "layer" can be replaced with other terms without using them. For example, the term "conductive layer" or "conductive film" can be changed to the term "conductor." Or, the term "conductor" can be changed to the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" can be changed to the term "insulator." Or, the term "insulator" can be changed to the term "insulating layer" or "insulating film."

In this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are formed integrally. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" and "conductive layer" depending on the circumstances.

In this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to "signal line." For example, the term "wiring" may be changed to "power line." The reverse is also true; terms such as "signal line" and "power line" may be changed to "wiring." A term such as "power line" may be changed to "signal line." The reverse is also true; terms such as "signal line" may be changed to "power line." The term "potential" applied to wiring may be changed to "signal" depending on the circumstances. The reverse is also true; terms such as "signal" may be changed to "potential."

In this specification, "source" refers to a source region, source electrode, or source wiring. A source region refers to one of two regions in a semiconductor layer that are adjacent to a channel formation region. A source electrode refers to a conductive layer that includes a portion connected to the source region.

In this specification, "drain" refers to a drain region, drain electrode, or drain wiring. A drain region refers to the other of the two regions in a semiconductor layer that are adjacent to a channel formation region. A drain electrode refers to a conductive layer that includes a portion connected to the drain region.

In this specification, "gate" refers to a gate electrode or gate wiring. A gate electrode is an electrode that overlaps with a semiconductor layer of a transistor and has the function of controlling the resistance between the source and drain of the transistor depending on the voltage supplied to it.

In this specification, one of the source or drain of a transistor may be referred to as the "first terminal of the transistor," and the other of the source or drain of the transistor may be referred to as the "second terminal of the transistor."

In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -15° or more and 15° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and elsewhere, unless otherwise specified, voltage and potential can be used interchangeably.

Furthermore, in this specification, high power supply potential VDD (hereinafter simply referred to as "VDD") refers to a power supply potential that is higher than low power supply potential VSS. Furthermore, low power supply potential VSS (hereinafter simply referred to as "VSS") refers to a power supply potential that is lower than high power supply potential VDD. Furthermore, ground potential GND (hereinafter simply referred to as "GND") can also be used as VDD or VSS. For example, if VDD is GND, VSS is a lower potential than GND, and if VSS is GND, VDD is a higher potential than GND.

In this specification, the "on state" of a transistor means that the source and drain of the transistor are in a conductive state (a state in which electricity can pass through). Furthermore, the "off state" of a transistor means that the source and drain of the transistor are in a non-conductive state (a state that can be considered to be electrically cut off).

Furthermore, in this specification, "on-state current" refers to the current that flows between the source and drain when a transistor is in the on state. Furthermore, "off-state current" refers to the current that flows between the source and drain when a transistor is in the off state.

In this specification, potential H is a potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor") and turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). Potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, potential H is a potential higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS. Unless otherwise specified, the transistors shown in this specification are enhancement-type (normally-off) n-type transistors.

Furthermore, in drawings and the like, to clearly indicate the potential of wiring, electrodes, etc., an "H" indicating a high potential or an "L" indicating a low potential may be written next to the wiring, electrode, etc. Furthermore, wiring, electrodes, etc. where a potential change has occurred may be marked with a box containing "H" or "L." Furthermore, when a transistor is in an off state, an "x" symbol may be written over the transistor. Furthermore, an arrow may be added to indicate the direction of current flow.

In this specification, when referring to counting values and measurement values, terms such as "same," "equal," or "uniform" (including synonyms thereof) are used, unless otherwise specified, and include an error of plus or minus 10%.

Furthermore, in the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, the "X direction" refers to the direction along the X axis, and the forward direction and reverse direction may not be distinguished from each other unless explicitly stated. The same applies to the "Y direction" and "Z direction." Furthermore, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, or Z direction may be referred to as the "first direction" or "first direction." Furthermore, the other may be referred to as the "second direction" or "second direction." Furthermore, the remaining one may be referred to as the "third direction" or "third direction."

Generally, "capacitance" has a configuration in which two electrodes face each other with an insulator (dielectric) interposed between them. In this specification, "capacitance element" includes the aforementioned "capacitance." That is, in this specification, "capacitance element" includes an element having a configuration in which two electrodes face each other with an insulator interposed between them, an element having a configuration in which two wires face each other with an insulator interposed between them, or an element in which two wires are arranged with an insulator interposed between them. Also, in this specification, one electrode of a capacitance element may be referred to as the "first terminal of the capacitance element," and the other electrode may be referred to as the "second terminal of the capacitance element."

In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]" may be added to the reference numeral.

In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Furthermore, even if there is a time during the operation of the circuit when no electrical signal is exchanged or an electrical potential interaction occurs between A and B, if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B, then it can still be defined that "A and B are indirectly connected."

An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, this would be the case when a capacitive element is connected between A and B, or when a transistor gate insulating film or the like is present between A and B. Therefore, it cannot be said that "the transistor gate (A) and the transistor source or drain (B) are indirectly connected."

Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another from a power supply, GND, etc.

(Embodiment 1)
A semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. The semiconductor device according to one embodiment of the present invention can be used as, for example, a memory cell.

<Configuration example of semiconductor device>
FIG. 1A is a plan view of a semiconductor device 10A according to one embodiment of the present invention. FIG. 1B is a perspective view of the semiconductor device 10A. FIG. 1C shows an example of a cross-sectional structure between A1 and A2 indicated by a dashed line in FIG. 1A. FIG. 1D shows an example of a cross-sectional structure between A3 and A4 indicated by a dashed line in FIG. 1A. FIG. 1E is an equivalent circuit diagram of the semiconductor device 10A. Note that in order to facilitate understanding of the configuration of the semiconductor device 10A, some components are omitted from perspective views, plan views, etc.

As shown in the circuit diagram of Figure 1E, the semiconductor device 10A includes a capacitor 110 and a transistor 120. One electrode of the capacitor 110 is connected to a wiring PL, and the other electrode of the capacitor 110 is connected to one of the source and drain of the transistor 120. The other of the source and drain of the transistor 120 is connected to a wiring BL. The gate of the transistor 120 is connected to a wiring WL. The wiring PL functions as a power supply line and has a function of supplying a fixed potential to one electrode of the capacitor 110. The wiring BL functions as a bit line. The wiring WL functions as a word line.

A specific example configuration of semiconductor device 10A will be described. Semiconductor device 10A has a conductive layer 102 on an insulating layer 101. The conductive layer 102 functions as wiring PL. An insulating layer 103 is also on the conductive layer 102. An opening 104 that penetrates the insulating layer 103 and reaches the conductive layer 102 is also provided in the region overlapping with the conductive layer 102. Note that in the semiconductor device 10A shown in this embodiment, the planar shape of opening 104 (shape as viewed from the Z direction) is an oval shape including straight and curved portions, but it can also be an oval shape (ellipse) that does not include straight portions. The shape of opening 104 can also be other than an oval. For example, it can be a polygon.

A conductive layer 105 is provided covering the inner wall of the opening 104. The conductive layer 105 has a region that connects to the conductive layer 102 in the opening 104. The conductive layer 105 also has a region that overlaps with the side surface of the insulating layer 103 in the opening 104. The conductive layer 105 also has a region that extends on the insulating layer 103 in a direction perpendicular to the Z direction (e.g., the Y direction).

Semiconductor device 10A also has insulating layer 106 on insulating layer 103 and conductive layer 105. Also, conductive layer 107 is on insulating layer 106, including a region that overlaps with opening 104. Conductive layer 107 has a region inside opening 104 that overlaps with conductive layer 105 via insulating layer 106. Conductive layer 107 also has a region that overlaps with the side of insulating layer 103 via insulating layer 106 and conductive layer 105. Conductive layer 107 also has a region that overlaps with conductive layer 102 via insulating layer 106 and conductive layer 105.

The region where the conductive layer 105 and the conductive layer 107 overlap with each other via the insulating layer 106 functions as the capacitor 110. The conductive layer 105 functions as one electrode of the capacitor 110. The conductive layer 107 functions as the other electrode of the capacitor 110. The capacitor 110 included in the semiconductor device 10A according to one embodiment of the present invention has a region that extends along the side surface of the insulating layer 103 in the opening 104. This gives the capacitor 110 a large capacitance per unit occupied area. Furthermore, the capacitance of the capacitor 110 can be increased or decreased by adjusting the thickness of the insulating layer 103. In other words, the capacitance per unit occupied area can be easily adjusted.

A capacitor whose capacitance can be adjusted mainly by the thickness of the insulating layer 103, such as the capacitor 110 included in the semiconductor device 10A according to one embodiment of the present invention, is also called a "vertical capacitor" or "VC (Vertical Capacitor)."

Semiconductor device 10A also has conductive layers 109a and 109b on insulating layer 106 and conductive layer 107. In this specification and elsewhere, conductive layers 109a and 109b may be collectively referred to as conductive layer 109. Furthermore, in the region overlapping conductive layer 107, an opening 111 is provided that penetrates insulating layer 108 and reaches conductive layer 107. As shown in FIG. 1C , in the cross-sectional structure viewed from the Y direction, opening 111 can be said to penetrate not only insulating layer 108 but also conductive layer 109. In semiconductor device 10A shown in this embodiment, the shape of opening 111 viewed from the Z direction is oval, but the shape of opening 111 can also be other than oval.

A semiconductor layer 112 is provided covering the inner wall of the opening 111. The semiconductor layer 112 has a region that runs along the inside of the opening 111. The semiconductor layer 112 also has a region that connects to the conductive layer 107 in the opening 111. The semiconductor layer 112 also has a region that overlaps with the side surface of the insulating layer 108 in the opening 111. The semiconductor layer 112 also has a region that contacts the side surface of the conductive layer 109 in the opening 111. The semiconductor layer 112 also has a region that extends in the X direction on the conductive layer 109 and a region that extends in the Y direction on the insulating layer 108.

Semiconductor device 10A also has an insulating layer 113 on insulating layer 108 and conductive layer 109. Also, on insulating layer 113, a conductive layer 114 is also provided, including a region that overlaps with opening 111. Inside opening 111, conductive layer 114 has a region that overlaps with semiconductor layer 112 via insulating layer 113. Also, conductive layer 114 has a region that overlaps with a side surface of insulating layer 108 via insulating layer 113 and semiconductor layer 112. Also, conductive layer 114 has a region that overlaps with conductive layer 107 via insulating layer 113 and semiconductor layer 112.

Insulating layer 115 is also provided on conductive layer 114 and insulating layer 113.

The conductive layer 107 functions as one of the source electrode and the drain electrode of the transistor 120. The conductive layer 109 functions as the other of the source electrode and the drain electrode of the transistor 120. The insulating layer 113 functions as the gate insulating layer of the transistor 120. The conductive layer 114 functions as the gate electrode of the transistor 120.

It is preferable to use an OS transistor (a transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed) as the transistor constituting the transistor 120. Since oxide semiconductors have a band gap of 2 eV or more, their off-state current is significantly low.

The off-state current of an OS transistor per 1 μm of channel width at room temperature can be 1 aA (1×10 ⁻¹⁸ A) or less, 1 zA (1×10 ⁻²¹ A) or less, or 1 yA (1×10 ⁻²⁴ A) or less. Note that the off-state current of a Si transistor (a transistor containing silicon in a semiconductor layer in which a channel is formed) per 1 μm of channel width at room temperature is 1 fA (1×10 ⁻¹⁵ A) or more and 1 pA (1×10 ⁻¹² A) or less. Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

By using an OS transistor as the transistor 120, the charge written to the capacitor 110 can be held for a long period of time. By using an OS transistor as the transistor 120, the operation of rewriting data at a predetermined cycle (refresh operation) is unnecessary. Alternatively, the frequency of refresh operations can be significantly reduced. Therefore, the power consumption of the semiconductor device 10A functioning as a memory cell can be reduced.

In this specification and elsewhere, a memory cell using an OS transistor or a storage device using an OS transistor is also referred to as "OS memory."

Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range from room temperature to 200°C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. Semiconductor devices including OS transistors operate stably and have high reliability even in a high-temperature environment.

In addition, OS transistors have a high breakdown voltage between the source and drain. By using OS transistors as transistors that constitute a semiconductor device, stable operation can be achieved even when the transistor size is reduced, resulting in a highly reliable semiconductor device.

The transistor 120 included in the semiconductor device 10A according to one embodiment of the present invention is a transistor in which the source electrode and the drain electrode are spaced apart in the Z direction. That is, the source and drain of the transistor 120 are located at different heights. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

Here, we will explain in more detail an example configuration of the transistor 120, which is a vertical transistor, and an example configuration of the capacitor 110, which is a vertical capacitor.

<Vertical transistor>
6A is a plan view of a transistor 120 applicable to a semiconductor device 10A according to one embodiment of the present invention. Fig. 6B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in Fig. 6A. Note that Fig. 6A illustrates a case where the shape of the opening 111 is circular when viewed from the Z direction.

As described above, the conductive layer 107 functions as one of the source and drain electrodes of the transistor 120, and the conductive layer 109 functions as the other of the source and drain electrodes of the transistor 120. The region of the semiconductor layer 112 in contact with the conductive layer 107 functions as one of the source and drain regions of the transistor 120, and the region of the semiconductor layer 112 in contact with the conductive layer 109 functions as the other of the source and drain regions of the transistor 120.

Furthermore, the region of the semiconductor layer 112 along the side surface of the insulating layer 108 functions as a channel formation region. Therefore, the length from the conductive layer 107 to the conductive layer 109 on the side surface of the insulating layer 108 becomes the channel length L of the transistor 120 (see Figure 6B). In other words, the channel length L of the transistor 120, which is a vertical transistor, is determined by the thickness ta of the insulating layer 108. Note that in this specification, the insulating layer 108 may also be referred to as a spacer layer.

Furthermore, the channel formation region of the semiconductor layer 112 is formed in a cylindrical shape along the side surface of the insulating layer 108 within the opening 111. Therefore, the perimeter of the opening 111 when viewed from the Z direction is the channel width W of the transistor 120 (see Figure 6A). Note that, if necessary, the perimeter of any position of the opening 111 can be set to the channel width W. For example, the perimeter of the bottom of the opening can be set to the channel width W, or the perimeter of the top of the opening 111 can be set to the channel width W. Furthermore, for example, the perimeter of the opening 111 can be set to a position halfway through the thickness ta of the insulating layer 108. Although the planar shape of the opening 111 is shown as a circle in Figure 6A, this is not limiting. For example, the planar shape of the opening 111 when viewed from the Z direction can be an oval, polygon, or the like.

Furthermore, as shown in FIG. 7A, it is preferable that the side surface of the opening 111 has a slope. By having the side surface of the opening 111 have a slope, it is possible to improve the coverage of the semiconductor layer 112, the insulating layer 113, and the conductive layer 114, including the region formed inside the opening 111. Specifically, it is preferable that the side surfaces of the insulating layer 108 and the conductive layer 109 exposed by the formation of the opening 111 have a slope. In this specification, the angle between the bottom surface and the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) is referred to as the "taper angle θ."

By reducing the taper angle θ of each of the insulating layer 108 and the conductive layer 109, the coverage of the semiconductor layer 112, insulating layer 113, and conductive layer 114 to be formed later can be improved. That is, the semiconductor layer 112, insulating layer 113, and conductive layer 114 can be easily formed on the inner wall of the opening 111. On the other hand, the smaller the taper angle θ, the larger the area occupied by the opening 111. Therefore, the area occupied by the transistor 120 increases, making it difficult to miniaturize and highly integrate the transistor 120. Furthermore, the larger the taper angle θ of each of the insulating layer 108 and the conductive layer 109, the lower the coverage of the semiconductor layer 112, insulating layer 113, and conductive layer 114, resulting in a decrease in the manufacturing yield and reliability of the transistor 120. For these reasons, the taper angle θ of each of the side surfaces of the insulating layer 108 and the conductive layer 109 is preferably 45° or greater and less than 90°, and more preferably 50° or greater and 75° or less. The taper angles θ of the side surfaces of the insulating layer 108 and the conductive layer 109 can be the same or different.

7B , during the formation of the opening 111, depending on the etching conditions for the conductive layer 107 and the insulating layer 108, a portion of the conductive layer 107 may be removed. The bottom of the opening 111 may also include a curved portion. The curved portion at the bottom of the opening 111 may also cause the semiconductor layer 112, the insulating layer 113, and other layers formed on the curved portion to also have curved portions. This reduces electric field concentration in the insulating layer 113 near the curved portion when a voltage is applied to the conductive layer 114, improving the dielectric strength of the transistor 120 and suppressing electrostatic breakdown of the transistor 120. Therefore, the reliability of the semiconductor device can be improved. Furthermore, when viewed in a direction perpendicular to the Z direction (e.g., the Y direction), the conductive layer 114, which functions as the gate electrode of the transistor 120, and the conductive layer 107, which functions as one of the source and drain electrodes of the transistor 120, preferably have an overlapping region. By doing so, an electric field can be applied from the conductive layer 114 to the entire semiconductor layer 112 that overlaps with the insulating layer 108, which improves the electrical characteristics of the transistor 120. For example, the on-state current of the transistor 120 can be increased.

Vertical transistors can occupy a smaller area than transistors in which the channel formation region, source region, and drain region are provided separately on the XY plane (also called "horizontal transistors"). Therefore, by using vertical channel transistors in a semiconductor device, the area occupied by the semiconductor device can be reduced. Furthermore, by using vertical channel transistors in a semiconductor device, high integration of the semiconductor device can be achieved.

Furthermore, in a horizontal transistor, the channel length is limited by the exposure limit of photolithography. In a vertical channel transistor according to one embodiment of the present invention, the channel length can be set by the film thickness of the insulating layer 108. Therefore, the channel length of the transistor can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more). This increases the on-state current of the transistor, thereby improving frequency characteristics. By using a vertical channel transistor, a semiconductor device with high operating speed can be provided.

<Vertical Capacitor>
Fig. 8A is a plan view of a capacitor 110 applicable to a semiconductor device 10A according to one embodiment of the present invention. Fig. 8B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in Fig. 8A. Note that Fig. 8A illustrates a case where the shape of the opening 104 is circular when viewed from the Z direction.

As described above, the conductive layer 105 functions as one electrode of the capacitor 110, and the conductive layer 107 functions as the other of the source and drain electrodes of the capacitor 110. The region where the conductive layer 105 and the conductive layer 107 overlap with each other with the insulating layer 106 interposed therebetween functions as the capacitor 110.

The capacitance of the capacitance element 110 is determined by the relative dielectric constant of the insulating layer 106, the area where the conductive layers 105 and 107 overlap, and the distance at which the conductive layers 105 and 107 face each other. That is, in this embodiment, the capacitance is determined by the sum of the area where the conductive layers 105 and 107 overlap at the bottom of the opening 104, the area where the conductive layers 105 and 107 overlap on the insulating layer 103, and the area where the conductive layers 105 and 107 overlap along the side of the insulating layer 103.

Furthermore, the capacitance of the vertical capacitance element 110 can be determined primarily by the area where the conductive layers 105 and 107 overlap along the side of the insulating layer 103. In other words, it can be determined by the product of the thickness tb of the insulating layer 103 and the perimeter (length Wc) of the opening 104 when viewed from the Z direction.

Note that, if necessary, the perimeter of any position on the opening 111 can be set to length Wc. For example, the perimeter of the bottom of the opening 104 can be set to length Wc, or the perimeter of the top of the opening 104 can be set to length Wc. Also, for example, the perimeter of the opening 104 can be set to a position halfway through the thickness tb of the insulating layer 103. In addition, although the planar shape of the opening 104 is shown as a circle in Figure 8A, this is not limited to this. For example, the planar shape of the opening 104 can be an oval, a polygon, or the like.

Furthermore, as with the opening 111, in order to improve the coverage of the conductive layer 105 and the insulating layer 106, the taper angle θ (not shown) of the side surface of the opening 104 is preferably 45° or more and 90° or less, and more preferably 50° or more and 75° or less.

Also, as shown in FIG. 9A , when forming the opening 104, depending on the etching conditions for the insulating layer 103, part of the conductive layer 102 may be removed. Furthermore, the bottom of the opening 104 may include a curved portion. Removing part of the conductive layer 102 increases the area of the region of the capacitance element 110 corresponding to the bottom of the opening 104, thereby increasing the capacitance of the capacitance element 110. Also, including a curved portion in the bottom of the opening 104 increases the area of the region of the capacitance element 110 corresponding to the bottom of the opening 104, thereby increasing the capacitance of the capacitance element 110.

Also, the capacitor element 110 can be configured as shown in Figure 9B. In Figure 9B, the end 121 of the conductive layer 105 is located lower than the upper surface of the insulating layer 103. This makes it possible to suppress electric field concentration in the insulating layer 106 near the end 121, compared to when the end 121 is located on the insulating layer 103. By suppressing electric field concentration in the insulating layer 106, dielectric breakdown of the insulating layer 106 can be suppressed, and a highly reliable semiconductor device can be provided.

Note that Figure 9B shows an example in which region 122 between the upper surface of insulating layer 103 and the side surface of opening 104 has a curved portion. By having region 122 have a curved portion, it is possible to suppress electric field concentration in insulating layer 106 near region 122. By suppressing electric field concentration in insulating layer 106, it is possible to suppress dielectric breakdown of insulating layer 106 and provide a highly reliable semiconductor device.

<Plane shape of openings and number of openings>
As described above, increasing the perimeter of the opening 111 can increase the on-current of the transistor 120. Increasing the perimeter of the opening 104 can increase the capacitance of the capacitor 110. For example, if the planar shape of the opening 111 or the opening 104 is circular when viewed from the Z direction and its diameter is 60 nm, the circumference is 188.5 nm. As shown in FIG. 1A , making the opening 111 an oval that is elongated in the Y direction can increase the on-current of the transistor 120. In addition, making the opening 104 an oval that is elongated in the Y direction can increase the capacitance of the capacitor 110.

Increasing the on-state current of the transistor 120 increases the operating speed of the semiconductor device 10A. Increasing the capacitance of the capacitor 110 also increases the data retention capability of the semiconductor device 10A. Increasing the capacitance of the capacitor 110 also reduces the effect of the parasitic capacitance of the bit line, thereby improving the accuracy of reading retained data. This improves the reliability of the semiconductor device 10A.

For example, as shown in FIG. 10A, if the width of the oval is 60 nm and the length is 140 nm, the circumference is 349 nm. Therefore, the circumference can be made approximately 1.9 times that of a circle with a diameter of 60 nm. Therefore, the on-state current of the transistor 120 can be increased by approximately 1.9 times. Furthermore, the capacitance of the capacitor 110 can be increased by approximately 1.9 times.

In other words, when the opening 111 is viewed in a plan view (when viewed from the Z direction), the on-current of the transistor 120 can be increased by making the length 151 of the opening 111 in the first direction different from the length 152 in the second direction perpendicular to the first direction. Here, for example, if the first direction is the X direction, the second direction corresponds to the Y direction. Furthermore, when the shape of the opening 111 viewed in a plan view, i.e., the planar shape of the opening 111, is oval, the length in the first direction corresponds to the length in the direction of the minor axis, and the length in the second direction corresponds to the length in the direction of the major axis. Furthermore, when the planar shape of the opening 111 is rectangular, the length in the first direction corresponds to the length of the opposite sides in the shorter direction, and the length in the second direction corresponds to the length of the opposite sides in the longer direction.

Furthermore, by making the length 151 in the first direction and the length 152 in the second direction perpendicular to the first direction different when the opening 104 is viewed in a plan view, the capacitance of the capacitive element 110 can be increased. As with the opening 111, when the shape of the opening 104 when viewed in a plan view, i.e., the planar shape of the opening 104, is oval, the first direction corresponds to the direction of the minor axis, and the second direction corresponds to the direction of the major axis. Furthermore, when the planar shape of the opening 104 is rectangular, the length in the first direction corresponds to the direction in which the distance between opposing sides is shorter, and the second direction corresponds to the direction in which the distance is longer.

In addition, even if the planar shape of opening 111 and opening 104 is a shape other than oval or rectangular, the length in the first direction and the length in the second direction can be determined based on the above concept.

Note that the first direction length 151 and second direction length 152 of the opening 111 can be the length at the top of the opening 111, the length at the bottom of the opening 111, or the length from the top to the bottom of the opening 111. Similarly, the first direction length 151 and second direction length 152 of the opening 104 can be the length at the top of the opening 104, the length at the bottom of the opening 104, or the length from the top to the bottom of the opening 104.

Furthermore, when the length 151 in the first direction is shorter than the length 152 in the second direction, the length 152 in the second direction is preferably 1.5 to 10 times the length 151 in the first direction, and more preferably 2 to 5 times. By keeping the relationship between the length 152 in the second direction and the length 151 in the first direction within the above range, it is possible to prevent a significant increase in the area occupied by the transistor 120 and increase the on-current of the transistor 120. It is also possible to prevent a significant increase in the area occupied by the capacitance element 110 and increase the capacitance of the capacitance element 110.

Next, consider the case where the area occupied by opening 111 or opening 104 is fixed at 60 nm x 140 nm. For example, as shown in Figure 10B, if two openings 111 with a diameter of 60 nm are provided in a rectangular area of 60 nm x 140 nm, the total perimeter of the two openings is 379 nm, which is longer than when an ellipse is used. This further increases the on-state current of transistor 120. Similarly, if two openings 104 with a diameter of 60 nm are provided in a rectangular area of 60 nm x 140 nm, the capacitance of capacitor 110 can be increased compared to when an ellipse is used.

Furthermore, as shown in FIG. 10C, if ten openings 111 each having a diameter of 24 nm are provided in a rectangular region of 60 nm x 140 nm, the total perimeter of the ten openings is 751 nm. Therefore, the on-state current of the transistor 120 can be further increased. Similarly, if ten openings 104 each having a diameter of 24 nm are provided in a rectangular region of 60 nm x 140 nm, the capacitance of the capacitor 110 can be further increased.

Note that the same effect as above can be achieved even when the planar shape of openings 111 and openings 104 is a shape other than a circle. Figures 10D to 10F show the relationship between the number of openings and the total perimeter when the planar shape of openings 111 or openings 104 is a rectangle.

As shown in Figure 10D, when opening 111 or opening 104 is a rectangle measuring 60 nm x 140 nm, the perimeter is 400 nm. Furthermore, as shown in Figure 10E, if two square openings 111 or openings 104 with a side length of 60 nm are provided in a rectangular area of 60 nm x 140 nm, the total perimeter of the two openings is 480 nm. Furthermore, as shown in Figure 10F, if ten square openings 111 or openings 104 with a side length of 24 nm are provided in a rectangular area of 60 nm x 140 nm, the total perimeter of the ten openings is 960 nm.

In this way, by dividing the opening 104 into multiple parts, the total perimeter can be increased even with the same occupied area. Therefore, the on-state current of the transistor 120 per unit occupied area can be increased. Similarly, by dividing the opening 104 into multiple parts, the total perimeter can be increased even with the same occupied area. Therefore, the capacitance of the capacitor 110 per unit occupied area can be increased. Therefore, the operating speed, reliability, and the like of the semiconductor device 10A can be improved without increasing the occupied area. Furthermore, the occupied area of the transistor 120 can be reduced without reducing the on-state current of the transistor 120. Furthermore, the occupied area of the capacitor 110 can be reduced without reducing the capacitance of the capacitor 110. Therefore, the memory density of a memory device using the semiconductor device 10A as a memory cell can be increased. Furthermore, the memory capacity of a memory device using the semiconductor device 10A as a memory cell can be increased.

<Modification 1>
A configuration example of a semiconductor device 10B, which is a modification of the semiconductor device 10A, will be described with reference to FIGS. 2A to 2E . FIG. 2A is a plan view of the semiconductor device 10B according to one embodiment of the present invention. FIG. 2B is a perspective view of the semiconductor device 10B. FIG. 2C shows an example of a cross-sectional structure between A1 and A2 indicated by a dashed line in FIG. 2A . FIG. 2D shows an example of a cross-sectional structure between A3 and A4 indicated by a dashed line in FIG. 2A . FIG. 2E is an equivalent circuit diagram of the semiconductor device 10B. Note that in order to facilitate understanding of the configuration of the semiconductor device 10B, some components are omitted from perspective views, plan views, and the like.

Semiconductor device 10B differs from semiconductor device 10A in that it has two openings 111 and two transistors 120. To reduce repetition, the following description will mainly focus on the differences between semiconductor device 10B and semiconductor device 10A.

Semiconductor device 10B has opening 111[1] that overlaps with a portion of conductive layer 107 and opening 111[2] that overlaps with another portion of conductive layer 107. Semiconductor device 10B also has transistor 120[1] and transistor 120[2].

In semiconductor device 10B, semiconductor layer 112 is provided to cover opening 111[1] and opening 111[2]. Semiconductor layer 112 also has a region along the inside of opening 111[1] and a region along the inside of opening 111[2]. The channel formation region of transistor 120[1] is formed in semiconductor layer 112 along the side surface of insulating layer 108 in opening 111[1]. The channel formation region of transistor 120[2] is formed in semiconductor layer 112 along the side surface of insulating layer 108 in opening 111[2].

Furthermore, the insulating layer 113 is provided to cover the semiconductor layer 112. In the semiconductor device 10B, the insulating layer 113 has a region along the inside of the opening 111[1] and a region along the inside of the opening 111[2]. Therefore, a part of the insulating layer 113 functions as the gate insulating layer for the transistor 120[1], and another part functions as the gate insulating layer for the transistor 120[2]. Furthermore, the conductive layer 114 has a region along the inside of the opening 111[1] and a region along the inside of the opening 111[2].

In the semiconductor device 10B, the conductive layer 107 functions as one of the source and drain electrodes of the transistor 120[1] and one of the source and drain electrodes of the transistor 120[2]. In the semiconductor device 10B, the conductive layer 109 functions as the other of the source and drain electrodes of the transistor 120[1] and the other of the source and drain electrodes of the transistor 120[2]. In the semiconductor device 10B, the conductive layer 114 functions as the gate electrode of the transistor 120[1] and the gate electrode of the transistor 120[2].

That is, as shown in the equivalent circuit diagram of Figure 2E, semiconductor device 10B has a configuration in which transistor 120[1] and transistor 120[2] are connected in parallel. Transistor 120[1] and transistor 120[2] connected in parallel essentially function as a single transistor.

Vertical transistors are easier to form than horizontal transistors, allowing multiple transistors to be connected in parallel. Furthermore, vertical transistors allow multiple transistors to be connected in parallel in a smaller area than horizontal transistors.

As described above, by increasing the number of openings 111, the on-state current of the transistor can be increased without increasing the occupied area. Semiconductor device 10B according to one aspect of the present invention can achieve a higher operating speed than semiconductor device 10A without increasing the occupied area.

Note that, although this embodiment shows an example configuration of the semiconductor device 10B having two openings 111 on the conductive layer 107, the semiconductor device 10B according to one embodiment of the present invention can have three or more openings 111.

<Modification 2>
A configuration example of a semiconductor device 10C, which is a modification of the semiconductor device 10A, will be described with reference to FIGS. 3A to 3E . FIG. 3A is a plan view of the semiconductor device 10C according to one embodiment of the present invention. FIG. 3B is a perspective view of the semiconductor device 10C. FIG. 3C shows an example of a cross-sectional structure between A1 and A2 indicated by a dashed line in FIG. 3A . FIG. 3D shows an example of a cross-sectional structure between A3 and A4 indicated by a dashed line in FIG. 3A . FIG. 3E is an equivalent circuit diagram of the semiconductor device 10C. Note that to facilitate understanding of the configuration of the semiconductor device 10C, some components are omitted from perspective views, plan views, and the like.

Semiconductor device 10C differs from semiconductor device 10A in that it has two openings 104. To reduce repetition, the following description will mainly focus on the differences between semiconductor device 10C and semiconductor device 10A.

Semiconductor device 10C has opening 104[1] that overlaps with a portion of conductive layer 102 and opening 104[2] that overlaps with another portion of conductive layer 102. In semiconductor device 10C, conductive layer 105 is provided to cover opening 104[1] and opening 104[2]. Conductive layer 105 also has a region along the inside of opening 104[1] and a region along the inside of opening 104[2].

Furthermore, insulating layer 106 is provided to cover conductive layer 105. In semiconductor device 10C, insulating layer 106 has a region that runs along the inside of opening 104[1] and a region that runs along the inside of opening 104[2]. Furthermore, conductive layer 107 is provided on insulating layer 106. Furthermore, conductive layer 107 has a region that runs along the inside of opening 104[1] and a region that runs along the inside of opening 104[2].

In semiconductor device 10C, if the region inside opening 104[1] where conductive layer 105 and conductive layer 107 overlap each other with insulating layer 106 interposed therebetween is defined as capacitance element 110[1], and the region inside opening 104[2] where conductive layer 105 and conductive layer 107 overlap each other with insulating layer 106 interposed therebetween is defined as capacitance element 110[2], then semiconductor device 10C can be said to have a configuration in which capacitance element 110[1] and capacitance element 110[2] are connected in parallel (see Figure 3E). Capacitance elements 110[1] and 110[2] connected in parallel essentially function as a single capacitance element 110.

Vertical capacitor elements make it easy to form multiple capacitor elements connected in parallel. Furthermore, by increasing the number of openings 104, the area where the conductive layers 105 and 107 overlap can be increased without increasing the occupied area. Therefore, by increasing the number of openings 104, the capacitance of the capacitor element can be increased without increasing the occupied area.

The semiconductor device 10C according to one embodiment of the present invention can improve data retention capability compared to the semiconductor device 10A without increasing the occupied area. It can also improve data read accuracy compared to the semiconductor device 10A. Therefore, it can achieve higher reliability than the semiconductor device 10A.

Note that, although this embodiment shows an example configuration of the semiconductor device 10C having two openings 104 on the conductive layer 102, the semiconductor device 10C according to one embodiment of the present invention can have three or more openings 104.

<Modification 3>
4A to 4E , a configuration example of a semiconductor device 10D, which is a modification of the semiconductor device 10A, will be described. The semiconductor device 10D has a configuration that combines the semiconductor device 10B and the semiconductor device 10C. Therefore, the semiconductor device 10D is a modification of both the semiconductor device 10B and the semiconductor device 10C.

Figure 4A is a plan view of a semiconductor device 10D according to one embodiment of the present invention. Figure 4B is a perspective view of the semiconductor device 10D. Figure 4C shows an example of a cross-sectional structure between A1 and A2 indicated by a dashed line in Figure 4A. Figure 4D shows an example of a cross-sectional structure between A3 and A4 indicated by a dashed line in Figure 4A. Figure 4E is an equivalent circuit diagram of the semiconductor device 10D. Note that to make the configuration of the semiconductor device 10D easier to understand, some components are omitted from the perspective view, plan view, etc.

Semiconductor device 10D differs from semiconductor devices 10A, 10B, and 10C in that it has two openings 111 and two openings 104. By increasing the number of both openings 104 and openings 111, it is possible to increase both the on-state current of transistor 120 and the capacitance of capacitive element 110. By configuring semiconductor device 10D, it is possible to achieve improved operating speed and reliability without increasing the occupied area.

<Modification 4>
As described above, the planar shapes of the openings 104 and 111 are not limited to circular or elliptical. For example, the planar shapes of the openings 104 and 111 may be rectangular (see FIGS. 10D to 10F).

Figure 5A1 shows a plan view of semiconductor device 10Ar. Figure 5A2 shows a perspective view of semiconductor device 10Ar. Semiconductor device 10Ar has a configuration in which the planar shapes of openings 104 and 111 of semiconductor device 10A are rectangular.

Figure 5B1 shows a plan view of semiconductor device 10Br. Figure 5B2 shows a perspective view of semiconductor device 10Br. Semiconductor device 10Br has a configuration in which the planar shapes of openings 104 and 111 of semiconductor device 10B are rectangular.

Figure 5C1 shows a plan view of semiconductor device 10Dr. Figure 5C2 shows a perspective view of semiconductor device 10Dr. Semiconductor device 10Dr has a configuration in which the planar shapes of openings 104 and 111 of semiconductor device 10D are rectangular.

By making the planar shapes of openings 104 and 111 rectangular, it is possible to increase the on-state current of transistor 120 and the capacitance of capacitor 110.

<Constituent materials of semiconductor device>
Next, constituent materials that can be used in the semiconductor device 10 (semiconductor device 10A, semiconductor device 10B, semiconductor device 10C, semiconductor device 10D, semiconductor device 10Ar, semiconductor device 10Br, and semiconductor device 10Dr) according to one embodiment of the present invention will be described.

[substrate]
When the semiconductor device according to one embodiment of the present invention is provided over a substrate, the material used for the substrate is not particularly limited. The material used for the substrate is determined depending on the purpose, taking into consideration the presence or absence of light-transmitting properties and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used as the substrate. Examples of insulating substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). Furthermore, semiconductor substrates, flexible substrates, resin substrates, and the like can also be used as the substrate.

Semiconductor substrates include, for example, semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide (also called zinc oxide), or gallium oxide. Furthermore, there are semiconductor substrates that have an insulating region inside the aforementioned semiconductor substrate, such as SOI (Silicon On Insulator) substrates. Furthermore, the semiconductor substrate can be a single-crystal semiconductor or a polycrystalline semiconductor.

Conductor substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates containing metal nitrides and substrates containing metal oxides. Furthermore, there are substrates in which a conductive layer or semiconductor layer is provided on an insulator substrate, substrates in which a conductive layer or insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or insulating layer is provided on a conductive substrate.

Materials that can be used for flexible substrates, resin substrates, etc. include, for example, polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, cellulose nanofiber, etc.

By using the above materials for the substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is less likely to break can be provided. Furthermore, these substrates can be used with elements provided on them. Elements that can be provided on the substrate include capacitance elements, resistance elements, switching elements, light-emitting elements, and memory elements.

[Insulating layer]
The insulating layers (insulating layer 101, insulating layer 103, insulating layer 106, insulating layer 108, insulating layer 113, insulating layer 115, etc.) can each include an inorganic insulating film. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In addition, an organic insulating film can also be used for the insulating layers of a semiconductor device.

Note that in this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

For example, as transistors become more miniaturized and highly integrated, thinner gate insulating layers can cause problems such as leakage current. Using high-k materials for insulating layers that function as gate insulating layers, such as insulating layer 113, enables lower voltages during transistor operation while maintaining the physical film thickness. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for insulating layers that function as interlayer films can reduce the parasitic capacitance that occurs between wiring. Therefore, it is important to select materials according to the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

Examples of high-dielectric-constant (high-k) materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide with vacancies. Note that these silicon oxides may contain nitrogen.

A material capable of exhibiting ferroelectricity can be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include materials obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 atoms can be set appropriately; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to that. Examples of materials capable of exhibiting ferroelectricity include materials obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set as appropriate, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to or near 1:1. As a material that can have ferroelectricity, piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO _x (X is a real number greater than 0)), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), or barium titanate can be used.

Examples of materials that can have ferroelectricity include aluminum scandium _nitride (Al1 _{- aScaNb} (where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1; hereinafter, this may be referred to simply as "AlScN")), Al-Ga-Sc nitride, and Ga-Sc nitride. Examples of materials that can have ferroelectricity include metal nitrides containing an element M1, an element M2, and nitrogen. Here, the element M1 is one or more elements selected from aluminum, gallium, indium, and the like. The element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. The ratio of the number of atoms of the element M1 to the number of atoms of the element M2 can be set as appropriate. Furthermore, a metal oxide containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Examples of materials that may exhibit ferroelectricity include materials obtained by adding element M3 to the above-mentioned metal nitrides. The element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, and the like. The ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set. Since the above-mentioned metal nitrides contain at least a Group 13 element and nitrogen, which is a Group 15 element, the metal nitrides may be referred to as Group 13-15 ferroelectrics, Group 13 nitride ferroelectrics, etc.

Furthermore, materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO ₂ N and BaTaO ₂ N, and GaFeO ₃ with a κ-alumina structure.

Note that, although metal oxides and metal nitrides have been exemplified in the above explanation, the present invention is not limited to these. For example, metal oxide nitrides, in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides, in which oxygen is added to the aforementioned metal nitrides, can be used.

Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made up of multiple materials selected from the materials listed above can be used. For example, the insulating layer 106 can have a layered structure made up of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, etc., in this specification, a material that exhibits ferroelectricity is not only called a ferroelectric, but also called a material capable of exhibiting ferroelectricity.

Metal oxides containing hafnium and/or zirconium can exhibit ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing hafnium and/or zirconium can exhibit ferroelectricity even in very small areas. Therefore, by using metal oxides containing hafnium and/or zirconium, miniaturization of semiconductor devices can be achieved. A representative example of a metal oxide containing hafnium and zirconium is HfZrO _X. Furthermore, a metal oxide in which Y (yttrium) is added to HfZrO _X can also be used. Adding Y (yttrium) to HfZrO _X can enhance ferroelectricity.

In this specification, a material that can exhibit ferroelectricity may be referred to as a "ferroelectric material." A layer of ferroelectric material may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. A device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification.

Ferroelectricity is believed to be manifested when an external electric field displaces oxygen or nitrogen in crystals contained in the ferroelectric layer. It is also believed that the manifestation of ferroelectricity depends on the crystalline structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to manifest ferroelectricity, the insulating layer must contain crystals. It is particularly preferable for an insulating layer to contain crystals with an orthorhombic crystalline structure, as this will manifest ferroelectricity. The crystalline structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having both an amorphous structure and a crystalline structure.

Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the concentration of oxygen vacancies in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in an oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

Metal oxides containing one or both of hafnium and zirconium are preferred for the insulating layer 106 because, as mentioned above, they can exhibit ferroelectricity even in thin films of only a few nanometers. The film thickness of the insulating layer 106 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm).

Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in a small area, making them preferable for the insulating layer 106. For example, the ferroelectric layer can exhibit ferroelectricity even when its area (occupied area) in a plan view is 100 μm ² or less, 10 μm ² or less, 1 μm ² or less, or 0.1 μm ² or less. Furthermore, the ferroelectric layer may exhibit ferroelectricity even when its area is 10,000 nm ² or less, or 1,000 nm 2 or less. By using a ferroelectric layer with a small area, the occupied area of the semiconductor device can be reduced.

Ferroelectrics are insulators that are polarized internally when an external electric field is applied, and the polarization remains even when the electric field is removed. For this reason, ferroelectric materials can be used as dielectrics to form non-volatile memory elements. Non-volatile memory elements that use ferroelectric materials are sometimes called "ferroelectric memory."

The method for forming the insulating layer is not particularly limited, and various methods can be used, such as vapor deposition, atomic layer deposition (ALD), CVD, sputtering, and spin coating.

[Conductive layer]
For the conductive layers (conductive layer 102, conductive layer 105, conductive layer 107, conductive layer 114, etc.), it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy can be used. For example, it is preferable to use tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. Furthermore, it is possible to use a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide.

In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, and ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide (also referred to as indium oxide), indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide doped with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive layer formed using a conductive material containing oxygen may be referred to as an oxide conductive layer.

Conductive materials primarily composed of tungsten, copper, or aluminum are preferred due to their high conductivity.

It is also possible to use a stack of multiple conductive layers made of the above materials. For example, a stack structure can be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen. Also, a stack structure can be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen. Also, a stack structure can be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

For example, when an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 112 of the transistor 120, a conductive layer that functions as a gate electrode, such as the conductive layer 114, may have a stacked structure that combines a material containing the metal element described above and a conductive material containing oxygen. In this case, the conductive material containing oxygen may be provided on the semiconductor layer 112 side. By providing the conductive material containing oxygen on the semiconductor layer 112 side, oxygen desorbed from the conductive material is more easily supplied to the channel formation region of the semiconductor layer 112.

When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 112, the conductive layers 107 and 109 are each conductive layers in contact with the semiconductor layer 112. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has the function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 107 and the conductive layer 109.

By using a conductive material containing oxygen for the conductive layers 107 and 109, the conductive layers 107 and 109 can maintain their conductivity even when they absorb oxygen. For example, even when an insulating layer containing excess oxygen is used as an insulating layer in contact with the conductive layers 107 and 109, this is preferable because the conductive layers 107 and 109 can maintain their conductivity. For example, ITO, ITSO, IZO (registered trademark), etc. can be used for the conductive layers 107 and 109, respectively.

The method for forming the conductive layer is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.

[Semiconductor layer]
As the semiconductor layer 112, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. Organic materials having semiconductor properties can also be used as compound semiconductors. Metal oxides (also referred to as oxide semiconductors) having semiconductor properties can also be used as compound semiconductors. Note that these semiconductor materials can also contain impurities as dopants.

The semiconductor layer can be made of a semiconductor made of a single element or a compound semiconductor. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that oxide semiconductors are also a type of compound semiconductor. Note that it is also possible to include impurities as dopants in these semiconductor materials.

When silicon is used as the semiconductor layer, silicon that can be used for the semiconductor layer includes single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

For example, by using silicon for the semiconductor layer 112 of the transistor 120 and adding phosphorus or arsenic as an n-type dopant to the source and drain regions of the semiconductor layer 112, the transistor can function as an n-type transistor. Also, by adding boron as a p-type dopant to the source and drain regions of the semiconductor layer 112, the transistor can function as a p-type transistor. Note that when the source and drain regions of the semiconductor layer 112 contain both n-type and p-type dopants, the conductivity type with the higher dopant concentration is more likely to be expressed.

A two-dimensional material that functions as a semiconductor can be used for the semiconductor layer 112. Two-dimensional materials are also called layered materials and are a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within each layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the semiconductor layer, a transistor with a large on-state current can be provided.

Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (typically MoS ₂ ), molybdenum selenide (typically MoSe ₂ ), molybdenum tellurium (typically MoTe 2 ), tungsten sulfide (typically WS ₂ ), tungsten selenide (typically WSe ₂ ), tungsten tellurium (typically WTe _{2 )} , hafnium sulfide (typically HfS ₂ ), hafnium selenide (typically HfSe ₂ ), zirconium sulfide (typically ZrS ₂ ), and zirconium selenide (typically ZrSe ₂ ).

When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 112, the band gap of the metal oxide is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2.0 eV or more, and more preferably 2.5 eV or more. By using a metal oxide that functions as a semiconductor layer and has a band gap larger than that of silicon, the off-state current of the transistor can be significantly reduced. Because an OS transistor has a small off-state current, the power consumption of the semiconductor device can be reduced. Note that the metal oxide used for the semiconductor layer will be described in detail in Embodiment 2.

The method for forming the semiconductor layer is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.

The configuration described in this embodiment can be used in appropriate combination with the configurations described in other embodiments.

(Embodiment 2)
In this embodiment, a metal oxide that can be used for a semiconductor layer of a transistor will be described. As the semiconductor layer of a transistor, a layer containing a metal oxide can be used as a single layer or a stacked layer. Note that in a metal oxide having a stacked structure, the boundaries between stacked layers may be unclear, as will be described later.

[Metal oxides]
The metal oxide preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide contains indium and zinc as the main components and may further contain element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide preferably contains one or more selected from indium, gallium, and zinc. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

Examples of metal oxides include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), and indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO). Examples of usable metal oxides include indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of usable metal oxides include gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as the metal oxide. Gallium oxide, zinc oxide, and the like can also be used.

By increasing the indium content in the metal oxide, the transistor can achieve a large on-state current and high frequency characteristics.

Instead of indium, the metal oxide can contain one or more metal elements with higher periodic numbers in the periodic table. Alternatively, the metal oxide can contain, in addition to indium, one or more metal elements with higher periodic numbers in the periodic table. The greater the overlap between the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element with a higher periodic number in the periodic table can sometimes improve the field-effect mobility of a transistor. Examples of metal elements with higher periodic numbers in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

Furthermore, metal oxides can contain one or more nonmetallic elements. When metal oxides contain nonmetallic elements, the field-effect mobility of transistors can be increased in some cases. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

Furthermore, by increasing the zinc content in the metal oxide, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide. This therefore suppresses fluctuations in the electrical characteristics of the transistor and improves reliability.

Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies is suppressed, resulting in a transistor with a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, improving reliability.

A structural example of a metal oxide that can increase the field-effect mobility of a transistor will be described. For example, it is preferable to use a stacked structure of indium oxide and IGZO. Specifically, it is preferable that the metal oxide has indium oxide and IGZO on the indium oxide. Furthermore, it is preferable to use IGZO containing nitrogen as the metal oxide. For example, IGZO containing nitrogen can be formed by performing N ₂ O plasma treatment during or after film formation. Furthermore, it is preferable to use at least one of indium oxide, In—Ga oxide, In—Zn oxide, and IGZTO as the metal oxide.

In this embodiment, In-M-Zn oxide may be used as an example of a metal oxide.

The metal oxide preferably has crystallinity. Examples of crystalline metal oxide structures include a c-axis aligned crystal (CAAC) structure, a polycrystalline (Poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the semiconductor layer, the density of defect states in the semiconductor layer can be reduced. This can improve the reliability of a transistor that uses a metal oxide for the semiconductor layer. Furthermore, it can improve the reliability of a semiconductor device incorporating such a transistor.

Note that the crystallinity of the metal oxide used in the semiconductor layer is not particularly limited. For example, the semiconductor layer may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). The crystallinity of the semiconductor layer may help prevent deterioration of transistor characteristics.

The crystallinity of the semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, analysis can be performed by combining multiple of these techniques.

The metal oxide used in the semiconductor layer preferably has a CAAC structure. A CAAC structure is a crystal structure in which multiple microcrystals (typically multiple microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of a metal oxide having a CAAC structure is observed using a high-resolution TEM image (also called a multi-beam interference image), it can be confirmed that metal atoms are arranged in layers in the crystalline portion. Therefore, a metal oxide having a CAAC structure can also be said to have a structure having layered crystalline portions.

The CAAC structure is formed, for example, so that the c-axis is perpendicular or approximately perpendicular to the surface or surface of the metal oxide on which it is formed. In the CAAC structure, metal atoms are arranged in layers parallel or approximately parallel to the surface on which it is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less) relative to the surface on which it is formed, more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less).

When a metal oxide has a CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) that reflect the layered arrangement of metal atoms are observed in a cross-section of the metal oxide observed using a TEM image. Specifically, bright spots are observed to be arranged in layers parallel or approximately parallel to the surface on which they are formed.

When electron diffraction is performed on a metal oxide having a CAAC structure, spots (bright spots) indicating c-axis orientation are observed in the electron diffraction pattern.

Furthermore, the FFT pattern obtained by performing fast Fourier transform (FFT) processing on the TEM image reflects reciprocal lattice spatial information similar to that of an electron diffraction pattern.

A cross-sectional TEM image of a metal oxide having a CAAC structure is acquired, and an FFT pattern is created by performing FFT processing on each region within the cross-sectional TEM image. The crystal axis direction of each region can then be calculated from the created FFT pattern. Specifically, the direction of the line segment connecting two spots observed in the created FFT pattern that are high in brightness and approximately equidistant from the center is defined as the crystal axis direction. Regions where the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90° ± 20°) relative to the surface to be formed, more preferably 75° to 105° (within 90° ± 15°), more preferably 80° to 100° (within 90° ± 10°), and even more preferably 85° to 95° (within 90° ± 5°) can be considered to have a CAAC structure.

When metal oxides with a CAAC structure are viewed using TEM images in a direction perpendicular to the surface on which they are formed, triangular or hexagonal atomic arrangements are observed in the a-b plane, and the oxides are crystalline.

[Metal oxide composition]
The metal oxide preferably contains indium (In), and more preferably has a high In content. By using a metal oxide with a high In content for the semiconductor layer, the on-state current of the transistor can be increased, and the frequency characteristics can be improved. For example, it is preferable to use indium oxide for the semiconductor layer.

The metal oxide may also contain zinc. When the metal oxide contains zinc, it becomes a highly crystalline metal oxide, for example, a metal oxide having a CAAC structure. For example, In-Zn oxide can be used as the semiconductor layer. Specifically, metal oxides having a composition of In:Zn = 1:1 [atomic ratio] or a composition close to that, In:Zn = 2:1 [atomic ratio] or a composition close to that, or In:Zn = 4:1 [atomic ratio] or a composition close to that can be used. Note that a composition close to that includes a range of ±30% of the desired atomic ratio.

Furthermore, the metal oxide may contain element M. When the metal oxide contains element M, the formation of oxygen vacancies in the metal oxide can be suppressed. This can improve the reliability of transistors that use metal oxide as semiconductor layers.

For example, the semiconductor layer can be made of In-Zn oxide containing a trace amount of element M. Specifically, metal oxides having a composition of In:Ga:Zn = 4:0.1:1 (atomic ratio) or a similar composition, In:Ga:Zn = 2:0.1:1 (atomic ratio) or a similar composition, or In:Ga:Zn = 1:0.1:1 (atomic ratio) or a similar composition can be used. Also, metal oxides having a composition of In:Sn:Zn = 4:0.1:1 (atomic ratio) or a similar composition, In:Sn:Zn = 2:0.1:1 (atomic ratio) or a similar composition, or In:Sn:Zn = 1:0.1:1 (atomic ratio) or a similar composition can be used.

Furthermore, an In-Zn oxide containing element M can be used as the semiconductor layer. Specifically, metal oxides having a composition of In:M:Zn = 1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn = 4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn = 1:3:2 [atomic ratio] or a composition close thereto, or In:M:Zn = 1:3:4 [atomic ratio] or a composition close thereto can be used.

When metal oxides are formed by sputtering, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.

Furthermore, when depositing a metal oxide containing multiple metal elements, such as In-Ga-Zn oxide, using atomic layer deposition (ALD), the ratio of the number of cycles of precursors containing each metal element can be set to match the target composition. For example, when depositing an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:2, one cycle of depositing an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of depositing a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of depositing a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element and the atomic ratio of each metal element in the deposited metal oxide film may not match.

To analyze the composition of metal oxides, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, analysis can be performed by combining multiple of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

Metal oxides can also be formed into a stacked structure of two or more layers. When the metal oxide used as the semiconductor layer has a two-layer structure consisting of a first layer and a second layer on the first layer, it is preferable that the second layer have a different composition from the first layer. Furthermore, when the metal oxide used as the semiconductor layer has a three-layer structure consisting of a first layer, a second layer on the first layer, and a third layer on the second layer, it is preferable that the second layer have a different composition from the first and third layers. The first layer can have the same composition as the third layer. Alternatively, the first and third layers can have different compositions.

The first to third layers can each be made of the metal oxides mentioned above.

The second layer can be made of, for example, indium oxide, In-Zn oxide, or In-Zn oxide containing a trace amount of element M. Specifically, metal oxides having a composition of In:Zn = 1:1 (atomic ratio) or a similar composition, In:Zn = 2:1 (atomic ratio) or a similar composition, or In:Zn = 4:1 (atomic ratio) or a similar composition can be used. For example, metal oxides having a composition of In:Ga:Zn = 4:0.1:1 (atomic ratio) or a similar composition, In:Ga:Zn = 2:0.1:1 (atomic ratio) or a similar composition, or In:Ga:Zn = 1:0.1:1 (atomic ratio) or a similar composition can be used. Alternatively, for example, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a similar composition, an atomic ratio of In:Sn:Zn=2:0.1:1 or a similar composition, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a similar composition can be used. Increasing the In content in the second layer can increase the on-state current and improve the frequency characteristics.

The conduction band minimum of each of the first layer and the third layer is preferably located closer to the vacuum level than the conduction band minimum of the second layer. In other words, the energy of the conduction band minimum of each of the first layer and the third layer is preferably lower than the energy of the conduction band minimum of the second layer. In this case, the second layer is sandwiched between the first layer and the third layer, whose conduction band minimums are located closer to the vacuum level, and can function mainly as a current path (channel).

By sandwiching the second layer between the first and third layers, it is possible to reduce carriers trapped at the interface of the second layer and its vicinity. Furthermore, the channel can be moved away from the surface of the gate insulating layer, reducing the effects of surface scattering. This makes it possible to realize a buried channel transistor in which the channel is moved away from the insulating layer interface, thereby increasing field-effect mobility. Furthermore, the effects of interface states that may form on the back channel side are reduced, suppressing light degradation of the transistor (e.g., negative bias light degradation) and improving transistor reliability.

When forming a buried channel using the first to third layers, for example, the first and third layers can be made of a metal oxide with a higher Ga content than the second layer. Specifically, the first and third layers can each be made of a metal oxide with an atomic ratio of In:Ga:Zn = 1:1:1 or a similar composition, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:2 or a similar composition, or a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or a similar composition. Alternatively, Ga-Zn oxide or gallium oxide can be used. Increasing the Ga content of the first and third layers can position the conduction band minimum of each of the first and third layers closer to the vacuum level than the conduction band minimum of the second layer.

Furthermore, by increasing the Ga content in the first layer and the third layer, the barrier properties of the first layer and the third layer against hydrogen can be improved. This makes it possible to suppress the diffusion of hydrogen from below the first layer or above the third layer into the second layer. Furthermore, by increasing the Ga content in the first layer and the third layer, it is possible to reduce impurities such as hydrogen or water contained in the metal oxide used as the semiconductor layer due to heat or the like applied after its formation. Note that a similar effect may be achieved by using a metal oxide with a lower In content for the first layer and the third layer compared to the second layer.

For example, it is preferable to use a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a similar composition, In:Ga:Zn = 1:3:2 [atomic ratio] or a similar composition, or In:Ga:Zn = 1:3:4 [atomic ratio] or a similar composition for the third layer. In this case, the third layer contains indium and gallium.

Furthermore, by increasing the Ga content in the first and third layers, the oxygen barrier properties of the first and third layers can be improved. This prevents oxygen from being released from the second layer where the channel is formed, and prevents the formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer. This improves the electrical characteristics of the transistor.

Furthermore, by increasing the Ga content in the first layer, it may be possible to make the resistivity of the first layer higher than that of the second layer. When the first layer is provided on the back channel side, providing a layer with high resistivity as the first layer can suppress a negative shift in threshold voltage or a decrease in on-current. Therefore, the threshold voltage of the transistor is shifted positively, making it possible to make the transistor normally off. As a result, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

To evaluate the band gap of metal oxides, optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS) can be used. Analysis can also be performed by combining multiple of these techniques. The electron affinity or conduction band minimum can be determined from the ionization potential, which is the energy difference between the vacuum level and the top of the valence band, and the band gap. To evaluate the ionization potential, for example, ultraviolet photoelectron spectroscopy (UPS) can be used.

The first and third layers may be made of a metal oxide having a higher In content than the second layer. Also, one of the first and third layers may be made of a metal oxide having a higher In content than the second layer, and the other may be made of a metal oxide having a higher Ga content than the second layer.

Furthermore, the first layer, second layer, and third layer can each be a stack of layers having the composition described above. For example, the first layer can be configured by stacking a metal oxide with a high In content on a metal oxide with a high Ga content. For example, the third layer can be configured by stacking a metal oxide with a high Ga content on a metal oxide with a high In content.

[Method for producing metal oxide]
The metal oxide can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

Furthermore, the metal oxide used as the semiconductor layer can be produced using two different film formation methods. For example, the metal oxide used as the semiconductor layer can be produced using a first film formation method and a second film formation method.

The metal oxide used as the semiconductor layer can have a two-layer structure consisting of a first layer and a second layer on the first layer. When the metal oxide has a two-layer structure, the metal oxide can be produced by forming the first layer on the surface to be formed using a first film formation method, and then forming the second layer on top of the first layer using a second film formation method.

The first film formation method preferably causes less damage to the surface on which the metal oxide is formed than the second film formation method. This makes it possible to suppress the formation of a mixed layer at the interface between the metal oxide and the layer on which the metal oxide is formed. Furthermore, since it is possible to suppress the incorporation of impurities such as silicon into the second layer formed on the first layer, the crystallinity of the metal oxide layer may be increased.

Examples of the first film formation method include ALD, CVD, and MBE. Examples of CVD methods include plasma-enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and MOCVD. The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and is one of the film formation methods that causes minimal damage to the surface on which the film is formed. A wet method can also be used as the first film formation method. The wet method is one of the film formation methods that causes minimal damage to the surface on which the film is formed. Examples of wet methods include spray coating.

The second film formation method is preferably a method capable of forming a crystalline metal oxide film. It is particularly preferable that the metal oxide film formed in this case has a CAAC structure. Examples of the second film formation method include sputtering and PLD. Because metal oxide films formed using sputtering tend to be crystalline, sputtering is preferred as the second film formation method.

When a metal oxide is formed on a surface using the second film formation method, damage to the surface may cause alloying between components contained in the metal oxide and components contained in the layer on the surface. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface. This mixed layer may also be referred to as an alloyed region. The formation of a mixed layer may also be referred to as alloying.

For example, when sputtering is used as the second deposition method, a mixed layer may be formed by particles (also called sputtering particles) emitted from a target or the like, or by energy imparted to the substrate by the sputtering particles. Specifically, when a metal oxide film is formed using the second deposition method on a silicon-containing insulating layer, such as a silicon oxide film, as the deposition surface, silicon may be mixed into the metal oxide. There is a concern that the inclusion of impurities such as silicon in the metal oxide may inhibit the crystallization of the metal oxide. Furthermore, there is a concern that using a metal oxide layer containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when the heat treatment described below is performed, it is difficult to improve the crystallinity of the alloyed region.

As described above, by forming a metal oxide using the first film formation method before forming a metal oxide using the second film formation method, it is possible to prevent impurities from being mixed into the metal oxide layer. Furthermore, it is possible to prevent alloying with the layer on which the metal oxide is to be formed. This improves the initial characteristics and reliability of the transistor. Furthermore, it is possible to further increase the crystallinity of the metal oxide used as the semiconductor layer.

Note that a mixed layer may be formed at the interface between the first layer and the second layer. The mixed layer contains the components contained in the first layer and the components contained in the second layer. For example, if gallium oxide is used for the first layer and a metal oxide containing indium is used for the second layer, the mixed layer contains gallium and indium. Furthermore, for example, if the indium content in the second layer is higher than the indium content in the first layer, the indium content in the mixed layer will be equal to or greater than the indium content in the first layer and equal to or less than the indium content in the second layer.

The ALD method is suitable as the first film formation method because it can reduce damage to the surface to be formed compared to the sputtering method. Furthermore, the ALD method is a film formation method with superior coverage compared to the sputtering method, and using the ALD method as the film formation method for the first layer can improve the coverage of the metal oxide. Therefore, the metal oxide can be well coated on steps, openings, and the like with high aspect ratios.

The first layer may be formed, for example, as a metal oxide with a microcrystalline or amorphous structure, which has lower crystallinity than a CAAC structure. By forming a highly crystalline second layer on the low-crystallinity first layer, or by applying heat treatment after forming the second layer, the crystallinity of the first layer may be increased, with the second layer acting as a nucleus. This may increase the crystallinity of the entire metal oxide layer, including the area near the interface with the surface on which it is formed.

The layer on which the film is formed is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Depending on the transistor structure, the film may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer on which the film is formed does not need to be crystalline. If the layer is crystalline, it preferably has a crystal structure with low lattice matching with the metal oxide in the metal oxide layer.

The first layer is preferably formed using the ALD method. Here, we will explain a method for forming In-M-Zn oxide as the first layer using the ALD method.

First, a source gas containing an indium-containing precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the surface to be formed. Next, an oxidizing agent is introduced into the reaction chamber as a reactant, and reacts with the adsorbed precursor, desorbing components other than indium while leaving indium adsorbed to the substrate, forming a layer in which indium and oxygen are combined.

Next, a source gas containing a precursor containing element M is introduced into the reaction chamber and adsorbed onto the layer of indium and oxygen. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer of element M and oxygen.

Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer of combined element M and oxygen. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacts with the adsorbed precursor, desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer of combined zinc and oxygen.

By repeating the above-described method, In-M-Zn oxide can be formed as a metal oxide on the layer to be formed using the ALD method.

When forming a metal oxide using the ALD method, ozone ( _O3 ), oxygen ( _O2 ), water ( _H2O ), etc. can be used as an oxidizing agent. By using ozone ( _O3 ), oxygen ( _O2 ), etc. that do not contain hydrogen as an oxidizing agent, the amount of hydrogen mixed into the metal oxide can be reduced.

In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the reaction chamber, and then discharge excess precursor and reaction products, etc. from the reaction chamber. In the above, it is also preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the reaction chamber, and then discharge excess reactant and reaction products, etc. from the reaction chamber.

Furthermore, unless otherwise specified, in this specification and elsewhere, when ozone, oxygen, or water is used as a reactant or oxidant, this is not limited to the gas or molecular state, but also includes the plasma state, radical state, and ion state.

The second layer is preferably formed using a sputtering method.

In-M-Zn oxide can be used as a target for sputtering. When forming metal oxide by sputtering, oxygen or a mixture of oxygen and a noble gas can be used as the sputtering gas. Furthermore, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film formed can be increased.

Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), the more crystalline the metal oxide may be formed.

When metal oxide is formed by sputtering, if the percentage of oxygen contained in the sputtering gas is more than 30% and less than 100%, preferably 70% to 100%, oxygen-excess metal oxide may be formed. A transistor using oxygen-excess metal oxide in the channel formation region can achieve relatively high reliability. However, one embodiment of the present invention is not limited to this. If the percentage of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%, oxygen-deficient metal oxide is formed. A transistor using oxygen-deficient metal oxide in the channel formation region can achieve relatively high field-effect mobility.

When forming metal oxide using a sputtering method, it is preferable to heat the substrate. Increasing the substrate temperature (stage temperature) during metal oxide formation may result in the formation of metal oxide with high crystallinity. When forming metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

By using the above manufacturing method, the thickness of the mixed layer formed at the interface between the layer on which the layer is formed and the metal oxide can be reduced, or the alloyed region formed at the interface between the layer on which the layer is formed and the metal oxide can be made thin enough to be difficult to observe. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

In some cases, the thickness of the alloyed region can be calculated by performing a line analysis of the composition of the region and its surroundings using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

For example, EDX line analysis is performed on the alloyed region and its surroundings, with the direction perpendicular to the surface on which the first layer is to be formed as the depth direction. Next, in the profile of quantitative values of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal that is the main component of the first layer but is not the main component of the layer that will become the surface on which the layer is to be formed (In if the first layer contains In) reaches half its maximum is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value of an element that is the main component of the layer that will become the surface on which the layer is to be formed but is not the main component of the first layer (e.g., Si) reaches half its maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface on which the layer is to be formed. From the above, the thickness of the alloyed region can be calculated.

When observing the thickness of the alloyed region of a metal oxide using EDX analysis, the thickness is, for example, 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

Furthermore, for example, in the case of performing SIMS analysis of a metal oxide formed on a silicon oxide film that is a surface to be formed, the depth at which the silicon concentration is 50% of the maximum concentration of the silicon oxide film is defined as the interface, and the distance between the interface and the depth at which the silicon concentration decreases to 1.0× ¹⁰ atoms/cm ^, preferably 5.0× ¹⁰ atoms/ ^cm , more preferably 1.0× ¹⁰ atoms/cm ^, is defined as the thickness t. The thickness t is preferably 3 nm or less, more preferably 2 nm or less.

By reducing the thickness of the alloyed region, the thickness t can be set within the above range.

Furthermore, by reducing the alloyed region, it becomes possible to form a CAAC structure near the surface on which the structure is to be formed. Here, "near the surface on which the structure is to be formed" refers to, for example, a region that is more than 0 nm and less than 3 nm, preferably more than 0 nm and less than 2 nm, and more preferably 1 nm or more and less than 2 nm, approximately perpendicular to the surface on which the metal oxide is to be formed.

In addition, the CAAC structure near the surface to be formed can sometimes be confirmed by observation using a TEM. For example, when observing a cross section of a metal oxide using a high-resolution TEM, bright spots arranged in layers parallel to the surface to be formed can be confirmed near the surface to be formed.

Furthermore, the metal oxide used as the semiconductor layer can have a three-layer structure consisting of a first layer, a second layer on the first layer, and a third layer on the second layer.

When the metal oxide has a three-layer structure, the metal oxide can be produced by forming a first layer on the surface to be formed using a first film formation method, then forming a second layer using a second film formation method, and finally forming a third layer using the first film formation method.

Even if the above metal oxide uses a composition for the first and third layers that makes it difficult to form a CAAC structure when formed as a single layer, crystal growth occurs using the second layer as a nucleus, allowing the entire metal oxide, including the first and third layers, to have a CAAC structure. Alternatively, the CAAC structure can be formed in the region spanning the second layer and regions including at least a portion of each of the first and third layers.

In particular, even when the first and third layers have a high In content, they can have suitable crystallinity for use as semiconductor layers in transistors. In metal oxides used as semiconductor layers, increasing the In content can improve the on-state characteristics of the transistor, while achieving improved reliability by using a highly crystalline CAAC structure.

Furthermore, it is preferable that the first and third layers use metal oxides with the same composition as the second layer. Using the same composition may make it easier for CAAC to form after heat treatment.

Because the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that is likely to impart crystallinity is not used as the film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the metal oxide can have both high crystallinity and high coverage throughout the entire layer.

Furthermore, by providing the first layer, the influence of the surface on which the second layer is formed is reduced, thereby increasing the crystallinity of the second layer and resulting in extremely excellent crystallinity. Therefore, even in the third layer, which is crystallized using the second layer as a nucleus or seed, a layer with extremely excellent crystallinity is formed.

When a metal oxide is used as the semiconductor layer of a transistor, the third layer, which is the uppermost layer of the metal oxide, may be in contact with the gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, it is possible to increase carrier mobility when the transistor is in the on state.

The first layer and the third layer each have high crystallinity, using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer may be increased by heat treatment during the deposition of the second layer or after the deposition of the third layer. The crystallinity of the third layer may be increased by heat treatment during the deposition of the third layer or after the deposition of the third layer. The heat treatment described above has the function of assisting in increasing crystallinity.

In this way, in the metal oxide manufacturing method, the second layer having a highly crystalline metal oxide (i.e., CAAC) serves as a nucleus or seed to increase the crystallinity of the upper and lower metal oxides (here, the first and third layers). This increases the crystallinity of the entire metal oxide. In other words, the second layer serves as a nucleus or seed to cause solid-phase growth of the upper and lower metal oxides, forming a highly crystalline metal oxide. The metal oxide formed using this film formation method, here a CAAC film, can be referred to as Axial Growth CAAC (AG CAAC).

In a metal oxide used as a semiconductor layer, it is preferable that a region having a CAAC structure be widely present throughout the entire layer. The region having a CAAC structure in the first layer is crystalline connected to a region having a CAAC structure in the second layer. The region having a CAAC structure in the third layer is crystalline connected to a region having a CAAC structure in the second layer. As a result, the boundary between the first layer and the second layer may not be observed. Also, the boundary between the second layer and the third layer may not be observed. Therefore, a metal oxide composed of the first layer, the second layer, and the third layer may be described as a single layer with no clearly observable interface. The metal oxide may be described as a single layer.

In each of the first to third layers, in the region having the CAAC structure, for example, cross-sectional observation using a high-resolution TEM confirms bright spots aligned parallel or approximately parallel to the surface on which the metal oxide is formed. Furthermore, it is preferable that the c-axis of the CAAC structure in each of the first to third layers is parallel or approximately parallel to the normal direction of the surface on which the metal oxide is formed.

In addition, parts of the first layer or third layer may not crystallize.

Furthermore, when the metal oxide has a three-layer structure, the metal oxide can also be produced by forming a first layer on the surface to be formed using a first film formation method, then forming a second layer using the first film formation method, and then forming a third layer using a second film formation method.

As mentioned above, using a metal oxide with a high In content in the semiconductor layer of a transistor can increase the field-effect mobility of the transistor. On the other hand, metal oxides with a high In content tend to have a cubic crystal structure. Therefore, by using a metal oxide with a high In content in the second layer that contacts the third layer, it is possible to form crystals that reflect the crystal orientation of the third layer.

Furthermore, it is preferable that the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. This allows the second layer to form crystals that reflect the orientation of the crystals of the third layer. In this case, for example, when observing a cross section of the metal oxide using a high-resolution TEM, bright spots arranged in layers parallel to the surface on which they are formed are observed in the second layer.

There are no particular restrictions on the crystal structure of the second layer, as long as the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. The crystal structure of the second layer may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

In the above structure, typically, the first layer is a layer containing gallium oxide or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition; the second layer is a layer containing indium oxide or a metal oxide containing a trace amount of the aforementioned element M; and the third layer is a layer containing a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. In this case, the first layer contains gallium. Furthermore, when the first layer contains a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition, the indium content in the first layer is lower than the gallium content. Furthermore, the indium content in the second layer is higher than the indium content in the third layer.

When the first layer and the second layer are formed using the first film formation method, it is preferable to form the first layer and the second layer successively without exposing them to the atmosphere. By forming the first layer and the second layer successively without exposing them to the atmosphere, productivity can be increased. Furthermore, impurities (typically moisture, etc.) that are introduced into the interface between the first layer and the second layer and its vicinity can be reduced.

Furthermore, one or more of the first to third layers can have multiple stacked layers with different compositions. For example, the first layer can be produced by forming a layer containing a metal oxide with a high Ga content using the first film formation method, and then forming a layer containing a metal oxide with a higher In content than the first layer using the first film formation method.

After forming a layer using the first film formation method, it is preferable to perform microwave plasma treatment.

In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Furthermore, microwave plasma processing refers to processing using, for example, a device with a power source that generates high-density plasma using microwaves. Microwave plasma processing can also be referred to as microwave-excited high-density plasma processing.

By performing microwave plasma treatment in an oxygen-containing atmosphere, the impurity concentration in the metal oxide can be reduced. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an oxygen-containing atmosphere, the present invention is not limited to this. For example, by performing microwave plasma treatment on an insulating film, more specifically, a silicon oxide film, provided near a metal oxide used as a semiconductor layer in an oxygen-containing atmosphere, the impurity concentration in the metal oxide can be reduced. Furthermore, the heat generated during microwave plasma treatment may increase the crystallinity of the metal oxide layer.

Microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, more preferably 50 Pa or higher and 700 Pa or lower, and even more preferably 100 Pa or higher and 400 Pa or lower. The treatment temperature is preferably room temperature (25°C) or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and can be 400°C or higher and 450°C or lower.

When performing microwave plasma treatment, it is preferable to heat the substrate. The heating temperature of the substrate is preferably from room temperature (25°C) to 750°C, more preferably from 300°C to 500°C, and even more preferably from 400°C to 450°C. By heating the substrate and performing microwave plasma treatment, it is possible to further reduce the impurity concentration in the metal oxide. Furthermore, by setting the temperature within the above range, deformation (distortion or warping) of the substrate can be extremely minimized, even when the substrate is heated and microwave plasma treatment is performed.

Microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In microwave plasma treatment using oxygen gas and argon gas, the main oxygen radicals can _take three states: triplet oxygen (O( ^3Pj )), singlet oxygen ( _O ( ^1D2 )), and oxygen ions ( _O2 ⁺ ). Note that oxygen ions act effectively in reducing the hydrogen concentration in metal oxides by microwave plasma treatment. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in the microwave plasma treatment. For example, under conditions of a low oxygen flow rate ratio and a low pressure, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize discharge, or that the metal oxide may be etched. Therefore, for example, the oxygen flow rate ratio ( _O2 /( _O2 +Ar)) in microwave plasma processing is preferably greater than 0% and less than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

The shorter the microwave plasma treatment time, the more oxidation of the conductive layer and the like can be suppressed. It also increases productivity. Therefore, for example, the microwave plasma treatment time is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

By performing microwave plasma treatment in an oxygen-containing atmosphere, oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and the oxygen radicals generated by converting the oxygen gas into plasma can act on the metal oxide. The action of plasma, microwaves, oxygen radicals, or the like can separate defects in the metal oxide where hydrogen has entered oxygen vacancies (hereinafter sometimes referred to as _VOH ) into oxygen vacancies and hydrogen, thereby removing the impurity hydrogen from the metal oxide. In this way, the _VOH contained in the metal oxide layer can be reduced. Furthermore, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, microwave plasma treatment can reduce impurities such as carbon and hydrogen. Furthermore, by supplying the oxygen radicals to the metal oxide, oxygen vacancies in the metal oxide layer can be further reduced.

Furthermore, microwave plasma treatment can improve the crystallinity of a layer formed using the first film formation method. Here, the principle by which microwave plasma treatment improves the crystallinity of a metal oxide will be explained. First, active species such as oxygen radicals excited by microwaves arrive at the metal oxide surface, and a substitution reaction occurs between the active species and oxygen in the metal oxide. At this time, nuclei or seeds are formed. Furthermore, lateral growth of the nuclei or seeds is induced. Note that it is preferable for the active species excited by microwaves to contain oxygen (typically oxygen ions), which is easily adsorbed to the sides of the nuclei or seeds, as this promotes the lateral growth. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, improving the crystallinity of the metal oxide.

On the other hand, a reaction occurs between some of the oxygen in the metal oxide that was present before the microwave plasma treatment and hydrogen in the metal oxide, in other words, the reaction "2H + O → H ₂ O↑" occurs, and the hydrogen can be removed as H ₂ O (also referred to as dehydration or dehydrogenation). Since H ₂ O is one of the factors that inhibit improvement of crystallinity, it is preferable to remove it from the metal oxide. By removing hydrogen in the metal oxide as H ₂ O and reducing the hydrogen concentration in the metal oxide, it is also possible to promote improvement of crystallinity. Note that the hydrogen concentration in the metal oxide can be further reduced by increasing the temperature during microwave plasma treatment.

Furthermore, after microwave plasma treatment, it is preferable to perform heat treatment immediately without exposing the substrate to the outside air. The temperature for the heat treatment is, for example, preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower. By setting the temperature within the above range, deformation (distortion or warping) of the substrate can be minimized even when performing the heat treatment.

In addition to microwave plasma treatment, crystallinity can also be improved by plasma treatment containing oxygen gas.

By increasing the crystallinity of the layer formed using the first film formation method, the crystallinity of the layer formed on top of that layer can be further increased. Therefore, the crystallinity of the entire metal oxide can be increased.

Oxygen supplied to metal oxides can take various forms, including oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). It is preferable that the oxygen injected into the metal oxide be in one or more of the above forms, with oxygen radicals being particularly preferred.

Furthermore, after forming the metal oxide, it is preferable to perform heat treatment. Heat treatment can increase the crystallinity of the metal oxide. The heat treatment referred to here is not limited to heat treatment. For example, heat applied during the manufacturing process can be replaced with the above heat treatment.

The heat treatment temperature can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. A typical temperature is 400°C ± 25°C (375°C to 425°C). The treatment time can be 10 hours or less, for example, 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that this heat treatment will repair atomic-level crystalline gaps in the CAAC structure of the second layer formed using the second film formation method with the third layer formed using the first film formation method.

There are no particular limitations on the heating device used for heat treatment; any device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element can be used. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

This heat treatment process may increase the crystallinity of the region having the CAAC structure in the third layer formed using the first film formation method. Furthermore, if this region is formed only below the third layer after film formation using the ALD method, this heat treatment process may cause this region to expand upward. In other words, this heat treatment may result in the formation of a region having the CAAC structure throughout the entire third layer.

Furthermore, it is preferable that the heat treatment step converts at least a portion of the first layer or second layer formed using the first film formation method into CAAC. It is expected that the CAAC conversion is more likely to occur when the mixed layer formed in the first layer or second layer during the formation of the layer formed using the second film formation method acts as a nucleus or seed. It is preferable that the region in the first layer or second layer that converts into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the surface on which it is formed.

Furthermore, because the CAAC conversion occurs from the top to the bottom of the first or second layer, it can be converted to CAAC up to the vicinity of the layer, regardless of the material or crystallinity of the layer on which it is formed. For example, even if the layer has an amorphous structure, the crystallinity of the first or second layer can be increased. Therefore, the method for manufacturing a metal oxide used as a semiconductor layer is particularly suitable when the layer on which it is formed has an amorphous structure.

As described above, by performing microwave plasma treatment and/or heat treatment, the crystallinity of the metal oxide as a whole can be increased. It also reduces impurities in the metal oxide. By performing crystal growth in a state where the impurity concentration in the metal oxide has been reduced, further improvement in crystallinity can be achieved.

By increasing the crystallinity of metal oxides, it is possible to suppress an increase in the electrical resistance of transistors that use metal oxides as semiconductor layers, or to improve the initial characteristics of the transistors (particularly the on-state current), thereby realizing transistors suitable for high-speed operation. It is also possible to improve the reliability of the transistors and increase their on-state current.

Note that either or both of the microwave plasma treatment and the heat treatment can be performed directly on the formed metal oxide, or can be performed after forming an insulating film or the like on the metal oxide.

It is preferable to perform a process to supply oxygen to the first layer or second layer before forming the first layer, or after forming the first layer or second layer using the first film formation method. This allows oxygen to be supplied to the metal oxide by heat or other factors applied after the process.

Examples of treatments for supplying oxygen include heat treatment in an oxygen-containing atmosphere or plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the first or second layer formed using the first film formation method by forming a metal oxide film in an oxygen-containing atmosphere by sputtering. The formed metal oxide film can be removed immediately or left as is. When the formed metal oxide film is left as is, the metal oxide film can be used as a layer (second or third layer) provided on the first or second layer. Note that the oxygen-containing atmosphere includes not only oxygen gas (O ₂ ) but also an atmosphere containing a gas of an oxygen-containing compound such as ozone (O ₃ ) or dinitrogen monoxide (N ₂ O). The substrate temperature during the plasma treatment is set to be from room temperature (25° C.) to 450° C.

The metal oxide formed by the above manufacturing method has high crystallinity throughout the entire layer. Therefore, in the metal oxide, the boundaries between the stacked films of the first to third layers may not be visible. In particular, after heat treatment, it may be difficult to identify the boundaries between the stacked films. The presence or absence of boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM or cross-sectional STEM (scanning transmission electron microscope), etc.

Furthermore, metal oxides having a CAAC structure formed using the two aforementioned film formation methods may have higher film relative permittivity, film density, and film hardness than metal oxides having a CAAC structure formed using a single film formation method.

By using a metal oxide having a CAAC structure formed using the two film formation methods described above in the channel formation region of a transistor, it is possible to realize a transistor with excellent characteristics (e.g., a transistor with a large on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also called f characteristics), a highly reliable transistor, etc.).

Furthermore, metal oxides can sometimes be formed by using the first film formation method and one or both of microwave plasma treatment and heat treatment. In other words, metal oxides can sometimes be formed without using the second film formation method. For example, after forming a first layer using the first film formation method, the crystallinity of the first layer can be increased by performing one or both of microwave plasma treatment and heat treatment. Therefore, the crystallinity of a second layer formed on the first layer using the first film formation method can be increased using the first layer as a nucleus or seed. Furthermore, after forming the second layer, the crystallinity of the metal oxide can be increased by performing one or both of microwave plasma treatment and heat treatment. Therefore, a CAAC structure can be formed in the metal oxide.

As described above, even in a manufacturing method that does not use the second film formation method, the first layer formed using the first film formation method can be used as a nucleus or seed to cause solid-phase growth of the upper metal oxide, forming a highly crystalline metal oxide. Metal oxides formed using such film formation methods can also be referred to as AG CAAC.

Note that when the metal oxide has a stacked structure of two or more layers, it can be produced by forming the metal oxide using a single film formation method. When the metal oxide has a two-layer structure consisting of a first layer and a second layer on the first layer, the metal oxide can be produced, for example, by forming the first layer and the second layer in this order using a sputtering method. Sputtering has a higher film formation rate than ALD, and therefore can improve productivity. For example, when the metal oxide has a three-layer structure consisting of a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer to the third layer can be produced using a sputtering method. Furthermore, portions of the first layer to the third layer can also be deposited using ALD. For example, one or both of the second layer and the third layer can be deposited using ALD.

[Metal oxide layer of transistor]
The metal oxide of this embodiment can be used as a semiconductor layer of a transistor, for example, as the semiconductor layer 112 of the transistor 120.

Metal oxides used as semiconductor layers of transistors preferably have a CAAC structure. In metal oxides with a CAAC structure, metal atoms in the crystalline portion are arranged in layers parallel or approximately parallel to the surface on which they are formed.

Metal oxides with a CAAC structure are presumed to exhibit current anisotropy. For example, in IGZO crystals, current flows more easily in the a-axis direction than in the c-axis direction. In other words, in metal oxides with a CAAC structure, current flows more easily in the horizontal direction than in the vertical direction.

In a semiconductor device according to one embodiment of the present invention, when a metal oxide having a CAAC structure is used for the semiconductor layer 112, metal atoms are arranged in a layered manner parallel to or approximately parallel to the surface on which the metal oxide is to be formed (e.g., the side surface of the insulating layer 108). It can also be expressed as the a-b plane of the CAAC structure being provided parallel to or approximately parallel to the surface on which the metal oxide is to be formed. With this structure, the a-b plane of the CAAC structure can be provided along the direction of current flow in the channel of the transistor. This allows the on-state current of the transistor to be increased.

When a metal oxide is used as the semiconductor layer of a transistor, the thickness of the metal oxide is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, even more preferably 5 nm to 100 nm, even more preferably 10 nm to 100 nm, even more preferably 10 nm to 70 nm, even more preferably 15 nm to 70 nm, even more preferably 15 nm to 50 nm, and even more preferably 20 nm to 50 nm. Furthermore, in transistors used in smaller semiconductor devices, the thickness of the metal oxide used as the semiconductor layer is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, even more preferably 5 nm to 12 nm, and even more preferably 5 nm to 10 nm. Furthermore, the average thickness of the metal oxide in the channel formation region of the transistor is particularly preferably 2 nm to 15 nm.

The first layer preferably has a thickness of, for example, 0.5 nm or more and 50 nm or less, more preferably 0.5 nm or more and 30 nm or less, even more preferably 0.5 nm or more and 20 nm or less, even more preferably 1 nm or more and 50 nm or less, even more preferably 1 nm or more and 30 nm or less, even more preferably 1 nm or more and 20 nm or less, and even more preferably 2 nm or more and 20 nm or less. Furthermore, the first layer preferably has a thickness of 0.5 nm or more and 3 nm or less.

Furthermore, the first layer preferably has a region with a film thickness of 0.1 nm or more and 3 nm or less, and more preferably has a region with a film thickness of 0.1 nm or more and 2 nm or less. Alternatively, it is more preferable that the first layer has a region with a film thickness of 0.5 nm or more and 3 nm or less, and even more preferable that the first layer has a region with a film thickness of 0.5 nm or more and 2 nm or less.

The second layer preferably has a thickness of, for example, 200 nm or less. Furthermore, if the second layer is layer-like, it preferably has a thickness of, for example, 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and more preferably 2 nm or more and 100 nm or less.

Alternatively, if the second layer can function as a crystal nucleus, the second layer may not exist in a layered structure, but may be a collection of island-like regions. In such cases, for example, the island-like regions of the second layer exist discretely.

For the preferred range of film thickness for the third layer, please refer to the explanation for the film thickness of the first layer.

[Impurities in metal oxides]
Here, the influence of each impurity in the metal oxide layer will be described.

If oxygen vacancies ( _VO ) and impurities are present in the channel formation region of a metal oxide used as a semiconductor layer of a transistor, the electrical characteristics of the transistor are likely to fluctuate, which may result in poor reliability. Therefore, in order to stabilize the electrical characteristics of an OS transistor, it is effective to reduce the impurity concentration in the metal oxide used as a semiconductor layer. Furthermore, in order to reduce the impurity concentration in the metal oxide used as a semiconductor layer, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities in the metal oxide used as a semiconductor layer include hydrogen, carbon, and nitrogen. Note that the impurities in the metal oxide refer to, for example, elements other than the main component constituting the metal oxide. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

When a metal oxide contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the metal oxide. Therefore, the carbon concentration in the channel formation region of the metal oxide obtained by SIMS is set to 1× ¹⁰ atoms/cm ^or less, preferably 5× ¹⁰ atoms/cm ^or less, more preferably 3× ¹⁰ atoms/cm ^or less, more preferably 1× ¹⁰ atoms/ ^cm or less, more preferably ³ × ¹⁰ atoms/cm or less, and even more preferably 1× ¹⁰ atoms/cm or ^less . The silicon concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁸ atoms/cm ³ or less, and even more preferably 1×10 ¹⁸ atoms/cm ³ or less.

Furthermore, when nitrogen is contained in a metal oxide, electrons serving as carriers are generated, the carrier concentration increases, and the metal oxide is likely to become n-type. As a result, a transistor using a nitrogen-containing metal oxide as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in a metal oxide, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the metal oxide obtained by SIMS is set to 1×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, more preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and even more preferably 5×10 ¹⁷ atoms/cm ³ or less.

Furthermore, hydrogen contained in the metal oxide may react with oxygen bonded to metal atoms to form water, thereby forming oxygen vacancies. Hydrogen entering the oxygen vacancies may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using a metal oxide containing hydrogen is likely to exhibit normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the metal oxide. Specifically, the hydrogen concentration in the channel formation region of the metal oxide obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 5×10 ¹⁹ atoms/cm ³ , more preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ , and even more preferably less than 1×10 ¹⁷ atoms/cm ³ .

Furthermore, when a metal oxide contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or alkaline earth metal as a semiconductor layer tends to have normally-on characteristics. Therefore, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the metal oxide obtained by SIMS is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

By using metal oxides with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be achieved.

The configuration described in this embodiment can be used in appropriate combination with the configurations described in other embodiments.

(Embodiment 3)
In this embodiment, a configuration example of a semiconductor device 900 using the semiconductor device 10 as a memory cell will be described. The semiconductor device 900 can function as a memory device.

Figure 11 shows a block diagram illustrating an example configuration of a semiconductor device 900. The semiconductor device 900 shown in Figure 11 has a driver circuit 910 and a memory array 920. The memory array 920 has a plurality of semiconductor devices 10 that function as memory cells. Figure 11 shows an example in which the memory array 920 has a plurality of semiconductor devices 10 arranged in a matrix of p rows and q columns (p and q are each an integer of 2 or greater). By arranging a plurality of semiconductor devices 10 in a matrix, a memory device with a large storage capacity can be realized.

In FIG. 11, the semiconductor device 10 in the first row and first column is indicated as semiconductor device 10[1,1], the semiconductor device 10 in the pth row and qth column is indicated as semiconductor device 10[p,q], the semiconductor device 10 in the pth row and first column is indicated as semiconductor device 10[p,1], the semiconductor device 10 in the first row and qth column is indicated as semiconductor device 10[1,q], and the semiconductor device 10 in the rth row and sth column (r is an integer of 1 to p inclusive indicating an arbitrary row, and s is an integer of 1 to q inclusive indicating an arbitrary column) is indicated as semiconductor device 10[r,s].

Note that rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction (direction along the X axis) is referred to as a "row" and the Y direction (direction along the Y axis) as a "column," but it is also possible to refer to the X direction as a "column" and the Y direction as a "row."

FIGS. 12A and 13A are block diagrams showing a portion of the memory array 920. FIGS. 12B and 13B are schematic perspective views showing a portion of the memory array 920. As shown in FIGS. 12A and 12B, multiple semiconductor devices 10 functioning as memory cells can be aligned in the row and column directions within the memory array 920. Also, as shown in FIGS. 13A and 13B, multiple semiconductor devices 10 functioning as memory cells can be staggered within the memory array 920.

The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

In the semiconductor device 900, each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal.

Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 can also be generated by control circuit 912.

The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

The peripheral circuit 911 is a circuit for writing and reading data to and from the memory array 920. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

The row decoder 941 and column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying the row to be accessed, and the column decoder 942 is a circuit for specifying the column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory array 920, reading data from the memory array 920, and retaining the read data.

The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory array 920. The data (Dout) read from the memory array 920 by the column driver 924 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. The output circuit 926 also has the function of outputting Dout externally from the semiconductor device 900. The data output from the output circuit 926 is the signal RDA.

PSW931 has the function of controlling the supply of VDD to the peripheral circuit 915. PSW932 has the function of controlling the supply of VHM to the row driver 923. Here, the high power supply potential of the semiconductor device 900 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to set the word line to a high level and is higher than VDD. The on/off of PSW931 is controlled by signal PON1, and the on/off of PSW932 is controlled by signal PON2. In FIG. 11, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but there can be multiple. In this case, a power switch can be provided for each power domain.

An example circuit configuration that can be applied to the memory cells of the semiconductor device 900 will be described using Figures 14A to 14G.

[DOSRAM]
14A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM).

Memory cell 951 has the same circuit configuration as semiconductor device 10. Therefore, semiconductor device 10 functions as DRAM or DOSRAM.

Memory cell 951 includes a transistor M1 and a capacitor CA. Note that a transistor having a front gate (sometimes simply referred to as a gate) and a back gate can be used as transistor M1. In this case, the back gate can be connected to a wiring that supplies a constant potential or a signal, or the front gate and back gate can be connected to each other.

The first terminal of transistor M1 is connected to the first terminal of capacitor CA, the second terminal of transistor M1 is connected to wiring BL, and the gate of transistor M1 is connected to wiring WL. The second terminal of capacitor CA is connected to wiring CAL.

The wiring BL functions as a bit line, and the wiring WL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

Data is written and read by applying a high-level potential to the wiring WL, turning on the transistor M1, and bringing the wiring BL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

Furthermore, the circuit configuration that can be applied to the memory cells of the semiconductor device 900 is not limited to the circuit configuration shown as memory cell 951.

Note that it is preferable to use an OS transistor as transistor M1. OS transistors have the characteristic of having an extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made extremely low. That is, written data can be held by transistor M1 for a long time, reducing the frequency of refreshing the memory cell. Alternatively, refreshing the memory cell can be made unnecessary. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in memory cell 951.

[NOSRAM]
14B shows an example circuit configuration of a two-transistor, one-capacitor gain cell memory cell. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WL functions as a word line. Wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of capacitance CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

Data is written by applying a high-level potential to the wiring WL, turning on transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and this potential is written to the first terminal of the capacitor CB and the gate of transistor M3. Then, a low-level potential is applied to the wiring WL, turning off transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of transistor M3.

Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate of transistor M3 and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held in the first terminal of capacitor CB (or the gate of transistor M3) can be read. In other words, the information written in this memory cell can be read from the potential held in the first terminal of capacitor CB (or the gate of transistor M3).

Furthermore, for example, it is possible to combine the wiring WBL and the wiring RBL into a single wiring BL. An example circuit configuration of such a memory cell is shown in Figure 14C. In memory cell 954, the wiring WBL and the wiring RBL of memory cell 953 are combined into a single wiring BL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BL. In other words, memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BL.

Memory cell 955 shown in Figure 14D is an example in which the capacitance CB and wiring CAL in memory cell 953 have been omitted. Furthermore, memory cell 956 shown in Figure 14E is an example in which the capacitance CB and wiring CAL in memory cell 954 have been omitted. This configuration allows for increased integration of the memory cells.

Note that it is preferable to use an OS transistor for at least transistor M2. In particular, it is preferable to use OS transistors for transistors M2 and M3.

OS transistors have an extremely low off-state current, which allows written data to be retained by transistor M2 for a long time, thereby reducing the frequency of refreshing the memory cell. Alternatively, refresh operations of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be retained in each of memory cells 953, 954, 955, and 956.

Memory cell 953, memory cell 954, memory cell 955, and memory cell 956, in which an OS transistor is used as transistor M2, are one embodiment of NOSRAM.

It should be noted that a Si transistor can be used as transistor M3. Si transistors can increase field-effect mobility and can also be used as p-channel transistors, allowing for greater freedom in circuit design.

Furthermore, when an OS transistor is used as transistor M3, the memory cell can be composed of only n-type transistors.

Figure 14F also shows a three-transistor, one-capacitor gain cell type memory cell 957. Memory cell 957 has transistors M4 to M6 and a capacitor CC. Memory cell 957 is also a form of NOSRAM.

The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BL, and the gate of transistor M4 is connected to wiring WL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BL, and the gate of transistor M6 is connected to wiring RWL.

The wiring BL functions as a bit line, the wiring WL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

Data is written by applying a high-level potential to the wiring WL, turning on transistor M4, and establishing electrical continuity between the wiring BL and the first terminal of the capacitor CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BL, and this potential is written to the first terminal of the capacitor CC and the gate of transistor M5. Then, a low-level potential is applied to the wiring WL, turning off transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of transistor M5.

Data is read by precharging the wiring BL to a predetermined potential, electrically floating the wiring BL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, the information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

Note that it is preferable to use an OS transistor for at least transistor M4.

Note that Si transistors can be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of the silicon used in the semiconductor layer.

Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be composed of only n-type transistors.

[OS-SRAM]
14G shows an example of a static random access memory (SRAM) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an oxide semiconductor SRAM (OS-SRAM). Note that a memory cell 958 shown in FIG. 14G is a memory cell of an SRAM capable of backing up data.

Memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

The first terminal of transistor M7 is connected to wiring BL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WL. The first terminal of transistor M8 is connected to wiring BLB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WL.

The second terminal of transistor MS1 is connected to the wiring VDL. The second terminal of transistor MS2 is connected to the wiring VDL. The second terminal of transistor MS3 is connected to the wiring GNDL. The second terminal of transistor MS4 is connected to the wiring GNDL.

The second terminal of transistor M9 is connected to the first terminal of capacitor CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2, and the gate of transistor M10 is connected to wiring BRL.

The second terminal of capacitor CD1 is connected to wiring GNDL, and the second terminal of capacitor CD2 is connected to wiring GNDL.

Wiring BL and wiring BLB function as bit lines, wiring WL functions as a word line, and wiring BRL is a wiring that controls the on/off states of transistors M9 and M10.

The wiring VDL is a wiring that supplies a high-level potential, and the wiring GNDL is a wiring that supplies a low-level potential.

Data is written by applying a high-level potential to the wiring WL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to the information to be recorded is applied to the wiring BL, and the potential is written to the second terminal of the transistor M10.

Meanwhile, since memory cell 958 forms an inverter loop using transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of transistor M8. Because transistor M8 is on, the potential applied to wiring BL, i.e., the inverted signal of the signal input to wiring BL, is output to wiring BLB. Because transistors M9 and M10 are on, the potentials of the second terminals of transistors M7 and M8 are held in the first terminals of capacitors CD2 and CD1, respectively. Subsequently, a low-level potential is applied to wiring WL and a low-level potential is applied to wiring BRL, turning off transistors M7 to M10, thereby holding the potentials of the first terminals of capacitors CD1 and CD2.

Data is read by precharging the wiring BL and wiring BLB to a predetermined potential, then applying a high-level potential to the wiring WL and a high-level potential to the wiring BRL. The potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BLB. The potential of the first terminal of the capacitor CD2 is also refreshed by the inverter loop of the memory cell 958 and output to the wiring BL. The potentials of the wiring BL and wiring BLB change from the precharged potentials to the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively, so the potential held in the memory cell can be read from the potential of the wiring BL or wiring BLB.

Note that it is preferable to use OS transistors as transistors M7 to M10. This allows written data to be held for a long time by transistors M7 to M10, thereby reducing the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

Note that Si transistors can be used as transistors MS1 to MS4.

The drive circuit 910 and memory array 920 of the semiconductor device 900 can be provided on the same plane. It is also preferable to provide the drive circuit 910 and memory array 920 in an overlapping manner, as shown in Figure 15A. By providing the drive circuit 910 and memory array 920 in an overlapping manner, the signal propagation distance can be shortened. It is also possible to provide multiple layers of memory arrays 920 on top of the drive circuit 910, as shown in Figure 15B.

Next, we will explain an example of a processing device that can be equipped with a semiconductor device such as the above-mentioned memory device.

Figure 16 shows a block diagram of the arithmetic unit 960. The arithmetic unit 960 shown in Figure 16 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic unit 960 can also be applied to processors such as a GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), or NPU (Neural Processing Unit), which have a larger number (tens to hundreds) of processor cores capable of parallel processing than a CPU.

The arithmetic device 960 shown in Figure 16 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and cache interface 989 may also be provided on separate chips.

The cache 999 is connected to the main memory provided on a separate chip via a cache interface 989. The cache interface 989 has the function of supplying a portion of the data held in the main memory to the cache 999. The cache interface 989 also has the function of outputting a portion of the data held in the cache 999 to the ALU 991 or register 996, etc. via the bus interface 998.

As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have the function of supplying data held in the memory array 920 to the cache 999. In this case, it is also preferable that a drive circuit 910 be included as part of the cache interface 989.

It is also possible to use only the memory array 920 as a cache without providing the cache 999.

The arithmetic device 960 shown in FIG. 16 is merely one example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 16 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The more cores there are, the better, and for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more cores are preferable. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, while the arithmetic unit 960 is executing a program, the interrupt controller 994 determines and processes interrupt requests from external input/output devices, peripheral circuits, etc. based on their priority, mask status, etc. The register controller 997 generates the address of the register 996 and performs read and write operations on the register 996 depending on the state of the arithmetic unit 960.

The timing controller 995 also generates signals that control the timing of the operations of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits mentioned above.

In the arithmetic unit 960 shown in FIG. 16, the register controller 997 selects the holding operation in the register 996 in accordance with instructions from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or capacitance. If holding data using flip-flops is selected, power is supplied to the memory cells in the register 996. If holding data using capacitance is selected, the data is rewritten to the capacitance, and the power supply to the memory cells in the register 996 can be stopped.

The memory array 920 and the computing device 960 can be provided overlapping each other. Figures 17A and 17B show perspective views of a semiconductor device 970A. The semiconductor device 970A has an element layer 930 on which a memory array is provided above the computing device 960. The element layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The computing device 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, Figure 17B shows the computing device 960 and element layer 930 separated.

By stacking the element layer 930 having the memory array and the computing device 960, the connection distance between them can be shortened. This increases the communication speed between them. In addition, the short connection distance reduces power consumption.

As a method for stacking the element layer 930 having a memory array and the arithmetic device 960, it is possible to use a method in which the element layer 930 having a memory array is stacked directly on the arithmetic device 960 (also known as monolithic stacking), or a method in which the arithmetic device 960 and the element layer 930 are formed on different substrates, the two substrates are bonded together, and the connection is made using through-vias or conductive film bonding technology (such as Cu-Cu bonding). The former method does not require consideration of misalignment during bonding, and therefore not only can the chip size be reduced, but manufacturing costs can also be reduced.

Here, the arithmetic device 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the element layer 930 can each be used as a cache. In this case, for example, memory array 920L1 can be used as an L1 cache (also called a level 1 cache), memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 920L3 has the largest capacity and is accessed least frequently. Furthermore, memory array 920L1 has the smallest capacity and is accessed most frequently.

Note that when the cache 999 provided in the arithmetic device 960 is used as an L1 cache, each memory array provided in the element layer 930 can be used as a lower-level cache or main memory. Main memory has a larger capacity than the cache and is accessed less frequently.

Also, as shown in FIG. 17B, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

Note that while three memory arrays functioning as caches are shown here, it is also possible to have one or two memory arrays, or even four or more.

When the memory array 920L1 is used as a cache, the drive circuit 910L1 can function as part of the cache interface 989. It is also possible to configure the drive circuit 910L1 to be connected to the cache interface 989. Similarly, the drive circuit 910L2 and the drive circuit 910L3 can also function as part of the cache interface 989 or be configured to be connected to it.

Whether the memory array 920 functions as a cache or as main memory is determined by the control circuit 912 of each drive circuit 910. Based on a signal supplied from the arithmetic device 960, the control circuit 912 can cause part of the memory array 920 of the semiconductor device 900 to function as RAM.

The semiconductor device 900 can cause part of the memory array 920 to function as a cache, and the other part to function as main memory. In other words, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.

It is also possible to provide an element layer 930 having one memory array 920 stacked on the computing device 960. Figure 18A shows a perspective view of the semiconductor device 970B.

In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for different functions. Figure 18A shows an example in which area L1 is used as an L1 cache, area L2 as an L2 cache, and area L3 as an L3 cache.

Furthermore, in semiconductor device 970B, the capacity of each of areas L1 to L3 can be changed depending on the situation. For example, if you want to increase the capacity of the L1 cache, you can achieve this by increasing the area of area L1. With this configuration, it is possible to improve the efficiency of calculation processing and increase processing speed.

It is also possible to stack multiple memory arrays. Figure 18B shows a perspective view of semiconductor device 970C.

Semiconductor device 970C has an element layer 930L1 having memory array 920L1 stacked on top of it, an element layer 930L2 having memory array 920L2 on top of that, and an element layer 930L3 having memory array 920L3 on top of that. Memory array 920L1, which is physically closest to the computing device 960, can be used as a higher-level cache, and memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory array can be increased, thereby further improving processing power.

This embodiment can be combined with other embodiments or examples as appropriate. Furthermore, in this specification, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

The configuration described in this embodiment can be used in appropriate combination with the configurations described in other embodiments.

(Fourth embodiment)
In this embodiment, an example of the applicability of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

Semiconductor devices such as computers use a variety of memory devices depending on the application. Figure 19 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices such as computers. In Figure 19, the conceptual diagram explaining the hierarchy of memory devices is represented by a triangle, with memory devices located higher in the triangle requiring faster operating speeds, and memory devices located lower in the triangle requiring larger memory capacities and higher recording densities.

In Figure 19, from the top layer of the triangle, there are memories integrated as registers into the CPU, GPU, and NPU processing units, cache memory (sometimes simply referred to as cache, and typically L1, L2, and L3 caches), main memory such as DRAM, and storage memory such as 3D NAND and hard disks (also known as HDDs: hard disk drives).

Memory integrated as registers into arithmetic processing units such as CPUs, GPUs, and NPUs is used for temporary storage of calculation results, and is therefore frequently accessed by the arithmetic processing unit. Therefore, fast operating speeds are required rather than large storage capacities. Registers also have the function of storing setting information for the arithmetic processing unit.

Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, it is possible to increase the speed of access to the data. Cache memory requires less storage capacity than DRAM, but is required to have a faster operating speed than DRAM. Data rewritten in cache memory is duplicated and supplied to DRAM. Note that while Figure 19 only shows up to the L3 cache, the cache memory is not limited to this. For example, an OS memory according to one aspect of the present invention is also suitable for the LLC (Last Level cache) or FLC (Final Level cache), which are the lowest level caches.

DRAM has the function of storing programs, data, etc. read from 3D NAND.

3D NAND has the ability to store data that requires long-term storage, various programs used in computing devices (for example, artificial neural network models), and more. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speeds.

Hard disks have large storage capacity and are non-volatile. Alternatively, solid-state drives (SSDs) can be used instead of hard disks.

The OS memory according to one embodiment of the present invention is capable of long-term data retention. Therefore, it is suitable for the Target 1 area shown in Figure 19. Note that, as indicated by the diagonal hatching in Figure 19, Target 1 also includes part of the cache (L1, L2, L3) and part of the 3D NAND. In other words, Target 1 includes the boundary area between the DRAM and 3D NAND, and the boundary area between the DRAM and the cache (L1, L2, L3). Furthermore, because the OS memory according to one embodiment of the present invention has a high operating speed, it can achieve excellent write and read operations. Therefore, it can also be used for the Target 2 area shown in Figure 19.

For example, it is preferable to replace the DRAM shown in FIG. 19 with an OS memory according to one embodiment of the present invention. Here, DRAM requires refresh operations and is a destructive readout storage device, so it consumes more power than other storage devices. Therefore, a configuration that does not use DRAM can reduce power consumption. This configuration can reduce power consumption to one-hundredth or even one-thousandth of that of a configuration that uses DRAM. Therefore, by deploying information processing devices, including supercomputers (also called high performance computers (HPCs)), computers, servers, and the like, that employ such a configuration worldwide, global warming can be mitigated.

In this way, the OS memory according to one aspect of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs, to memories in the boundary area between DRAM and 3D NAND.

The configuration described in this embodiment can be used in appropriate combination with the configurations described in other embodiments.

Fifth Embodiment
In this embodiment, an application example of a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). The electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device according to one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[Electronic Components]
FIG. 20A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 20A has semiconductor device 710 inside mold 711. FIG. 20A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 is configured with multiple memory cell arrays stacked on top of each other. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stack, it is possible to achieve a so-called on-chip memory configuration, in which the memory is formed directly on the processor. The on-chip memory configuration enables faster operation of the interface between the processor and the memory.

The semiconductor device 900 according to one embodiment of the present invention or the like can be used as the semiconductor device 710. Therefore, the driver circuit 910 can be used as the driver circuit layer 715. The memory array 920 can be used as the memory layer 716. The semiconductor device 970A, the semiconductor device 970B, the semiconductor device 970C, or the like can be used as the semiconductor device 710.

Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also known as memory bandwidth).

Furthermore, it is preferable that the multiple memory cell arrays included in the memory layer 716 are formed using OS transistors and that the multiple memory cell arrays are monolithically stacked. By configuring the multiple memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to achieve a monolithic stack configuration than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stack configuration.

The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

Next, Figure 20B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.

Electronic component 730 shows an example in which semiconductor device 710 is used as a high bandwidth memory (HBM). Semiconductor device 735 can also be used in integrated circuits such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Processing Unit), or FPGA (Field Programmable Gate Array).

The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

The interposer 731 has multiple wiring lines and functions to connect multiple integrated circuits with different terminal pitches. The multiple wiring lines are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and package substrate 732 are connected using these through electrodes. In addition, with silicon interposers, TSVs can also be used as through electrodes.

HBM requires the connection of many wires to achieve a wide memory bandwidth. For this reason, the interposer on which the HBM is mounted must have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is less likely. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. It is particularly preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, space is required to accommodate the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the terminal pitch becomes an issue, and it may become difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. It is also possible to create a composite structure that combines a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

It is also possible to provide a heat sink (heat sink) overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

In order to mount the electronic component 730 on another substrate, electrodes 733 can also be provided on the bottom of the package substrate 732. Figure 20B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. The electrodes 733 can also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[Large computer]
21A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 is sometimes called a supercomputer.

Figure 21B shows a perspective view of an example of a computer 5620. The computer 5620 is mounted on a motherboard 5630. The motherboard 5630 has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

Figure 21C shows an example of a PC card 5621. PC card 5621 is a processing board equipped with, for example, a CPU, GPU, storage device, etc. PC card 5621 has board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on board 5622. Note that Figure 21C also shows components other than electronic components 5626, 5627, and 5628.

The connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. The connection terminal 5629 may conform to, for example, PCIe.

Connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to PC card 5621, inputting signals, etc. They can also be, for example, interfaces for outputting signals calculated by PC card 5621. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Also, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).

The electronic component 5626 has terminals (not shown) for inputting and outputting signals, and the electronic component 5626 can be connected to the board 5622 by inserting these terminals into sockets (not shown) provided on the board 5622.

Electronic component 5627 and electronic component 5628 have multiple terminals, and can be mounted to wiring on board 5622 by, for example, reflow soldering. Examples of electronic component 5627 include FPGAs, GPUs, and CPUs. Electronic component 5627 can be, for example, electronic component 730. Electronic component 5628 can be, for example, a memory device. Electronic component 5628 can be, for example, electronic component 700.

The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, artificial intelligence learning and inference.

[Space equipment]
The semiconductor device according to one embodiment of the present invention is suitable for space equipment.

A semiconductor device according to one embodiment of the present invention for use in space equipment preferably includes an OS transistor. OS transistors exhibit small changes in electrical characteristics due to radiation exposure. That is, they have high radiation resistance and are therefore suitable for environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used as transistors constituting semiconductor devices installed in space shuttles, artificial satellites, or space probes. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, for example, and the outer space described in this specification includes one or more of the thermosphere, mesosphere, and stratosphere.

Figure 22A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 22A also shows a planet 6804 in space.

Although not shown in FIG. 22A, the secondary battery 6805 can also be provided with a battery management system (also referred to as BMS) or a battery control circuit. Using an OS transistor in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in space.

In addition, outer space is an environment with radiation levels more than 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

When sunlight is irradiated onto the solar panel 6802, the power required for the satellite 6800 to operate is generated. However, for example, in situations where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is low, the amount of power generated is small. Therefore, there is a possibility that the power required for the satellite 6800 to operate will not be generated. In order to operate the satellite 6800 even in situations where the amount of power generated is low, it is recommended that a secondary battery 6805 be provided on the satellite 6800. Note that the solar panel is sometimes called a solar cell module.

Satellite 6800 can generate a signal. The signal is transmitted via antenna 6803, and can be received, for example, by a receiver located on the ground or by another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be determined. As described above, satellite 6800 can constitute a satellite positioning system.

The control device 6807 also has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The electrical characteristics of an OS transistor change less when exposed to radiation than those of a Si transistor. In other words, an OS transistor is highly reliable and suitable even in an environment where radiation may be incident.

Furthermore, the artificial satellite 6800 can be configured to include a sensor. For example, by configuring the artificial satellite 6800 with a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground. Or, by configuring the artificial satellite 6800 with a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an Earth observation satellite.

Note that in this embodiment, an artificial satellite is used as an example of space equipment; however, the present invention is not limited thereto. For example, a semiconductor device according to one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, or a space probe.

As explained above, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance compared to Si transistors.

[Data Center]
A semiconductor device according to one embodiment of the present invention is suitable for a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for maintaining the data, and ensuring cooling equipment required for maintaining the data.

By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, the power supply for storing data, and the cooling equipment. This allows for space savings in the data center.

Furthermore, the semiconductor device according to one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. This reduces adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using a semiconductor device according to one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. This improves the reliability of the data center.

Figure 22B shows a storage system applicable to a data center. The storage system 6000 shown in Figure 22B has multiple servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has multiple storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 can be connected to each other via a network.

Storage 6003 uses flash memory to reduce data access speed, i.e., the time required to store and output data, but this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the slow access speed of storage 6003, storage systems typically provide cache memory within the storage to reduce the time required to store and output data.

The aforementioned cache memory is used within the storage control circuit 6002 and storage 6003. Data exchanged between the host 6001 and storage 6003 is stored in the cache memory within the storage control circuit 6002 and storage 6003, and then output to the host 6001 or storage 6003.

By using OS transistors as transistors for storing data in the cache memory and maintaining a potential corresponding to the data, the frequency of refreshes can be reduced, and power consumption can be reduced. Furthermore, by stacking the memory cell array, miniaturization is possible.

Note that by applying a semiconductor device according to one embodiment of the present invention to one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers, it is expected that power consumption can be reduced. Therefore, while energy demand is expected to increase with the improvement in performance or integration of semiconductor devices, the use of a semiconductor device according to one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO ₂ ). Furthermore, the semiconductor device according to one embodiment of the present invention is effective as a countermeasure against global warming due to its low power consumption.

The configuration described in this embodiment can be used in appropriate combination with the configurations described in other embodiments.

10: semiconductor device, 101: insulating layer, 102: conductive layer, 103: insulating layer, 104: opening, 105: conductive layer, 106: insulating layer, 107: conductive layer, 108: insulating layer, 109: conductive layer, 110: capacitance element, 111: opening, 112: semiconductor layer, 113: insulating layer, 114: conductive layer, 115: insulating layer, 120: transistor, 121: end, 122: region, 151: length, 152: length, 700: electronic part 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit 915: Peripheral circuit, 920: Memory array, 923: Row driver, 924: Column driver, 925: Input circuit, 926: Output circuit, 927: Sense amplifier, 928: Voltage generation circuit, 930: Element layer, 931: PSW, 932: PSW, 941: Row decoder, 942: Column decoder, 951: Memory cell, 953: Memory cell, 954: Memory cell, 955: Memory cell, 956: Memory cell, 957: Memory cell, 958: Memory cell, 960: Arithmetic unit, 989: Cache interface, 990: Substrate, 991: ALU, 992: ALU controller, 993: Instruction decoder, 994: Interrupt controller, 995: Timing controller, 996: Register, 997: Register controller, 998: Bus interface, 999: Cache

Claims (9)

A semiconductor device having a first capacitance element and a first transistor,
a first insulating layer provided on the first conductive layer;
a first opening that penetrates the first insulating layer and reaches the first conductive layer;
a second conductive layer having a region overlapping the first conductive layer and a region overlapping a side surface of the first insulating layer in the first opening;
a second insulating layer provided on the second conductive layer;
a third conductive layer having a region overlapping the second conductive layer via a portion of the second insulating layer and a region overlapping a side surface of the first insulating layer via another portion of the second insulating layer;
a third insulating layer provided on the third conductive layer;
a fourth conductive layer provided on the third insulating layer;
a second opening that penetrates the third insulating layer and reaches the third conductive layer;
a semiconductor layer having a region electrically connected to the third conductive layer, a region electrically connected to the fourth conductive layer, and a channel formation region along a side surface of the third insulating layer in the second opening;
a fourth insulating layer provided on the semiconductor layer;
a fifth conductive layer having a region overlapping with a channel formation region of the first transistor via a part of the fourth insulating layer;
The semiconductor device has a length in a first direction different from a length in a second direction perpendicular to the first direction when viewed from above. In claim 1,
the second conductive layer functions as one electrode of the first capacitance element;
the third conductive layer functions as the other electrode of the first capacitance element,
the third conductive layer functions as one of a source electrode or a drain electrode of the first transistor;
The fourth conductive layer functions as the other of the source electrode and the drain electrode of the first transistor. In claim 1 or claim 2,
The length in the second direction is between two and five times the length in the first direction. In claim 1 or claim 2,
The semiconductor device has a region where the first capacitive element and the first transistor overlap each other in a plan view. In claim 1 or claim 2,
The semiconductor device, wherein the semiconductor layer includes an oxide semiconductor. A semiconductor device having a first capacitance element, a first transistor, and a second transistor,
a first insulating layer provided on the first conductive layer;
a second conductive layer having a region overlapping the first conductive layer and a region overlapping a side surface of the first insulating layer;
a second insulating layer provided on the second conductive layer;
a third conductive layer having a region overlapping the second conductive layer via a portion of the second insulating layer;
a third insulating layer provided on the third conductive layer;
a fourth conductive layer provided on the third insulating layer;
a semiconductor layer having a region electrically connected to the third conductive layer, a region electrically connected to the fourth conductive layer, a channel formation region of the first transistor, and a channel formation region of the second transistor;
a fourth insulating layer provided on the semiconductor layer;
a fifth conductive layer having a region overlapping with a channel formation region of the first transistor via a portion of the fourth insulating layer and a channel formation region of the second transistor via another portion of the fourth insulating layer;
A semiconductor device having: In claim 6,
the second conductive layer functions as one electrode of the first capacitance element;
the third conductive layer functions as the other electrode of the first capacitance element,
the third conductive layer functions as one of a source electrode and a drain electrode of each of the first transistor and the second transistor;
The fourth conductive layer functions as the other of the source electrode and the drain electrode of each of the first transistor and the second transistor. In claim 6 or claim 7,
The first capacitive element has a first region that overlaps with the first transistor in a plan view and a second region that overlaps with the second transistor in a plan view. In claim 6 or claim 7,
The semiconductor device, wherein the semiconductor layer includes an oxide semiconductor.