WO2024185436A1 - Surface-emitting laser - Google Patents

Abstract

A surface-emitting laser according to one embodiment of the present disclosure comprises a first DBR layer, a second DBR layer, an active layer, a first spacer layer, a second spacer layer, a tunnel junction layer, a first electrode layer, and a second electrode layer. The first electrode layer is electrically connected to the first spacer layer without the intervention of the first DBR layer. The second electrode layer is electrically connected to the second spacer layer without the intervention of the second DBR layer. The first spacer layer has a flat exposed surface in a region that is not oriented toward the tunnel junction layer. The first electrode layer is formed so as to be in contact with a portion of the first spacer layer that is deeper than the exposed surface.

Description

Surface-emitting laser

This disclosure relates to surface-emitting lasers.

　 Surface-emitting lasers are disclosed, for example, in Patent Documents 1 and 2.

JP 2007-315883 A Japanese Patent Application Publication No. 9-27671

In order to emit laser light into space, it is necessary to take into consideration sufficient safety for the retina of the eye (eye safety). For this reason, eye-safe surface-emitting lasers have been developed in recent years. Eye-safe surface-emitting lasers are required to be highly efficient and have low power consumption. It is desirable to provide a surface-emitting laser that can achieve both high efficiency and low voltage.

The surface-emitting laser according to an embodiment of the present disclosure includes a first DBR layer, a second DBR layer, an active layer, a first spacer layer, a second spacer layer, a tunnel junction layer, a first electrode layer, and a second electrode layer. The active layer is disposed between the first DBR layer and the second DBR layer. The first spacer layer is disposed between the active layer and the first DBR layer. The second spacer layer is disposed between the active layer and the second DBR layer. The tunnel junction layer is disposed between the active layer and the second DBR layer. The first electrode layer is electrically connected to the first spacer layer without the first DBR layer. The second electrode layer is electrically connected to the second spacer layer without the second DBR layer. The first spacer layer has a flat exposed surface in a region not facing the tunnel junction layer. The first electrode layer is formed so as to contact a portion of the first spacer layer that is deeper than the exposed surface.

FIG. 1 is a diagram illustrating an example of a cross-sectional configuration of a surface-emitting laser according to a first embodiment of the present disclosure. FIG. 2 is a diagram showing an example of the top configuration of the surface emitting laser of FIG. 3A to 3C are diagrams showing an example of a method for manufacturing the surface emitting laser of FIG. FIG. 4 is a diagram showing an example of a manufacturing process subsequent to FIG. FIG. 5 is a diagram showing an example of a manufacturing process subsequent to FIG. FIG. 6 is a diagram showing an example of a manufacturing process subsequent to FIG. FIG. 7 is a diagram showing an example of a manufacturing process subsequent to FIG. FIG. 8 is a diagram showing an example of a manufacturing process following FIG. FIG. 9 is a diagram showing an example of a manufacturing process subsequent to FIG. FIG. 10 is a diagram showing an example of a manufacturing process subsequent to FIG. FIG. 11 is a diagram showing an example of a manufacturing process subsequent to FIG. FIG. 12 is a diagram illustrating an example of a cross-sectional configuration of a surface-emitting laser according to a comparative example. FIG. 13 is a diagram illustrating an example of the relationship between the carrier concentration and the sheet resistance. FIG. 14 is a diagram showing an example of the IV characteristics of the surface emitting lasers according to the example and the comparative example. FIG. 15 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 16 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 17 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 18 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 19 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 20 is a diagram showing an example of the top configuration of the surface emitting laser of FIG. FIG. 21 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 22 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 23 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 24 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 25 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 26 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 27 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser in FIG. FIG. 28 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG. FIG. 29 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser in FIG. FIG. 30 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser in FIG. FIG. 31 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser in FIG. FIG. 32 is a diagram illustrating an example of a cross-sectional configuration of a surface-emitting laser according to the second embodiment of the present disclosure. FIG. 33 is a diagram showing an example of the top configuration of the surface emitting laser of FIG. FIG. 34 is a diagram showing a modification of the cross-sectional structure of the surface-emitting laser of FIG.

Hereinafter, the embodiment of the present disclosure will be described in detail with reference to the drawings. The following description is one specific example of the present disclosure, and the present disclosure is not limited to the following embodiment. Furthermore, the present disclosure is not limited to the arrangement, dimensions, and dimensional ratios of each component shown in each drawing. The description will be given in the following order.
1. First embodiment: FIGS. 1 to 14
1. Example in which the lower electrode is embedded in the semiconductor layer 2. Modifications of the first embodiment Modification A: Example in which the lower electrode is composed of a metal layer and a plating layer (FIG. 15)
Modification B: Example in which the bottom electrode is composed of a diffusion metal region and an alloy metal layer (Figure 16)
Modification C: An example in which the lower electrode is composed of a diffusion metal region, an alloy metal layer, and a metal layer (FIG. 17)
Modification D: An example in which a lower electrode is formed at the interface between the active layer and the semiconductor layer in contact with the active layer (FIG. 18)
Modification E: Example in which a ring-shaped lower electrode is provided around the mesa (FIGS. 19 and 20)
Modification F: Example in which the cross-sectional shape of the buried portion of the lower electrode is forward tapered (FIG. 21)
Modification G: Example in which the buried portion of the lower electrode is made pyramidal (FIG. 22)
Modification H: Example of forming a tunnel junction using ion implantation (FIG. 23)
Modification I: Example in which a transparent conductive layer is provided between the semiconductor layer and the upper DBR layer (FIG. 24)
Modification J: Example in which the lower DBR layer is made of a dielectric material (FIG. 25)
Modification K: An example in which the lower mirror is composed of a dielectric DBR layer and a reflective metal layer (Figure 26)
Modification L: Example in which the lower DBR layer is made of a GaAs-based semiconductor (FIG. 27)
Modification M: In a back-emitting surface-emitting laser,
An example of embedding the bottom electrode in the semiconductor layer (Figure 28)
Modification N: In a back-emitting surface-emitting laser,
Example of lower DBR layer made of dielectric material (Figure 29)
Modification O: In a back-emitting surface-emitting laser,
Example of lower DBR layer made of GaAs-based semiconductor (Figure 30)
Modification P: In a back-emitting surface-emitting laser,
An example in which the upper mirror is composed of a dielectric DBR layer and a reflective metal layer (Figure 31)
3. Second embodiment: Example in which a lower electrode is provided on the bottom surface of a groove (FIGS. 32 and 33)
4. Modification of the Second Embodiment Modification Q: In a back-emitting surface-emitting laser,
An example of embedding the bottom electrode in the semiconductor layer (Figure 34)

1. First embodiment
[composition]
A surface-emitting laser 1 according to a first embodiment of the present disclosure will be described. Fig. 1 illustrates an example of a cross-sectional configuration of the surface-emitting laser 1. Fig. 2 illustrates an example of a top surface configuration of the surface-emitting laser 1.

The surface-emitting laser 1 has a vertical resonator structure 20 on a substrate 10. The substrate 10 is a crystal growth substrate used when epitaxially growing the vertical resonator structure 20. In the surface-emitting laser 1, the substrate 10 can be omitted.

The vertical resonator structure 20 includes a semiconductor DBR (distributed Bragg reflector) layer 21, a dielectric DBR layer 26, and a cavity layer disposed between the semiconductor DBR layer 21 and the dielectric DBR layer 26. The cavity layer is designed according to the oscillation wavelength λ ₀ and the intended use. The cavity layer includes, for example, an active layer 23, a spacer layer 22 disposed between the active layer 23 and the semiconductor DBR layer 21, spacer layers 24 and 25 disposed between the active layer 23 and the dielectric DBR layer 26, and a tunnel junction layer disposed between the active layer 23 and the dielectric DBR layer 26.

The spacer layer 24 is disposed on the active layer 23 side, and the spacer layer 25 is disposed on the dielectric DBR layer 26 side. The tunnel junction layer is surrounded by the spacer layers 24 and 25, for example, as shown in FIG. 1. The spacer layer 24 contacts the bottom surface of the tunnel junction layer, and the spacer layer 25 contacts the top surface and side surface of the tunnel junction layer. The tunnel junction layer is composed of a high-concentration p-layer 28 and a high-concentration n-layer 29 stacked on top of each other, for example, as shown in FIG. 1. The spacer layer 24 contacts the bottom surface of the high-concentration p-layer 28, and the spacer layer 25 contacts the side surface of the high-concentration p-layer 28. The high-concentration p-layer 28 contacts the bottom surface of the high-concentration n-layer 29, and the spacer layer 25 contacts the top surface and side surface of the high-concentration n-layer 29.

The tunnel junction layer forms a current confinement structure due to the tunnel junction. In the tunnel junction layer, at the boundary between the high-concentration p layer 28 and the high-concentration n layer 29, the conduction band of the high-concentration p layer 28 and the valence band of the high-concentration n layer 29 are close to each other, forming a tunnel junction between the high-concentration p layer 28 and the high-concentration n layer 29. As a result, in the tunnel junction layer, a current flows from the high-concentration n layer 29 to the high-concentration p layer 28.

The surface-emitting laser 1 is configured to emit laser light L with an oscillation wavelength λ ₀ from the dielectric DBR layer 26 side. Specifically, in the vertical resonator structure 20, the number of pairs and reflectance of the reflecting mirror on the semiconductor DBR layer 21 side and the number of pairs and reflectance of the reflecting mirror on the dielectric DBR layer 26 side are configured to emit laser light L with an oscillation wavelength λ ₀ from the dielectric DBR layer 26 side. Therefore, the surface-emitting laser 1 is a top-emitting laser that emits laser light L from a light emission surface 1S provided on the dielectric DBR layer 26 side.

In the vertical resonator structure 20, at least the active layer 23, the spacer layer 24, the tunnel junction layer, the spacer layer 25, and the dielectric DBR layer 26 form a columnar mesa portion 20A extending in the normal direction of the substrate 10. FIG. 1 shows an example in which the mesa portion 20A is formed by a part of the spacer layer 22, the active layer 23, the spacer layer 24, the tunnel junction layer, the spacer layer 25, and the dielectric DBR layer 26. The mesa portion 20A is, for example, circular in plan view. The semiconductor DBR layer 21 is provided in a region on the substrate 10 side in relation to the position of the mesa portion 20A.

The tunnel junction layer is provided in the center of the mesa portion 20A in a planar view. The tunnel junction layer has, for example, a circular shape in a planar view. The tunnel junction layer is provided on the opposite side to the substrate 10 (i.e., the light emission surface 1S side) in terms of its positional relationship with the active layer 23. A convex portion having a shape corresponding to the shape of the tunnel junction layer is formed on the upper surface of the spacer layer 25 at a location facing the tunnel junction layer. This convex portion is provided in the center of the mesa portion 20A in a planar view, and has, for example, a circular shape in a planar view.

The dielectric DBR layer 26 is in contact with the upper surface of the spacer layer 25, for example, with the upper surface of the convex portion. Note that FIG. 1 shows an example in which the dielectric DBR layer 26 is in contact with not only the upper surface of the convex portion, but also the side and base portions of the convex portion on the upper surface of the spacer layer 25. Note that the portions of the dielectric DBR layer 26 that are in contact with the side and base portions of the convex portion do not contribute to laser oscillation.

The surface-emitting laser 1 further includes a contact layer 27 and an electrode layer 32 as an upper electrode on the upper part of the mesa portion 20A, as shown in, for example, FIG. 1 and FIG. 2. The contact layer 27 is in contact with the spacer layer 25 and the electrode layer 32. As shown in, for example, FIG. 1, the contact layer 27 is in contact with the base of the convex portion of the spacer layer 25, and has a ring shape surrounding the convex portion of the spacer layer 25 in a plan view. The contact layer 27 is a layer for making the spacer layer 25 and the electrode layer 32 in ohmic contact with each other. The electrode layer 32 is in contact with the contact layer 27, and is electrically connected to the spacer layer 25 via the contact layer 27 and further without via the dielectric DBR layer 26. As shown in, for example, FIG. 1 and FIG. 2, the electrode layer 32 has a ring shape surrounding the convex portion of the spacer layer 25 in a plan view.

The surface-emitting laser 1 further includes an electrode layer 31 as a lower electrode at a location corresponding to the base of the mesa portion 20A, as shown in FIG. 1, for example. At the location corresponding to the base of the mesa portion 20A, a part of the spacer layer 22 is exposed, as shown in FIG. 1 and FIG. 2, for example. Hereinafter, the part of the spacer layer 22 corresponding to the base of the mesa portion 20A is referred to as the exposed surface 22S. The exposed surface 22S is a flat surface. The exposed surface 22S is a flat surface parallel to the stacking surface of the semiconductor DBR layer 21, for example. The electrode layer 31 is formed so as to contact a part of the exposed surface 22S and also contact a part of the spacer layer 22 that is deeper than the exposed surface 22S. The spacer layer 22 has a recess 22A in the exposed surface 22S that is deep enough not to reach the semiconductor DBR layer 21. The electrode layer 31 is formed so as to fill the recess 22A, and contacts the spacer layer 22 on the inner surface of the recess 22A. The electrode layer 31 is electrically connected to the spacer layer 22 without passing through the semiconductor DBR layer 21. Therefore, in the surface-emitting laser 1, a current path formed by the electrode layer 31 and the electrode layer 32 (indicated by the dashed line in FIG. 1) is provided without passing through the semiconductor DBR layer 21 and the dielectric DBR layer 26.

Next, we will explain the materials that make up each component of the surface-emitting laser 1.

The substrate 10 is an n-type InP substrate. The n-type InP substrate contains n-type impurities such as silicon (Si).

The semiconductor DBR layer 21 is an undoped semiconductor DBR layer. The semiconductor DBR layer 21 is configured by alternately laminating low-refractive index semiconductor layers containing undoped InP and high-refractive index semiconductor layers containing undoped AlGaInAs. The optical thicknesses of the low-refractive index semiconductor layers and the high-refractive index semiconductor layers are each, for example, λ ₀ ×¼.

The spacer layers 22, 24, and 25 are made of an InP-based semiconductor. The spacer layer 22 is made of, for example, n-type InP. The n-type InP contains, for example, silicon (Si) as an n-type impurity. The spacer layer 24 is made of, for example, p-type InP. The p-type InP contains, for example, carbon (C), zinc (Zn), magnesium (Mg), beryllium (Be), etc. as a p-type impurity. The spacer layer 25 is made of, for example, n-type InP. The n-type InP contains, for example, silicon (Si) as an n-type impurity.

The dielectric DBR layer 26 is formed by alternately laminating low refractive index dielectric layers made of a first dielectric material and high refractive index dielectric layers made of a second dielectric material. The optical thicknesses of the low refractive index dielectric layers and the high refractive index dielectric layers are, for example, λ ₀ ×1/4. The low refractive index dielectric layers are made of, for example, SiO _2. The high refractive index dielectric layers are made of, for example, Ta ₂ O _5. The material of the dielectric DBR layer 26 is not limited to the above dielectric materials.

The contact layer 27 is made of, for example, n-type InGaAs containing a higher concentration of n-type impurities than the n-type impurity concentration contained in the spacer layer 25. The n-type InGaAs contains the same n-type impurities as the n-type impurities contained in the spacer layer 25. The electrode layer 31 has a structure in which Ti, Pt, and Au are stacked in this order from the inner surface side of the recess 22A of the spacer layer 22. Ti, Pt, and Au are formed by, for example, sputtering or vapor deposition. The electrode layer 32 has a structure in which, for example, Ti, Pt, and Au, or AuGe, Ni, and Au are stacked in this order from the contact layer 27 side. The material of the electrode layer 32 is not limited to the above materials.

The high-concentration p-layer 28 is made of p-type AlGaInAs containing a higher concentration of p-type impurities than the p-type impurity concentration contained in the spacer layer 24. The p-type AlGaInAs contains, as the p-type impurity, for example, the same impurity as the p-type impurity contained in the spacer layer 24. The high-concentration n-layer 29 is made of n-type InP containing, as the n-type impurity, a higher concentration of n-type impurities than the n-type impurity concentration contained in the spacer layer 25. The n-type InP contains, as the n-type impurity, for example, the same impurity as the n-type impurity contained in the spacer layer 25.

[Manufacturing method]
Next, a method for manufacturing the surface emitting laser 1 according to the present embodiment will be described.

To manufacture the surface emitting laser 1, a compound semiconductor is formed on a substrate 10 made of, for example, InP by epitaxial crystal growth such as MOCVD (Metal Organic Chemical Vapor Deposition). In this case, as the raw material of the compound semiconductor, for example, methyl-based organometallic gas such as trimethylaluminum (TMAl), trimethylgallium (TMGa), and trimethylindium (TMIn), phosphine (PH ₃ ) gas, and arsine (AsH ₃ ) gas are used, as the raw material of the donor impurity, for example, disilane (Si ₂ H ₆ ), and as the raw material of the acceptor impurity, for example, carbon tetrabromide (CBr ₄ ) is used.

First, the semiconductor DBR layer 21, spacer layer 22, active layer 23, spacer layer 24, high-concentration p-layer 28, and high-concentration n-layer 29 are formed on the substrate 10 by epitaxial crystal growth, such as MOCVD (Figure 3). Next, for example, a resist layer (not shown) having a circular shape in a planar view is formed, and then the high-concentration p-layer 28 and high-concentration n-layer 29 are selectively etched using this resist layer as a mask. This forms the high-concentration p-layer 28 and high-concentration n-layer 29 having a circular shape in a planar view (Figure 4). The resist layer is then removed.

Next, the spacer layer 25 and the contact layer 27 are formed on the surface including the surfaces of the circular high-concentration p-layer 28 and the high-concentration n-layer 29 by epitaxial crystal growth, such as MOCVD (Figure 5). At this time, in the spacer layer 25 and the contact layer 27, in the areas facing the circular high-concentration p-layer 28 and the high-concentration n-layer 29, a step structure portion having a shape imitating the circular high-concentration p-layer 28 and the high-concentration n-layer 29 is formed.

Next, for example, a circular resist layer (not shown) is formed to cover a predetermined area centered on the circular high-concentration p-layer 28 and high-concentration n-layer 29 in a plan view, and then the semiconductor layers such as the contact layer 27 are selectively etched using this resist layer as a mask, and the semiconductor layers are etched to a depth that reaches the spacer layer 22. At this time, it is preferable to use RIE (Reactive Ion Etching) using a Cl-based gas, for example. In this manner, a columnar mesa portion 20A is formed (Figure 6). At this time, the spacer layer 22 is exposed at the base of the mesa portion 20A. In other words, an exposed surface 22S is formed at the base of the mesa portion 20A. The resist layer is then removed.

Next, an electrode layer 32 is formed in contact with the upper surface of the mesa portion 20A (contact layer 27) (Figure 7). Next, for example, a resist layer (not shown) is formed that covers the electrode layer 32 and the mesa portion 20A and has openings only at predetermined locations on the exposed surface 22S, and then the spacer layer 22 is selectively etched using this resist layer as a mask, and the spacer layer 22 is etched to a depth that does not reach the semiconductor DBR layer 21. At this time, it is preferable to use RIE using, for example, a Cl-based gas. In this way, a recess 22A is formed in the exposed surface 22S (Figure 8). Thereafter, the resist layer is removed.

Next, the electrode layer 31 is formed so as to fill the recess 22A (Figure 9). As a result, the electrode layer 31 contacts a part of the exposed surface 22S, and also contacts a portion of the spacer layer 22 that is deeper than the exposed surface 22S (specifically, the inner surface of the recess 22A). Next, a resist layer (not shown) is formed on the upper surface of the mesa portion 20A, with an opening only in the portion surrounded by the electrode layer 32, and the contact layer 27 is selectively etched using this resist layer as a mask. In this way, the convex portion of the spacer layer 25 is exposed (Figure 10). The resist layer is then removed.

Then, for example, a vacuum deposition method is used to form the dielectric DBR layer 26 on the entire surface, including the surfaces of the convex portions, of the spacer layer 25 (FIG. 11). Next, the formed dielectric DBR layer 26 is selectively removed except for the areas surrounded by the electrode layer 32. In this manner, the surface-emitting laser 1 is manufactured.

[Action]
In the surface-emitting laser 1 having such a configuration, when a predetermined voltage is applied between the electrode layer 31 electrically connected to the spacer layer 22 and the electrode layer 32 electrically connected to the contact layer 27, a current confined by the tunnel junction layer formed by the high-concentration p layer 28 and the high-concentration n layer 29 is injected into the active layer 23, which causes light emission due to recombination of electrons and holes. At this time, the tunnel junction layer confines the light generated in the active layer 23 in the in-plane direction of the stacking. As a result, the vertical resonator structure 20 generates laser oscillation at an oscillation wavelength λ _0. Then, the light leaking from the dielectric DBR layer 26 becomes a beam-like laser light L and is output to the outside from the light emission surface 1S.

[effect]
Next, the effects of the surface emitting laser 1 according to the present embodiment will be described.

In order to emit laser light into space, it is necessary to consider sufficient safety for the retina of the eye (eye safety). For this reason, eye-safe surface-emitting lasers have been developed in recent years. Eye-safe surface-emitting lasers are required to be highly efficient and have low power consumption.

In contrast, in this embodiment, the spacer layer 22 disposed between the active layer 23 and the semiconductor DBR layer 21 has a flat exposed surface 22S in a region not facing the tunnel junction layer. The electrode layer 31 is formed so as to contact a portion of the spacer layer 22 that is deeper than the exposed surface 22S. As a result, the density of the lateral current flowing in the spacer layer 22 is reduced, and the operating voltage is also reduced, compared to, for example, the surface-emitting laser 100 according to the comparative example shown in FIG. 12, in which the electrode layer 131 is provided only on the exposed surface 22S.

For example, as shown in FIG. 13, the sheet resistance of the surface-emitting laser 1 according to the embodiment can be significantly reduced compared to the sheet resistance of the surface-emitting laser 100 according to the comparative example. As a result, for example, as shown in FIG. 14, the operating voltage of the surface-emitting laser 1 according to the embodiment can be significantly reduced (by about 0.2 V) compared to the operating voltage of the surface-emitting laser 100 according to the comparative example.

In addition, in this embodiment, the current path formed by the electrode layers 31 and 32 is provided without passing through the semiconductor DBR layer 21 and the dielectric DBR layer 26, so there is no need to configure both the semiconductor DBR layer 21 and the dielectric DBR layer 26 from impurity-doped semiconductors. As a result, it is possible to reduce losses due to free carrier absorption in the semiconductor DBR layer 21 and the dielectric DBR layer 26. In addition, the impurity concentration of the spacer layer 22 itself can also be reduced, so that in this respect too, losses due to free carrier absorption in the spacer layer 22 can be reduced. Therefore, high efficiency and low voltage can be achieved.

In addition, in this embodiment, the oscillation efficiency can be improved by reducing the loss due to free carrier absorption. Furthermore, by reducing the operating voltage, the power consumption of the surface-emitting laser 1 can be reduced, and the temperature rise of the surface-emitting laser 1 can be kept low, so the reliability of the surface-emitting laser 1 can be improved. Furthermore, by reducing the operating voltage, the surface-emitting laser 1 can be arrayed.

In this embodiment, a recess 22A is formed in the exposed surface 22S of the spacer layer 22, and the electrode layer 31 is formed to fill the recess 22A. As a result, the electrode layer 31 contacts a portion of the spacer layer 22 that is deeper than the exposed surface 22S, so the density of the lateral current flowing in the spacer layer 22 is reduced and the operating voltage is also reduced compared to when the electrode is provided only on the exposed surface 22S. In addition, since the current path formed by the electrode layer 31 and the electrode layer 32 is provided without passing through the semiconductor DBR layer 21 and the dielectric DBR layer 26, it is not necessary to configure both the semiconductor DBR layer 21 and the dielectric DBR layer 26 with impurity-doped semiconductors. As a result, the loss due to free carrier absorption in the semiconductor DBR layer 21 and the dielectric DBR layer 26 can be reduced. Therefore, high efficiency and low voltage can be achieved.

In this embodiment, the electrode layer 31 is formed so as to contact a part of the exposed surface 22S and also contact a portion of the spacer layer 22 that is deeper than the exposed surface 22S. This reduces the density of the lateral current flowing in the spacer layer 22 and reduces the operating voltage, compared to when the electrode is provided only on the exposed surface 22S. In addition, since the current path formed by the electrode layer 31 and the electrode layer 32 is provided without passing through the semiconductor DBR layer 21 and the dielectric DBR layer 26, it is not necessary to configure both the semiconductor DBR layer 21 and the dielectric DBR layer 26 from impurity-doped semiconductors. As a result, the loss due to free carrier absorption in the semiconductor DBR layer 21 and the dielectric DBR layer 26 can be reduced. Therefore, high efficiency and low voltage can be achieved.

In this embodiment, the electrode layer 31 has a structure in which Ti, Pt, and Au are layered in this order from the inner surface side of the recess 22A. Ti is in contact with the inner surface of the recess 22A and is in ohmic contact with the inner surface of the recess 22A (spacer layer 22). Pt prevents impurities contained in the spacer layer 22 from diffusing into the Au. Au improves the bonding between the electrode layer 31 and the solder. This makes it possible to achieve a lower voltage.

In this embodiment, the spacer layers 22, 24, and 25 are composed of an InP-based semiconductor, the semiconductor DBR layer 21 is composed of a non-doped semiconductor, and the dielectric DBR layer 26 is composed of a dielectric. This makes it possible to reduce losses due to free carrier absorption in the semiconductor DBR layer 21 and the dielectric DBR layer 26. Therefore, high efficiency can be achieved.

In this embodiment, the semiconductor DBR layer 21 and the dielectric DBR layer 26 are configured so that the laser light L is emitted from the dielectric DBR layer 26 side. This makes it possible to realize a top-emitting laser.

In this embodiment, a mesa portion 20A is provided. This allows the electrode layer 31 to be formed close to the tunnel junction layer. As a result, a lower voltage can be achieved.

2. Modification of the First Embodiment
[Variation A]
In the above embodiment, the electrode layer 31 may have a metal layer 31a in which Ti, Pt, and Au are laminated in this order from the inner surface side of the recess 22A, and a plating layer 31b formed on the metal layer 31a, as shown in Fig. 15. In this case, the TAT (Turn Around Time) of the electrode layer 31 can be shortened compared to the case in which the entire electrode layer 31 is composed of the metal layer 31a.

[Variation B]
In the above embodiment, the electrode layer 31 may have a diffusion metal region 31c and an alloy metal layer 31d, for example, as shown in FIG. 16. The alloy metal layer 31d is in contact with the exposed surface 22S, and is, for example, a layer in which AuGe, Ni, and Au are laminated in this order from the exposed surface 22S side. The alloy metal layer 31d may be, for example, a layer in which Pd and Ge are laminated in this order from the exposed surface 22S side. The diffusion metal region 31c is a portion of the spacer layer 22 that is deeper than the exposed surface 22S and is in contact with the alloy metal layer 31d. The diffusion metal region 31c is formed, for example, by heating the alloy metal layer 31d formed on the exposed surface 22S at a predetermined temperature and diffusing Ge contained in the alloy metal layer 31d to a portion of the spacer layer 22 that is deeper than the exposed surface 22S. In this case, the operating voltage can be reduced without etching the spacer layer 22 to form the recess 22A. As a result, a lower voltage can be achieved.

[Variation C]
In the above modification B, the electrode layer 31 may further include a metal layer 31e, for example, as shown in FIG. 17. The metal layer 31e is formed on the alloy metal layer 31d and is made of a material different from that of the alloy metal layer 31d. The metal layer 31e is a laminated body made by laminating, for example, Ti, Pt, and Au in this order from the alloy metal layer 31d side. In this case, a lower voltage can be achieved.

[Modification D]
In the above embodiment and its modified examples, exposed surface 22S may be formed in the same plane as the interface between active layer 23 and spacer layer 22. In this modified example, exposed surface 22S is formed in the same plane as the interface between active layer 23 and spacer layer 22, as shown in Fig. 18, for example. In this case, the distance of the current path can be shortened compared to the above embodiment, and therefore a lower voltage can be achieved.

[Modification E]
In the above embodiment and its modified examples, the electrode layer 31 may be formed in an annular region surrounding the electrode layer 32 in a plan view. In this modified example, the electrode layer 31 has a ring shape surrounding the electrode layer 32 in a plan view, for example, as shown in Figs. 19 and 20. Fig. 19 shows an example of a cross-sectional configuration of the surface-emitting laser 1 according to this modified example. Fig. 20 shows an example of a top surface configuration of the surface-emitting laser 1 shown in Fig. 19. As a result, compared to the above embodiment, the density of the lateral current flowing in the spacer layer 22 is further reduced, and the operating voltage is also further reduced. As a result, a further reduction in voltage can be achieved.

[Variation F]
In the above embodiment and its modified examples, the cross-sectional shape of the recess 22A in the stacking direction may be a forward tapered shape. In this modified example, the cross-sectional shape of the recess 22A in the stacking direction may be a forward tapered shape, for example, as shown in FIG. 21. In this case, the part of the electrode layer 31 embedded in the recess 22A has a shape that is the inverse of the shape of the recess 22A. Even in this case, as in the above embodiment and its modified examples, the density of the lateral current flowing in the spacer layer 22 is reduced, and the operating voltage is also reduced. As a result, a lower voltage can be achieved.

[Modification G]
In the above embodiment and its modified examples, the shape of the recess 22A may be a mortar shape. In this modified example, the shape of the recess 22A may be a mortar shape, for example, as shown in FIG. 22. In this case, the part of the electrode layer 31 embedded in the recess 22A has a shape that is an inversion of the shape of the recess 22A. Even in this case, as in the above embodiment and its modified examples, the density of the lateral current flowing in the spacer layer 22 is reduced, and the operating voltage is also reduced. As a result, a lower voltage can be achieved.

[Variation H]
In the above embodiment and its modified examples, the tunnel junction layer may be formed in a region surrounded by a region made high-resistance by performing ion implantation into the vertical resonator structure 20 in a plan view. In this modified example, for example, as shown in Fig. 23, the tunnel junction layer TJ may be formed in a region surrounded by a region 33 made high-resistance by performing ion implantation into the vertical resonator structure 20 (high-concentration p-layer 28 and high-concentration n-layer 29) in a plan view.

In region 33, the tunnel junction formed by high-concentration p-layer 28 and high-concentration n-layer 29 disappears due to a decrease in carrier concentration caused by ion implantation. This makes the electrical resistance of region 33 greater than the electrical resistance of the tunnel junction layer TJ. Specific examples of the ion species implanted into region 33 include O ions, N ions, B ions, H ions, and He ions. Of these, O ions are more suitable as they can oxidize region 33.

In this way, in this modified example, a current confinement structure is formed by ion implantation. In this case, etching of the high-concentration p-layer 28 and the high-concentration n-layer 29 as in the above embodiment can be omitted.

[Variation I]
In the above modification H, the region 33 may be formed over a region from the upper surface of the spacer layer 25 to the spacer layer 22. In the above modification H, the region 33 may be formed over a region from the upper surface of the spacer layer 25 to the spacer layer 22, for example, as shown in FIG. 24. In this case, a transparent conductive layer 34 may be provided instead of the contact layer 27. The transparent conductive layer 34 is disposed between the dielectric DBR layer 26 and the spacer layer 25, and is in contact with a portion of the upper surface of the spacer layer 25 surrounded by the region 33 and is in contact with the electrode layer 32. The transparent conductive layer 34 is electrically connected to the spacer layer 25 and the electrode layer 32, and constitutes a part of the current path in the surface-emitting laser 1.

The transparent conductive layer 34 is made of, for example, an indium-based transparent conductive material, a tin-based transparent conductive material, or a zinc-based transparent conductive material. Examples of indium-based transparent conductive materials include indium-tin oxide (ITO, indium tin oxide, including Sn-doped In ₂ O ₃ , crystalline ITO, and amorphous ITO), indium-zinc oxide (IZO, indium zinc oxide), indium-gallium oxide (IGO), indium-doped gallium-zinc oxide (IGZO, In-GaZnO ₄ ), IFO (F-doped In ₂ O ₃ ), ITiO (Ti-doped In ₂ O ₃ ), InSn, and InSnZnO. Examples of tin-based transparent conductive materials include tin oxide ( _SnO2 ), ATO (Sb-doped _SnO2 ), FTO (F-doped _SnO2 ), etc. Examples of zinc-based transparent conductive materials include zinc oxide (including ZnO, Al-doped ZnO (AZO), and B-doped ZnO), gallium-doped zinc oxide (GZO), and AlMgZnO (aluminum oxide and magnesium oxide-doped zinc oxide).

In this manner, in this modified example, a transparent conductive layer 34 is provided that is electrically connected to the spacer layer 25 and the electrode layer 32. This makes it possible to inject a current into the surface-emitting laser 1 even when the region 33 is formed across the region that extends from the top surface of the spacer layer 25 to the spacer layer 22.

[Modification J]
In the above-described embodiment and its modified examples, for example, as shown in FIG. 25, a dielectric DBR layer 35 may be provided in place of the semiconductor DBR layer 21.

The dielectric DBR layer 35 is formed by alternately laminating low-refractive index dielectric layers formed of a first dielectric material and high-refractive index dielectric layers formed of a second dielectric material. The optical thicknesses of the low-refractive index dielectric layers and the high-refractive index dielectric layers are, for example, λ ₀ ×1/4. The low-refractive index dielectric layers are formed of, for example, SiO _2. The high-refractive index dielectric layers are formed of, for example, Ta ₂ O _5. The material of the dielectric DBR layer 35 is not limited to the above-mentioned dielectric materials. The material of the dielectric DBR layer 35 may be a material different from that of the dielectric DBR layer 26, or may be a material common to that of the dielectric DBR layer 26.

In this way, in this modified example, a dielectric DBR layer 35 is provided. This makes it possible to reduce loss due to free carrier absorption in the dielectric DBR layer 35. Therefore, high efficiency and low voltage can be achieved.

[Modification K]
In the above modification J, for example, as shown in FIG. 26, a reflective metal layer 36 may be provided in contact with the dielectric DBR layer 35 on the side opposite to the active layer 23. The reflective metal layer 36 corresponds to the end of the reflective mirror on the dielectric DBR layer 35 side as viewed from the active layer 23. The reflective metal layer 36 is a layer that supports the function of the dielectric DBR layer 35 and contributes to reducing the number of pairs of the dielectric DBR layer 35. The reflective metal layer 36 is composed of, for example, gold (Au), silver (Ag), or aluminum (Al). The film thickness of the reflective metal layer 36 is, for example, 20 nm or more.

In this manner, in this modified example, a reflective metal layer 36 is provided. This allows the number of pairs of the dielectric DBR layer 35 to be reduced, and therefore the TAT (Turn Around Time) of the surface-emitting laser 1 can be shortened compared to a case in which the reflective metal layer 36 is not provided.

[Variation L]
In the above embodiment and its modified examples A to I, for example, as shown in FIG. 27, a substrate 40 and a semiconductor DBR layer 41 may be provided instead of the substrate 10 and the semiconductor DBR layer 21.

The substrate 40 is a crystal growth substrate used for epitaxially growing the semiconductor DBR layer 41. In this modification, the substrate 40 can be omitted. The substrate 40 is an n-type GaAs substrate. The n-type GaAs substrate contains, for example, silicon (Si) as an n-type impurity. The semiconductor DBR layer 41 is a non-doped GaAs-based semiconductor DBR layer. The semiconductor DBR layer 41 is formed by alternately stacking low-refractive index semiconductor layers containing non-doped AlAs and high-refractive index semiconductor layers containing non-doped GaAs. The optical thicknesses of the low-refractive index semiconductor layers and the high-refractive index semiconductor layers are, for example, λ ₀ ×1/4.

In this modification, a substrate 40 on which a semiconductor DBR layer 41 is formed is bonded with the surface of the semiconductor DBR layer 41 facing the spacer layer 22. Here, the semiconductor DBR layer 41 is not included in the current path. Therefore, it is possible to bond a semiconductor DBR layer 41 according to the size of the oscillation wavelength _λ0 and the purpose of use.

[Variation M]
In the above embodiment and its modified examples A to J, and L, the surface emitting laser 1 may be a back-emitting type laser having a light emitting surface 1S provided on the back surface. In this modified example, the surface emitting laser 1 may be configured, for example, as shown in FIG. 28, so that the laser light L with the oscillation wavelength λ ₀ is emitted from the semiconductor DBR layer 21 side. Specifically, in the vertical resonator structure 20, the number of pairs and reflectance of the reflecting mirror on the semiconductor DBR layer 21 side and the number of pairs and reflectance of the reflecting mirror on the dielectric DBR layer 26 side may be configured so that the laser light L with the oscillation wavelength λ ₀ is emitted from the semiconductor DBR layer 21 side. Even in the case of such a configuration, the same effects as those of the above embodiment and its modified examples A to J, and L can be obtained.

[Modification N]
29, a dielectric DBR layer 35 may be provided instead of the substrate 10 and the semiconductor DBR layer 21. Even in the case of such a configuration, the same effects as those of the above modification M can be obtained.

[Variation O]
30, a semiconductor DBR layer 41 may be provided instead of the substrate 10 and the semiconductor DBR layer 21. Even in the case of such a configuration, the same effects as those of the above-mentioned modification M can be obtained.

[Modification P]
In the above-mentioned embodiment and its modified examples A to J, L to O, for example, as shown in FIG. 31, a reflective metal layer 37 may be provided in contact with the dielectric DBR layer 26 on the side opposite to the active layer 23. The reflective metal layer 37 corresponds to the end portion of the reflective mirror on the dielectric DBR layer 26 side as viewed from the active layer 23. The reflective metal layer 37 is a layer that supports the function of the dielectric DBR layer 26 and contributes to reducing the number of pairs of the dielectric DBR layer 26. The reflective metal layer 37 is composed of, for example, gold (Au), silver (Ag), or aluminum (Al). The film thickness of the reflective metal layer 37 is, for example, 20 nm or more.

In this manner, in this modified example, the reflective metal layer 37 is provided. This allows the number of pairs of the dielectric DBR layer 26 to be reduced, and therefore the heat dissipation performance of the surface-emitting laser 1 can be improved compared to a case in which the reflective metal layer 37 is not provided.

3. Second embodiment
[composition]
A surface-emitting laser 2 according to a second embodiment of the present disclosure will be described. Fig. 32 illustrates an example of a cross-sectional configuration of the surface-emitting laser 2. Fig. 33 illustrates an example of a top surface configuration of the surface-emitting laser 2.

In this embodiment, a groove portion 20B is provided in place of the mesa portion 20A in the vertical resonator structure 20 in the first embodiment and modifications A to L described above. An exposed surface 22S is formed on the bottom surface of the groove portion 20B. Even with this configuration, it is possible to obtain the same effects as the first embodiment and modifications A to L described above.

4. Modification of the Second Embodiment
[Variation Q]
In the second embodiment, the surface-emitting laser 2 may be a back-emitting type laser having a light-emitting surface 1S provided on the back surface. In this modification, the surface-emitting laser 2 may be configured to emit laser light L having an oscillation wavelength λ ₀ from the semiconductor DBR layer 21 side, as shown in Fig. 34, for example. Even in the case of such a configuration, the same effects as those of the second embodiment can be obtained.

The present disclosure has been described above by presenting several embodiments and their modified examples, but the present disclosure is not limited to the above-described embodiments, and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

Furthermore, for example, the present disclosure can have the following configuration.
(1)
A first DBR (Distributed Bragg Reflector) layer;
A second DBR layer;
an active layer disposed between the first DBR layer and the second DBR layer;
a first spacer layer of a first conductivity type disposed between the active layer and the first DBR layer;
a second spacer layer of a second conductivity type disposed between the active layer and the second DBR layer;
a tunnel junction layer disposed between the active layer and the second DBR layer;
a first electrode layer electrically connected to the first spacer layer without the first DBR layer;
a second electrode layer electrically connected to the second spacer layer without the second DBR layer therebetween;
the first spacer layer has a flat exposed surface in a region not facing the tunnel junction layer;
the first electrode layer is formed so as to be in contact with a portion of the first spacer layer that is deeper than the exposed surface.
(2)
the first spacer layer has a recess in the exposed surface;
The surface-emitting laser according to (1), wherein the first electrode layer is formed so as to fill the recess.
(3)
The surface-emitting laser according to (1) or (2), wherein the first electrode layer is formed so as to be in contact with a part of the exposed surface and also in contact with a portion of the first spacer layer that is deeper than the exposed surface.
(4)
The surface-emitting laser according to (2), wherein the first electrode layer has a structure in which Ti, Pt, and Au are laminated in this order from the inner surface side of the recess.
(5)
The surface-emitting laser according to (2), wherein the first electrode layer has a metal layer in which Ti, Pt, and Au are laminated in this order from the inner surface side of the recess, and a plating layer formed on the metal layer.
(6)
The surface-emitting laser described in (1) or (3), wherein the first electrode layer has an alloy metal layer in contact with the exposed surface, and a diffused metal region of the first spacer layer that is deeper than the exposed surface and in contact with the alloy metal layer.
(7)
The surface-emitting laser according to (6), wherein the first electrode layer further includes a metal layer formed on the alloy metal layer and made of a material different from that of the alloy metal layer.
(8)
The surface-emitting laser according to any one of (1) to (7), wherein the exposed surface is formed in the same plane as an interface between the active layer and the first spacer layer.
(9)
The surface-emitting laser according to any one of (1) to (8), wherein the first electrode layer is formed in an annular region surrounding the second electrode layer in a plan view.
(10)
3. The surface-emitting laser according to claim 2, wherein a cross-sectional shape of the recess in a stacking direction is a forward tapered shape.
(11)
The surface-emitting laser according to (2), wherein the recess has a cone shape.
(12)
a stacked structure including the first spacer layer, the active layer, the tunnel junction layer, and the second spacer layer;
The surface-emitting laser according to any one of (1) to (11), wherein the tunnel junction layer is formed in a region surrounded by a region that has been made highly resistive by performing ion implantation into the stacked structure in a plan view.
(13)
The surface-emitting laser according to any one of (1) to (12), further comprising a transparent conductive layer disposed between the second spacer layer and the second DBR layer and electrically connected to the second electrode.
(14)
the first spacer layer and the second spacer layer are configured to include an InP-based semiconductor;
the first DBR layer is a non-doped semiconductor DBR layer,
The surface emitting laser according to any one of (1) to (13), wherein the second DBR layer is a dielectric DBR layer.
(15)
the first spacer layer and the second spacer layer are configured to include an InP-based semiconductor;
The surface-emitting laser according to any one of (1) to (13), wherein the first DBR layer and the second DBR layer are dielectric DBR layers.
(16)
The surface emitting laser according to (15), further comprising a reflective metal layer in contact with the first DBR layer on the side opposite to the active layer.
(17)
the first spacer layer and the second spacer layer are configured to include an InP-based semiconductor;
the first DBR layer is a non-doped GaAs-based semiconductor DBR layer,
The surface emitting laser according to any one of (1) to (13), wherein the second DBR layer is a dielectric DBR layer.
(18)
The surface-emitting laser according to any one of (1) to (17), wherein the first DBR layer and the second DBR layer are configured such that laser light is emitted from the second DBR layer side.
(19)
The surface-emitting laser according to any one of (1) to (17), further comprising a reflective metal layer in contact with the second DBR layer on the side opposite to the active layer.
(20)
The surface-emitting laser according to any one of (1) to (19), further comprising a mesa portion including at least the active layer, the tunnel junction layer, and the second spacer layer.
(21)
a stacked structure including the first DBR layer, the first spacer layer, the active layer, the tunnel junction layer, the second spacer layer and the second DBR layer;
The laminated structure further includes a groove having the exposed surface as a bottom surface,
The surface-emitting laser according to any one of (1) to (19), wherein the first electrode layer is formed so as to be in contact with a portion of the first spacer layer that is deeper than the exposed surface in the groove.

In a surface-emitting laser according to an embodiment of the present disclosure, the first spacer layer disposed between the active layer and the first DBR layer has a flat exposed surface in a region not facing the tunnel junction layer. The first electrode layer is formed so as to contact a portion of the first spacer layer that is deeper than the exposed surface. This reduces the density of the lateral current flowing in the first spacer layer and reduces the operating voltage, compared to when the first electrode is provided only on the exposed surface. In addition, since the current path formed by the first electrode layer and the second electrode layer is provided without passing through the first DBR layer and the second DBR layer, for example, it is not necessary to configure both the first DBR layer and the second DBR layer with an impurity-doped semiconductor. For example, it is possible to configure both the first DBR layer and the second DBR layer with a non-doped semiconductor or dielectric. In addition, it is possible to configure the first DBR layer with a non-doped semiconductor and the second DBR layer with a dielectric, for example. As a result, the loss due to free carrier absorption in the first and second DBR layers can be reduced. This allows for high efficiency and low voltage to be achieved.

This application claims priority based on Japanese Patent Application No. 2023-032514, filed on March 3, 2023 in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

Those skilled in the art may conceive of various modifications, combinations, subcombinations, and variations depending on design requirements and other factors, and it is understood that these are within the scope of the appended claims and their equivalents.

Claims (21)

A first DBR (Distributed Bragg Reflector) layer;
A second DBR layer;
an active layer disposed between the first DBR layer and the second DBR layer;
a first spacer layer of a first conductivity type disposed between the active layer and the first DBR layer;
a second spacer layer of a second conductivity type disposed between the active layer and the second DBR layer;
a tunnel junction layer disposed between the active layer and the second DBR layer;
a first electrode layer electrically connected to the first spacer layer without the first DBR layer;
a second electrode layer electrically connected to the second spacer layer without the second DBR layer therebetween;
the first spacer layer has a flat exposed surface in a region not facing the tunnel junction layer;
the first electrode layer is formed so as to be in contact with a portion of the first spacer layer that is deeper than the exposed surface. the first spacer layer has a recess in the exposed surface;
The surface emitting laser according to claim 1 , wherein the first electrode layer is formed so as to fill the recess. The surface-emitting laser according to claim 1 , wherein the first electrode layer is formed so as to be in contact with a part of the exposed surface and also in contact with a portion of the first spacer layer that is deeper than the exposed surface. The surface emitting laser according to claim 2 , wherein the first electrode layer has a structure in which Ti, Pt, and Au are laminated in this order from the inner surface side of the recess. 3. The surface emitting laser according to claim 2, wherein the first electrode layer comprises a metal layer in which Ti, Pt and Au are laminated in this order from the inner surface side of the recess, and a plating layer formed on the metal layer. 2. The surface-emitting laser according to claim 1, wherein the first electrode layer has an alloy metal layer in contact with the exposed surface, and a diffused metal region of the first spacer layer that is deeper than the exposed surface and in contact with the alloy metal layer. The surface emitting laser according to claim 6 , wherein the first electrode layer further includes a metal layer formed on the alloy metal layer and made of a material different from that of the alloy metal layer. The surface emitting laser according to claim 1 , wherein the exposed surface is formed in the same plane as an interface between the active layer and the first spacer layer. The surface emitting laser according to claim 1 , wherein the first electrode layer is formed in an annular region surrounding the second electrode layer in a plan view. The surface emitting laser according to claim 2 , wherein a cross-sectional shape of the recess in a stacking direction is a forward tapered shape. The surface emitting laser according to claim 2 , wherein the recess has a cone shape. a stacked structure including the first spacer layer, the active layer, the tunnel junction layer, and the second spacer layer;
2 . The surface emitting laser according to claim 1 , wherein the tunnel junction layer is formed in a region surrounded by a region that is made highly resistive by ion implantation into the laminated structure in a plan view. The surface emitting laser according to claim 1 , further comprising a transparent conductive layer disposed between the second spacer layer and the second DBR layer and electrically connected to the second electrode. the first spacer layer and the second spacer layer are configured to include an InP-based semiconductor;
the first DBR layer is a non-doped semiconductor DBR layer,
The surface emitting laser according to claim 1 , wherein the second DBR layer is a dielectric DBR layer. the first spacer layer and the second spacer layer are configured to include an InP-based semiconductor;
The surface emitting laser according to claim 1 , wherein the first DBR layer and the second DBR layer are dielectric DBR layers. 16. The surface-emitting laser according to claim 15, further comprising a reflective metal layer in contact with the first DBR layer on the side opposite to the active layer, the reflective metal layer corresponding to a terminal end of a reflective mirror on the first DBR layer side as viewed from the active layer. the first spacer layer and the second spacer layer are configured to include an InP-based semiconductor;
the first DBR layer is a non-doped GaAs-based semiconductor DBR layer,
The surface emitting laser according to claim 1 , wherein the second DBR layer is a dielectric DBR layer. The surface emitting laser according to claim 1 , wherein the first DBR layer and the second DBR layer are configured such that laser light is emitted from the second DBR layer side. a reflective metal layer in contact with the second DBR layer on a side opposite to the active layer;
2. The surface emitting laser according to claim 1, wherein the reflective metal layer corresponds to a terminal end of a reflective mirror on the second DBR layer side as viewed from the active layer. The surface emitting laser according to claim 1 , further comprising a mesa portion including at least the active layer, the tunnel junction layer, and the second spacer layer. a stacked structure including the first DBR layer, the first spacer layer, the active layer, the tunnel junction layer, the second spacer layer and the second DBR layer;
The laminated structure further includes a groove having the exposed surface as a bottom surface,
The surface emitting laser according to claim 1 , wherein the first electrode layer is formed so as to be in contact with a portion of the first spacer layer that is deeper than the exposed surface in the groove.