TW202504193A - Surface Emitting Laser - Google Patents

Abstract

The subject of the present invention is to provide a surface emitting laser capable of achieving high efficiency and low voltage. The surface emitting laser of one embodiment of the present disclosure includes a first DBR layer, a second DBR layer, an active layer, a first spacer layer, a second spacer layer, a tunneling junction layer, a first electrode layer and a second electrode layer. The first electrode layer is electrically connected to the first spacer layer without passing through the first DBR layer. The second electrode layer is electrically connected to the second spacer layer without passing through the second DBR layer. The first spacer layer has a flat exposed surface in a region not opposite to the tunneling junction layer. The first electrode layer is formed to be in contact with a portion of the first spacer layer that is deeper than the exposed surface.

Description

Surface Emitting Laser

The present disclosure relates to a surface emitting laser.

Regarding surface emitting lasers, for example, they have been disclosed in patent documents 1 and 2. [Prior art document] [Patent document]

[Patent document 1] Japanese Patent Publication No. 2007-315883 [Patent document 2] Japanese Patent Publication No. 9-27671

[The problem the invention is trying to solve]

In order to emit laser light into space, sufficient safety for the retina of the eye must be considered (no harm to vision). Therefore, in recent years, the industry has been developing surface-emitting lasers that are harmless to vision. In surface-emitting lasers that are harmless to vision, high efficiency and low power consumption are required. It is ideal to provide a surface-emitting laser that can achieve high efficiency and low voltage. [Technical means to solve the problem]

The surface emitting laser of one embodiment of the present disclosure includes a first DBR layer, a second DBR layer, an active layer, a first spacer layer, a second spacer layer, a tunneling junction layer, a first electrode layer and a second electrode layer. The active layer is disposed between the first DBR layer and the second DBR layer. The first spacer layer is disposed between the active layer and the first DBR layer. The second spacer layer is disposed between the active layer and the second DBR layer. The tunneling junction layer is disposed between the active layer and the second DBR layer. The first electrode layer is electrically connected to the first spacer layer without passing through the first DBR layer. The second electrode layer is electrically connected to the second spacer layer without passing through the second DBR layer. The first spacer layer has a flat exposed surface in a region not facing the tunnel junction layer. The first electrode layer is formed to be in contact with a portion of the first spacer layer that is deeper than the exposed surface.

The following is a detailed description of the form used to implement the present disclosure with reference to the drawings. The following description is a specific example of the present disclosure, and the present invention is not limited to the following form. In addition, the present disclosure is not limited to the configuration, size, size ratio, etc. of each component shown in each figure. In addition, the description is carried out in the following order. 1. The first embodiment… Figures 1 to 14 Example of embedding the lower electrode semiconductor layer 2. Variations of the first embodiment Variation A: An example in which the lower electrode is formed by a metal layer and a plating layer (Figure 15) Variation B: An example in which the lower electrode is formed by a diffused metal region and an alloy metal layer (Figure 16) Variation C: An example in which the lower electrode is formed by a diffused metal region, an alloy metal layer, and a metal layer (Figure 17) Variation D: An example in which a lower electrode is formed at the interface between an active layer and a semiconductor layer connected to the active layer (Figure 18) Variation E: An example in which a ring-shaped lower electrode is provided around the table (Fig. 19, Fig. 20) Variation F: An example in which the cross-sectional shape of the portion where the lower electrode is buried is set to be a right cone (Fig. 21) Variation G: An example in which the portion where the lower electrode is buried is set to be a cone shape (Fig. 22) Variation H: An example in which a tunneling junction is formed using ion implantation (Fig. 23) Variation I: An example in which a transparent conductive layer is provided between the semiconductor layer and the upper DBR layer (Fig. 24) Variation J: An example in which the lower DBR layer is formed by a dielectric (Fig. 25) Variation K: An example in which a lower reflector is formed by a dielectric DBR layer and a reflective metal layer (Fig. 26) Variation L: Example of forming the lower DBR layer with GaAs semiconductor (Fig. 27) Variation M: Example of burying the lower electrode semiconductor layer in a back-emitting surface-emitting laser (Fig. 28) Variation N: Example of forming the lower DBR layer with a dielectric in a back-emitting surface-emitting laser (Fig. 29) Variation O: Example of forming the lower DBR layer with GaAs semiconductor in a back-emitting surface-emitting laser (Fig. 30) Variation P: Example of forming the upper reflector with a dielectric DBR layer and a reflective metal layer in a back-emitting surface-emitting laser (Fig. 31) 3. Second embodiment Example of providing a lower electrode on the bottom surface of the groove (Fig. 32, Fig. 33) 4. Variations of the second embodiment Variation Q: An example of burying the lower electrode semiconductor layer in a back-emitting surface-emitting laser (Figure 34)

<1. First Implementation Form> [Structure] The surface emitting laser 1 of the first implementation form of the present disclosure is described. FIG1 shows an example of a cross-sectional structure of the surface emitting laser 1. FIG2 shows an example of an upper surface structure of the surface emitting laser 1.

The surface emitting laser 1 has a vertical resonator structure 20 on a substrate 10. The substrate 10 is a crystal growth substrate used when epitaxially growing the vertical resonator structure 20. In the surface emitting laser 1, the substrate 10 can be omitted.

The vertical resonator structure 20 has: a semiconductor DBR (distributed Bragg reflector) layer 21 and a dielectric DBR layer 26, and a cavity layer arranged between the semiconductor DBR layer 21 and the dielectric DBR layer 26. The cavity layer is designed in accordance with the oscillation wavelength λ ₀ and the purpose. The cavity layer, for example, has: an active layer 23, a spacer layer 22 arranged between the active layer 23 and the semiconductor DBR layer 21, spacer layers 24 and 25 arranged between the active layer 23 and the dielectric DBR layer 26, and a tunneling junction layer arranged between the active layer 23 and the dielectric DBR layer 26.

The spacer layer 24 is arranged on the side of the active layer 23, and the spacer layer 25 is arranged on the side of the dielectric DBR layer 26. The tunnel junction layer is surrounded by the spacer layers 24 and 25 as shown in FIG1 , for example. The spacer layer 24 is connected to the bottom surface of the tunnel junction layer, and the spacer layer 25 is connected to the top surface and the side surface of the tunnel junction layer. The tunnel junction layer is composed of a high-concentration p layer 28 and a high-concentration n layer 29 stacked on each other as shown in FIG1 , for example. The spacer layer 24 is connected to the bottom surface of the high-concentration p layer 28, and the spacer layer 25 is connected to the side surface of the high-concentration p layer 28. The high-concentration p layer 28 is in contact with the bottom surface of the high-concentration n layer 29 , and the spacer layer 25 is in contact with the top surface and side surfaces of the high-concentration n layer 29 .

The tunneling junction layer forms a current limiting structure formed by the tunneling junction. In the tunneling junction layer, at the boundary between the high-concentration p layer 28 and the high-concentration n layer 29, the conduction band of the high-concentration p layer 28 and the valence band of the high-concentration n layer 29 are close to each other, forming a tunneling junction formed by the high-concentration p layer 28 and the high-concentration n layer 29. As a result, in the tunneling junction layer, current flows from the high-concentration n layer 29 to the high-concentration p layer 28.

The surface emitting laser 1 is configured to emit laser light L having an oscillation wavelength λ ₀ from the dielectric DBR layer 26 side. Specifically, in the vertical resonator structure 20, the logarithm and reflectivity of the reflective mirror on the semiconductor DBR layer 21 side and the logarithm and reflectivity of the reflective mirror on the dielectric DBR layer 26 side are configured to emit laser light L having an oscillation wavelength λ ₀ from the dielectric DBR layer 26 side. Therefore, the surface emitting laser 1 is a surface emitting type laser that emits laser light L from a light emitting surface 1S provided on the dielectric DBR layer 26 side.

In the vertical resonator structure 20, at least the active layer 23, the spacer layer 24, the tunneling junction layer, the spacer layer 25 and the dielectric DBR layer 26 constitute a columnar mesa portion 20A extending in the normal direction of the substrate 10. FIG. 1 shows an example in which the mesa portion 20A is constituted by a portion of the spacer layer 22, the active layer 23, the spacer layer 24, the tunneling junction layer, the spacer layer 25 and the dielectric DBR layer 26. The mesa portion 20A is, for example, circular in a plan view. The semiconductor DBR layer 21 is disposed in a region on the side of the substrate 10 in relation to the position of the mesa portion 20A.

The tunneling junction layer is disposed in the central portion of the mesa portion 20A in a plan view. The tunneling junction layer is, for example, circular in a plan view. The tunneling junction layer is disposed on the opposite side of the substrate 10 (i.e., the light emitting surface 1S side) in relation to the position of the active layer 23. A convex portion having a shape corresponding to the shape of the tunneling junction layer is formed on the upper surface of the spacer layer 25 at a position opposite to the tunneling junction layer. The convex portion is disposed in the central portion of the mesa portion 20A in a plan view, and is, for example, circular in a plan view.

The dielectric DBR layer 26 is in contact with the upper surface of the spacer layer 25, for example, in contact with the upper surface of the above-mentioned convex portion. In addition, FIG. 1 shows an example in which the dielectric DBR layer 26 is in contact with not only the upper surface of the above-mentioned convex portion in the upper surface of the spacer layer 25, but also the side surface and bottom edge portion of the above-mentioned convex portion. In addition, the portion of the dielectric DBR layer 26 in contact with the side surface and bottom edge portion of the above-mentioned convex portion does not contribute to laser oscillation.

The surface emitting laser 1 further includes a contact layer 27 and an electrode layer 32 as an upper electrode on the upper portion of the mesa portion 20A, as shown in, for example, FIG. 1 and FIG. 2 . The contact layer 27 is in contact with the spacer layer 25 and the electrode layer 32. As shown in, for example, FIG. 1 , the contact layer 27 is in contact with the bottom edge portion of the protrusion of the spacer layer 25 and is, for example, in a ring shape surrounding the protrusion of the spacer layer 25 in a plan view. The contact layer 27 is a layer for making the spacer layer 25 and the electrode layer 32 in ohmic contact with each other. The electrode layer 32 is in contact with the contact layer 27, and is electrically connected to the spacer layer 25 through the contact layer 27 and further through the dielectric DBR layer 26. As shown in FIG. 1 and FIG. 2, the electrode layer 32 is in a ring shape surrounding the protrusion of the spacer layer 25 in a plan view.

The surface emitting laser 1 further has an electrode layer 31 as a lower electrode at a position corresponding to the bottom edge of the mesa portion 20A, as shown in, for example, FIG. 1. At a position corresponding to the bottom edge of the mesa portion 20A, a portion of the spacer layer 22 is exposed, as shown in, for example, FIG. 1 and FIG. 2. Hereinafter, the portion of the spacer layer 22 corresponding to the bottom edge of the mesa portion 20A is referred to as an exposed surface 22S. The exposed surface 22S is a flat surface. The exposed surface 22S is, for example, a flat surface parallel to the stacking surface of the semiconductor DBR layer 21. The electrode layer 31 is formed to be in contact with a portion of the exposed surface 22S and also in contact with a portion of the spacer layer 22 that is deeper than the exposed surface 22S. The spacer layer 22 has a recess 22A in the exposed surface 22S, which has a depth that does not reach the semiconductor DBR layer 21. The electrode layer 31 is formed to bury the recess 22A and is in contact with the spacer layer 22 in the inner surface of the recess 22A. The electrode layer 31 is electrically connected to the spacer layer 22 without passing through the semiconductor DBR layer 21. Therefore, in the surface emitting laser 1, the current path formed by the electrode layer 31 and the electrode layer 32 (the dotted line portion in FIG. 1) is provided without passing through the semiconductor DBR layer 21 and the dielectric DBR layer 26.

Next, the materials of the components of the surface emitting laser 1 are explained.

The substrate 10 is an n-type InP substrate. The n-type InP substrate contains, for example, silicon (Si) as an n-type impurity.

The semiconductor DBR layer 21 is a non-doped semiconductor DBR layer. The semiconductor DBR layer 21 is formed by alternately laminating a low-refractive-index semiconductor layer containing non-doped InP and a high-refractive-index semiconductor layer containing non-doped AlGaInAs. The optical thicknesses of the low-refractive-index semiconductor layer and the high-refractive-index semiconductor layer are, for example, λ ₀ ×1/4.

The spacer layers 22, 24, and 25 are composed of an InP-based semiconductor. The spacer layer 22 is composed of, for example, n-type InP. In the n-type InP, for example, silicon (Si) is contained as an n-type impurity. The spacer layer 24 is composed of, for example, p-type InP. In the p-type InP, for example, carbon (C), zinc (Zn), magnesium (Mg), and curium (Be) are contained as a p-type impurity. The spacer layer 25 is composed of, for example, n-type InP. In the n-type InP, for example, silicon (Si) is contained as an n-type impurity.

The dielectric DBR layer 26 is formed by alternately laminating a low refractive index dielectric layer formed of a first dielectric material and a high refractive index dielectric layer formed of a second dielectric material. The optical thicknesses of the low refractive index dielectric layer and the high refractive index dielectric layer are, for example, λ ₀ × 1/4. The low refractive index dielectric layer is formed of, for example, SiO _2. The high refractive index dielectric layer is formed of, for example, Ta ₂ O _5. The material of the dielectric DBR layer 26 is not limited to the above-mentioned dielectric materials.

The contact layer 27 is composed of, for example, n-type InGaAs containing n-type impurities having a higher concentration than the n-type impurity concentration contained in the spacer layer 25. In the n-type InGaAs, as an n-type impurity, the same impurity as the n-type impurity contained in the spacer layer 25 is contained. The electrode layer 31 has a structure in which Ti, Pt, and Au are sequentially layered from the inner surface side of the recess 22A of the spacer layer 22. Ti, Pt, and Au are formed, for example, by sputtering or evaporation. The electrode layer 32 has a structure in which Ti, Pt, Au, or AuGe, Ni, and Au are sequentially layered from the contact layer 27 side. The material of the electrode layer 32 is not limited to the above-mentioned materials.

The high-concentration P layer 28 is composed of p-type AlGalnAs containing a p-type impurity with a higher concentration than the p-type impurity contained in the spacer layer 24. In the p-type AlGalnAs, for example, the same impurity as the p-type impurity contained in the spacer layer 24 is contained as the p-type impurity. The high-concentration n layer 29 is composed of n-type InP containing an n-type impurity with a higher concentration than the n-type impurity contained in the spacer layer 25. In the n-type InP, for example, the same impurity as the n-type impurity contained in the spacer layer 25 is contained as the n-type impurity.

[Manufacturing method] Next, the manufacturing method of the surface emitting laser 1 of this embodiment is described.

In order to manufacture the surface emitting laser 1, compound semiconductors are formed in batches by epitaxial growth methods such as MOCVD (Metal Organic Chemical Vapor Deposition) on a substrate 10 made of InP. At this time, as raw materials of the compound semiconductors, for example, methyl-based organic metal gases such as trimethylaluminum (TMAl), trimethylgallium (TMGa), and trimethylindium (TMIn), hydrogen phosphide (PH ₃ ) gas, and hydrogen arsenide (AsH ₃ ) gas are used, as raw materials of donor impurities, for example, disilane (Si ₂ H ₆ ) is used, and as raw materials of acceptor impurities, for example, carbon tetrabromide (CBr ₄ ) is used.

First, on the substrate 10, a semiconductor DBR layer 21, a spacer layer 22, an active layer 23, a spacer layer 24, a high-concentration p-layer 28, and a high-concentration n-layer 29 are formed by an epitaxial growth method such as MOCVD (FIG. 3). Next, after forming an anti-etching agent layer (not shown) that is circular in a top view, the high-concentration p-layer 28 and the high-concentration n-layer 29 are selectively etched using the anti-etching agent layer as a mask. Thus, a high-concentration p-layer 28 and a high-concentration n-layer 29 that are circular in a top view are formed (FIG. 4). Thereafter, the anti-etching agent layer is removed.

Next, a spacer layer 25 and a contact layer 27 are formed on the surface including the circular high-concentration p layer 28 and the high-concentration n layer 29 by an epitaxial growth method such as MOCVD (FIG. 5). At this time, a step structure portion imitating the shape of the circular high-concentration p layer 28 and the high-concentration n layer 29 is formed in the spacer layer 25 and the contact layer 27 in the region opposite to the circular high-concentration p layer 28 and the high-concentration n layer 29.

Next, for example, after forming a circular anti-etching agent layer (not shown) covering a predetermined area centered on the circular high-concentration p-layer 28 and the high-concentration n-layer 29 in a top view, the semiconductor layer such as the contact layer 27 is selectively etched using the anti-etching agent layer as a mask, and the semiconductor layer is etched to a depth reaching the spacer layer 22. At this time, it is preferred to use RIE (Reactive Ion Etching) performed by, for example, a C1-based gas. At this time, a columnar mesa portion 20A is formed (FIG. 6). At this time, the spacer layer 22 is exposed at the bottom edge of the mesa portion 20A. That is, an exposed surface 22S is formed at the bottom edge of the mesa portion 20A. Afterwards, the resist layer is removed.

Next, an electrode layer 32 is formed in contact with the upper surface of the mesa portion 20A (contact layer 27) (FIG. 7). Then, for example, after an anti-etching agent layer (not shown) is formed that covers the electrode layer 32 and the mesa portion 20A and has an opening only at a predetermined portion of the exposed surface 22S, the spacer layer 22 is selectively etched using the anti-etching agent layer as a mask, and the spacer layer 22 is etched to a depth that does not reach the semiconductor DBR layer 21. At this time, it is preferred to use RIE using, for example, a C1-based gas. In this way, a recess 22A is formed in the exposed surface 22S (FIG. 8). Thereafter, the anti-etching agent layer is removed.

Next, the electrode layer 31 is formed by embedding the recess 22A (Fig. 9). Thus, the electrode layer 31 is in contact with a portion of the exposed surface 22S and also in contact with a portion of the spacer layer 22 that is deeper than the exposed surface 22S (specifically, the inner surface of the recess 22A). Next, after an anti-etching agent layer (not shown) having an opening only in the portion surrounded by the electrode layer 32 on the upper surface of the mesa portion 20A is formed, the contact layer 27 is selectively etched using the anti-etching agent layer as a mask. In this way, the convex portion of the spacer layer 25 is exposed (Fig. 10). Thereafter, the anti-etching agent layer is removed.

Next, for example, a dielectric DBR layer 26 is formed on the entire surface of the spacer layer 25 including the surface of the convex portion by vacuum evaporation ( FIG. 11 ). Then, the portion of the formed dielectric DBR layer 26 other than the portion surrounded by the electrode layer 32 is selectively removed. In this way, the surface emitting laser 1 is manufactured.

[Operation] In the surface emitting laser 1 thus constructed, when a predetermined voltage is applied between the electrode layer 31 electrically connected to the spacer layer 22 and the electrode layer 32 electrically connected to the contact layer 27, a current limited by the tunneling junction layer composed of the high-concentration P layer 28 and the high-concentration n layer 29 is injected into the active layer 23, thereby generating light generated by the recombination of electrons and holes. At this time, the light generated in the active layer 23 is confined in the direction of the layer surface by the tunneling junction layer. As a result, laser oscillation is generated at an oscillation wavelength λ ₀ by the vertical resonator structure 20. Then, the light leaking out from the dielectric DBR layer 26 is a beam-shaped laser light L, and is output to the outside from the light emitting surface 1S.

[Effects] Next, the effects of the surface emitting laser 1 of this embodiment will be described.

In order to emit laser light into space, sufficient safety for the retina of the eye must be considered (no harm to vision). Therefore, in recent years, the industry has been developing surface-emitting lasers that are harmless to vision. In surface-emitting lasers that are harmless to vision, high efficiency and low power consumption are required.

On the other hand, in the present embodiment, the spacer layer 22 disposed between the active layer 23 and the semiconductor DBR layer 21 is provided with a flat exposed surface 22S in a region not facing the tunnel junction layer. Furthermore, the electrode layer 31 is formed to be in contact with a portion of the spacer layer 22 that is deeper than the exposed surface 22S. Thus, for example, compared with the case where the electrode layer 131 is provided only on the exposed surface 22S in the surface emitting laser 100 of the comparative example described in FIG. 12 , the density of the current flowing in the spacer layer 22 in the lateral direction is reduced, and the operating voltage is also reduced.

As shown in FIG13 , the sheet resistance of the surface emitting laser 1 of the embodiment can be significantly reduced compared to the sheet resistance of the surface emitting laser 100 of the comparative example. As a result, as shown in FIG14 , the operating voltage of the surface emitting laser 1 of the embodiment can be significantly reduced (also by about 0.2 V) compared to the operating voltage of the surface emitting laser 100 of the comparative example.

Furthermore, in this embodiment, since the current path formed by the electrode layer 31 and the electrode layer 32 is provided without passing through the semiconductor DBR layer 21 and the dielectric DBR layer 26, it is not necessary to form both the semiconductor DBR layer 21 and the dielectric DBR layer 26 with a semiconductor doped with impurities. As a result, the loss caused by free carrier absorption in the semiconductor DBR layer 21 and the dielectric DBR layer 26 can be reduced. Furthermore, since the impurity concentration of the spacer layer 22 itself can also be reduced, the loss caused by free carrier absorption in the spacer layer 22 can also be reduced in this regard. Therefore, high efficiency and low voltage can be achieved.

In addition, in this embodiment, the oscillation efficiency can be improved by reducing the loss due to free carrier absorption. In addition, since the power consumption in the surface emitting laser 1 can be reduced by reducing the operating voltage, the temperature rise of the surface emitting laser 1 can be suppressed to a low level, so the reliability of the surface emitting laser 1 can be improved. In addition, by reducing the operating voltage, the surface emitting laser 1 can be arrayed.

In this embodiment, a recess 22A is formed in the exposed surface 22S of the spacer layer 22, and the electrode layer 31 is formed to bury the recess 22A. As a result, since the electrode layer 31 is in contact with a portion of the spacer layer 22 that is deeper than the exposed surface 22S, the density of the current flowing in the spacer layer 22 in the lateral direction is reduced compared to the case where the electrode is only provided on the exposed surface 22S, and the operating voltage is also reduced. Furthermore, since the current path formed by the electrode layer 31 and the electrode layer 32 is not provided through the semiconductor DBR layer 21 and the dielectric DBR layer 26, it is not necessary to form both the semiconductor DBR layer 21 and the dielectric DBR layer 26 with a semiconductor doped with impurities. As a result, the loss caused by free carrier absorption in the semiconductor DBR layer 21 and the dielectric DBR layer 26 can be reduced. Therefore, high efficiency and low voltage can be achieved.

In this embodiment, the electrode layer 31 is formed to be in contact with a portion of the exposed surface 22S and also in contact with a portion of the spacer layer 22 that is deeper than the exposed surface 22S. Thus, compared with the case where the electrode is provided only on the exposed surface 22S, the density of the current flowing in the spacer layer 22 in the lateral direction is reduced, and the operating voltage is also reduced. In addition, since the current path formed by the electrode layer 31 and the electrode layer 32 is provided without passing through the semiconductor DBR layer 21 and the dielectric DBR layer 26, it is not necessary to form both the semiconductor DBR layer 21 and the dielectric DBR layer 26 with a semiconductor doped with impurities. As a result, the loss caused by free carrier absorption in the semiconductor DBR layer 21 and the dielectric DBR layer 26 can be reduced. Therefore, high efficiency and low voltage can be achieved.

In this embodiment, the electrode layer 31 has a structure in which Ti, Pt, and Au are sequentially layered from the inner surface side of the recess 22A. Ti is in contact with the inner surface of the recess 22A and is in ohmic contact with the inner surface of the recess 22A (spacer layer 22). Pt prevents impurities contained in the spacer layer 22 from diffusing to Au. Au improves the bonding property between the electrode layer 31 and the solder. This can achieve low voltage.

In this embodiment, the spacer layers 22, 24, and 25 are formed of an InP-based semiconductor, the semiconductor DBR layer 21 is formed of a non-doped semiconductor, and the dielectric DBR layer 26 is formed of a dielectric. This can reduce the loss caused by free carrier absorption in the semiconductor DBR layer 21 and the dielectric DBR layer 26. Therefore, high efficiency can be achieved.

In this embodiment, the semiconductor DBR layer 21 and the dielectric DBR layer 26 are configured so that the laser light L is emitted from the dielectric DBR layer 26 side. Thus, a top-emission type laser can be realized.

In this embodiment, the mesa portion 20A is provided. Thus, the electrode layer 31 can be formed near the tunnel junction layer. As a result, a lower voltage can be achieved.

<2. Variations of the first embodiment> [Variation A] In the above embodiment, the electrode layer 31 may include, for example, a metal layer 31a in which Ti, Pt, and Au are sequentially layered from the inner surface side of the recess 22A, and a coating layer 31b formed on the metal layer 31a, as shown in FIG. 15. In this case, the TAT (Turn Around Time) of the electrode layer 31 can be shortened compared to the case where the electrode layer 31 is composed entirely of the metal layer 31a.

[Variation B] In the above-mentioned embodiment, the electrode layer 31 may have a diffused metal region 31c and an alloy metal layer 31d as shown in FIG16. The alloy metal layer 31d is in contact with the exposed surface 22S, and is, for example, a layer in which AuGe, Ni, and Au are sequentially layered from the exposed surface 22S side. The alloy metal layer 31d may be, for example, a layer in which Pd and Ge are sequentially layered from the exposed surface 22S side. The diffused metal region 31c is a portion of the spacer layer 22 that is deeper than the exposed surface 22S and is in contact with the alloy metal layer 31d. The diffused metal region 31c is formed, for example, by heating the alloy metal layer 31d formed on the exposed surface 22S at a predetermined temperature, so that the Ge contained in the alloy metal layer 31d diffuses to a portion of the spacer layer 22 deeper than the exposed surface 22S. In this case, the spacer layer 22 does not need to be etched to form the recess 22A, thereby reducing the operating voltage. As a result, low voltage can be achieved.

[Variation C] In the above-mentioned variation B, the electrode layer 31 may further have a metal layer 31e as shown in FIG. 17, for example. The metal layer 31e is formed on the alloy metal layer 31d and is made of a material different from that of the alloy metal layer 31d. The metal layer 31e is, for example, a laminated body in which Ti, Pt, and Au are sequentially layered from the side of the alloy metal layer 31d. In this case, a low voltage can be achieved.

[Variation D] In the above-mentioned embodiment and its variation, the exposed surface 22S can be formed in the same plane as the interface between the active layer 23 and the spacer layer 22. In this variation, the exposed surface 22S is formed in the same plane as the interface between the active layer 23 and the spacer layer 22, as shown in FIG. 18, for example. In this case, the distance of the current path can be shortened compared to the above-mentioned embodiment, so that low voltage can be achieved.

[Variation E] In the above-mentioned embodiment and its variation, the electrode layer 31 can be formed in an annular region surrounding the electrode layer 32 in a top view. In this variation, the electrode layer 31 is in an annular shape surrounding the electrode layer 32 in a top view, as shown in, for example, FIG. 19 and FIG. 20. FIG. 19 shows an example of a cross-sectional structure of the surface-emitting laser 1 of this variation. FIG. 20 shows an example of an upper surface structure of the surface-emitting laser 1 described in FIG. 19. Thus, compared with the above-mentioned embodiment, the density of the current flowing in the lateral direction in the spacer layer 22 is further reduced, and the operating voltage is also further reduced. As a result, further low voltage can be achieved.

[Variation F] In the above-mentioned embodiment and its variation, the cross-sectional shape of the recess 22A in the lamination direction can be a right pyramid shape. In this variation, the cross-sectional shape of the recess 22A in the lamination direction can be a right pyramid shape as shown in FIG. 21, for example. At this time, the portion of the electrode layer 31 that embeds the recess 22A is a shape that reverses the shape of the recess 22A. In this case, as in the above-mentioned embodiment and its variation, the density of the current flowing in the lateral direction in the spacer layer 22 is reduced, and the operating voltage is also reduced. As a result, low voltage can be achieved.

[Variation G] In the above-mentioned embodiment and its variation, the shape of the recess 22A may be a mortar shape. In this variation, the shape of the recess 22A may be a mortar shape, as shown in FIG. 22 . At this time, the portion of the electrode layer 31 that embeds the recess 22A is a shape that reverses the shape of the recess 22A. In this case, as in the above-mentioned embodiment and its variation, the density of the current flowing in the lateral direction in the spacer layer 22 is reduced, and the operating voltage is also reduced. As a result, low voltage can be achieved.

[Variation H] In the above-mentioned embodiment and its variation, the tunnel junction layer can be formed in a region surrounded by a region made high in resistance by ion implantation in the vertical resonator structure 20 in a top view. In this variation, as shown in FIG. 23, for example, the tunnel junction layer TJ can be formed in a region surrounded by a region 33 made high in resistance by ion implantation in the vertical resonator structure 20 (high-concentration p-layer 28 and high-concentration n-layer 29) in a top view.

In the region 33, due to the reduction of carrier concentration caused by ion injection, the tunnel junction formed by the high-concentration p-layer 28 and the high-concentration n-layer 29 disappears. As a result, the resistance of the region 33 is greater than the resistance of the tunnel junction layer TJ. The type of ions injected into the region 33 can be specifically set to O ions, N ions, B ions, H ions, He ions, etc. Among them, O ions can oxidize the region 33, which is more preferable.

Thus, in this variation, the current confinement structure is formed by ion implantation. In this case, the etching of the high-concentration p-layer 28 and the high-concentration n-layer 29 in the above-mentioned embodiment can be omitted.

[Variation I] In the above variation, the region 33 may be formed across the region from the upper surface of the spacer layer 25 to the spacer layer 22. In the above variation H, the region 33 may be formed across the region from the upper surface of the spacer layer 25 to the spacer layer 22 as shown in FIG. 24. In this case, a transparent conductive layer 34 may be provided instead of the contact layer 27. The transparent conductive layer 34 is disposed between the dielectric DBR layer 26 and the spacer layer 25, and is connected to the portion of the upper surface of the spacer layer 25 surrounded by the region 33, and is connected to the electrode layer 32. The transparent conductive layer 34 is electrically connected to the spacer layer 25 and the electrode layer 32, and constitutes a part of the current path of the surface emitting laser 1.

The transparent conductive layer 34 is made of, for example, an indium-based transparent conductive material, a tin-based transparent conductive material, or a zinc-based transparent conductive material. Examples of the indium-based transparent conductive material include indium-tin oxide (including ITO, indium tin oxide (Indium Tin Oxide), In ₂ O ₃ doped with Sn, crystalline ITO, and amorphous ITO), indium-zinc oxide (IZO, indium zinc oxide (Indium Zinc Oxide)), indium-gallium oxide (IGO), indium-doped gallium-zinc oxide (IGZO, In-GaZnO ₄ ), IFO (In ₂ O ₃ doped with F), ITiO (In ₂ O ₃ doped with Ti), InSn, or InSnZnO. Examples of tin-based transparent conductive materials include tin oxide (SnO ₂ ), ATO (Sb-doped SnO ₂ ), and FTO (F-doped SnO ₂ ). Examples of zinc-based transparent conductive materials include zinc oxide (including ZnO, Al-doped ZnO (AZO) or B-doped ZnO), Ga-doped zinc oxide (GZO), and AlMgZnO (aluminum oxide and magnesium oxide-doped zinc oxide).

Thus, in this variation, a transparent conductive layer 34 is provided which is electrically connected to the spacer layer 25 and the electrode layer 32. Thus, even when the region 33 is formed from the upper surface of the spacer layer 25 to the region of the spacer layer 22, current can be injected into the surface emitting laser 1.

[Variation J] In the above-mentioned embodiment and its variation, as shown in FIG. 25 , a dielectric DBR layer 35 may be provided instead of the semiconductor DBR layer 21.

The dielectric DBR layer 35 is formed by alternately laminating a low refractive index dielectric layer formed of a first dielectric material and a high refractive index dielectric layer formed of a second dielectric material. The optical thicknesses of the low refractive index dielectric layer and the high refractive index dielectric layer are, for example, λ ₀ × 1/4, respectively. The low refractive index dielectric layer is formed of, for example, SiO _2. The high refractive index dielectric layer is formed of, for example, Ta ₂ O _5. The material of the dielectric DBR layer 35 is not limited to the above-mentioned dielectric materials. The material of the dielectric DBR layer 35 may be a material different from that of the dielectric DBR layer 26, or may be a material common to the dielectric DBR layer 26.

Thus, in this variation, the dielectric DBR layer 35 is provided. This can reduce the loss caused by free carrier absorption in the dielectric DBR layer 35. Therefore, high efficiency and low voltage can be achieved.

[Variation K] In the above-mentioned variation J, as shown in FIG. 26, a reflective metal layer 36 may be provided to contact the dielectric DBR layer 35 on the opposite side to the active layer 23. The reflective metal layer 36 corresponds to the end of the reflector on the dielectric DBR layer 35 side when viewed from the active layer 23. The reflective metal layer 36 is a layer that assists the function of the dielectric DBR layer 35 and helps reduce the logarithm of the dielectric DBR layer 35. The reflective metal layer 36 is composed of, for example, gold (Au), silver (Ag) or aluminum (Al). The film thickness of the reflective metal layer 36 is, for example, 20 nm or more.

Thus, in this variation, the reflective metal layer 36 is provided. This can reduce the number of pairs of the dielectric DBR layer 35, thereby shortening the TAT (Turn Around Time) of the surface emitting laser 1 compared to the case where the reflective metal layer 36 is not provided.

[Variation L] In the above-mentioned embodiment and its variations A to I, as shown in FIG. 27 , a substrate 40 and a semiconductor DBR layer 41 may be provided instead of the substrate 10 and the semiconductor DBR layer 21.

The substrate 40 is a crystal growth substrate used when epitaxially growing the semiconductor DBR layer 41. In this variation, the substrate 40 can be omitted. The substrate 40 is an n-type GaAs substrate. In the n-type GaAs substrate, silicon (Si) or the like is contained as an n-type impurity. The semiconductor DBR layer 41 is a non-doped GaAs-based semiconductor DBR layer. The semiconductor DBR layer 41 is formed by alternatingly laminating a low-refractive-index semiconductor layer containing non-doped AlAs and a high-refractive-index semiconductor layer containing non-doped GaAs. The optical thicknesses of the low-refractive-index semiconductor layer and the high-refractive-index semiconductor layer are, for example, λ ₀ ×1/4, respectively.

In this variation, the substrate 40 formed with the semiconductor DBR layer 41 is bonded with the surface of the semiconductor DBR layer 41 facing the spacer layer 22. Here, the semiconductor DBR layer 41 is not included in the current path. Therefore, a semiconductor DBR layer 41 corresponding to the size and purpose of the oscillation wavelength λ ₀ can be bonded.

[Variation M] In the above-mentioned embodiment and its variations A to J and L, the surface-emitting laser 1 may be a back-emitting laser having a light emitting surface 1S provided on the back side. In this variation, the surface-emitting laser 1 is configured to emit laser light L having an oscillation wavelength λ ₀ from the semiconductor DBR layer 21 side, as shown in FIG. 28 , for example. Specifically, in the vertical resonator structure 20, the logarithm and reflectivity of the reflective mirror on the semiconductor DBR layer 21 side and the logarithm and reflectivity of the reflective mirror on the dielectric DBR layer 26 side may be configured to emit laser light L having an oscillation wavelength λ ₀ from the semiconductor DBR layer 21 side. Even in the case of such a configuration, the same effects as those of the above-mentioned embodiment and its variations A to J and L can be obtained.

[Variation N] In the above-mentioned variation M, as shown in FIG. 29, for example, a dielectric DBR layer 35 may be provided instead of the substrate 10 and the semiconductor DBR layer 21. Even in such a configuration, the same effect as that of the above-mentioned variation M can be obtained.

[Variation O] In the above-mentioned variation M, as shown in FIG. 30, for example, a semiconductor DBR layer 41 may be provided instead of the substrate 10 and the semiconductor DBR layer 21. Even in the case of this configuration, the same effect as that of the above-mentioned variation M can be obtained.

[Variation P] In the above-mentioned embodiment and its variations A to J, L to O, a reflective metal layer 37 may be provided in contact with the dielectric DBR layer 26 on the opposite side of the active layer 23, as shown in FIG. 31 . The reflective metal layer 37 corresponds to the end of the reflector on the dielectric DBR layer 26 side when viewed from the active layer 23. The reflective metal layer 37 is a layer that assists the function of the dielectric DBR layer 26 and helps reduce the logarithm of the dielectric DBR layer 26. The reflective metal layer 37 is composed of, for example, gold (Au), silver (Ag) or aluminum (Al). The film thickness of the reflective metal layer 37 is, for example, 20 nm or more.

Thus, in this variation, the reflective metal layer 37 is provided. This can reduce the number of pairs of the dielectric DBR layer 26, and improve the heat dissipation performance of the surface emitting laser 1 compared to the case where the reflective metal layer 37 is not provided.

<3. Second Implementation Form> [Structure] The second implementation form of the surface emitting laser 2 of the present disclosure is described. FIG. 32 shows an example of a cross-sectional structure of the surface emitting laser 2. FIG. 33 shows an example of an upper surface structure of the surface emitting laser 2.

In this embodiment, in the first embodiment and variations A to L, a groove portion 20B is provided in place of the mesa portion 20A in the vertical resonator structure 20. An exposed surface 22S is formed on the bottom surface of the groove portion 20B. Even in the case of this configuration, the same effects as those of the first embodiment and variations A to L can be obtained.

<4. Variation of the Second Embodiment> [Variation Q] In the second embodiment, the surface emitting laser 2 may be a back-emitting laser having a light emitting surface 1S provided on the back. In this variation, the surface emitting laser 2 is configured to emit laser light L having an oscillation wavelength λ ₀ from the semiconductor DBR layer 21 side, as shown in FIG. 34 . Even in this configuration, the same effect as in the second embodiment can be obtained.

In the above, a plurality of embodiments and variations thereof are cited to illustrate the present disclosure, but the present disclosure is not limited to the above embodiments and variations thereof, and various variations are possible. In addition, the effects described in this specification are ultimately for illustration only. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

Furthermore, for example, the present disclosure may adopt the following structure. (1) A surface emitting laser, comprising: A first DBR (Distributed Bragg Reflector) layer; A second DBR layer; An active layer disposed between the first DBR layer and the second DBR layer; A first spacer layer of the first conductivity type disposed between the active layer and the first DBR layer; A second spacer layer of the second conductivity type disposed between the active layer and the second DBR layer; A tunneling junction layer disposed between the active layer and the second DBR layer; A first electrode layer electrically connected to the first spacer layer without passing through the first DBR layer; and The second electrode layer is electrically connected to the second spacer layer without passing through the second DBR layer; and the first spacer layer has a flat exposed surface in a region not opposite to the tunnel junction layer; the first electrode layer is formed to be in contact with a portion of the first spacer layer that is deeper than the exposed surface. (2) A surface emitting laser as in (1), wherein the first spacer layer has a recess in the exposed surface; and the first electrode layer is formed to bury the recess. (3) A surface emitting laser as in (1) or (2), wherein the first electrode layer is formed to be in contact with a portion of the exposed surface and also in contact with a portion of the first spacer layer that is deeper than the exposed surface. (4) A surface emitting laser as in (2), wherein the first electrode layer has a structure in which Ti, Pt, and Au are sequentially layered from the inner surface side of the recess. (5) A surface emitting laser as in (2), wherein the first electrode layer has: a metal layer in which Ti, Pt, and Au are sequentially layered from the inner surface side of the recess, and a coating layer formed on the metal layer. (6) A surface emitting laser as in (1) or (3), wherein the first electrode layer has: an alloy metal layer in contact with the exposed surface; and a diffused metal region in the first spacer layer that is deeper than the exposed surface and in contact with the alloy metal layer. (7) A surface emitting laser as in (6), wherein the first electrode layer further comprises a metal layer formed on the alloy metal layer and made of a material different from the alloy metal layer. (8) A surface emitting laser as in any one of (1) to (7), wherein the exposed surface and the interface between the active layer and the first spacer layer are formed in the same plane. (9) A surface emitting laser as in any one of (1) to (8), wherein the first electrode layer is formed in an annular region surrounding the second electrode layer in a plan view. (10) A surface emitting laser as in (2), wherein the cross-sectional shape of the recess in the stacking direction is a right pyramidal shape. (11) The surface emitting laser as described in (2), wherein the shape of the concave portion is a mortar shape. (12) The surface emitting laser as described in any one of (1) to (11), comprising a laminated structure including the first spacer layer, the active layer, the tunneling junction layer and the second spacer layer; and the tunneling junction layer is formed in a region surrounded by a region that has been made highly resistive by ion implantation into the laminated structure in a top view. (13) The surface emitting laser as described in any one of (1) to (12), further comprising a transparent conductive layer, which is disposed between the second spacer layer and the second DBR layer and is electrically connected to the second electrode. (14) A surface emitting laser as described in any one of (1) to (13), wherein the first spacer layer and the second spacer layer contain an InP semiconductor; and the first DBR layer is a non-doped semiconductor DBR layer; and the second DBR layer is a dielectric DBR layer. (15) A surface emitting laser as described in any one of (1) to (13), wherein the first spacer layer and the second spacer layer contain an InP semiconductor; and the first DBR layer and the second DBR layer are dielectric DBR layers. (16) A surface emitting laser as described in (15), further comprising a reflective metal layer in contact with the first DBR layer on the side opposite to the active layer. (17) A surface emitting laser as described in any one of (1) to (13), wherein the first spacer layer and the second spacer layer are composed of InP semiconductors; and the first DBR layer is a non-doped GaAs semiconductor DBR layer; and the second DBR layer is a dielectric DBR layer. (18) A surface emitting laser as described in any one of (1) to (17), wherein the first DBR layer and the second DBR layer are configured to emit laser light from the side of the second DBR layer. (19) A surface emitting laser as described in any one of (1) to (17), further comprising a reflective metal layer in contact with the second DBR layer on the side opposite to the active layer. (20) A surface emitting laser as described in any one of (1) to (19), comprising a mesa portion, the mesa portion comprising at least the aforementioned active layer, the aforementioned tunneling junction layer and the aforementioned second spacer layer. (21) A surface emitting laser as described in any one of (1) to (19), comprising a laminated structure comprising the aforementioned first DBR layer, the aforementioned first spacer layer, the aforementioned active layer, the aforementioned tunneling junction layer, the aforementioned second spacer layer and the aforementioned second DBR layer; and the aforementioned laminated structure further comprises a groove portion having the aforementioned exposed surface as a bottom surface; the aforementioned first electrode layer is formed to be in contact with a portion of the aforementioned first spacer layer that is deeper than the aforementioned exposed surface in the aforementioned groove portion.

In a surface emitting laser of one embodiment of the present disclosure, a first spacer layer disposed between an active layer and a first DBR layer is provided with a flat exposed surface in a region not facing the tunnel junction layer. Furthermore, a first electrode layer is formed to be in contact with a portion of the first spacer layer that is deeper than the exposed surface. Thus, compared with a case where the first electrode is provided only on the exposed surface, the density of the current flowing in the first spacer layer in the lateral direction is reduced, and the operating voltage is also reduced. Furthermore, since the current path formed by the first electrode layer and the second electrode layer is provided without passing through the first DBR layer and the second DBR layer, for example, it is not necessary to form both the first DBR layer and the second DBR layer with a doped semiconductor. For example, both the first DBR layer and the second DBR layer can be formed with a non-doped semiconductor or a dielectric. Furthermore, for example, the first DBR layer can be formed with a non-doped semiconductor and the second DBR layer can be formed with a dielectric. As a result, the loss caused by free carrier absorption in the first DBR layer and the second DBR layer can be reduced. Therefore, high efficiency and low voltage can be achieved.

1,2,100: Surface emitting laser 1S: Light emitting surface 10: Substrate 20: Vertical resonator structure 20A: Terrane 20B: Groove 21,41: Semiconductor DBR layer 22,24,25: Spacer layer 22A: Recess 22S: Exposed surface 23: Active layer 26,35: Dielectric DBR layer 27: Contact layer 28: High concentration p layer 29: High concentration n layer 31,32,131: Electrode layer 31a,31e: Metal layer 31b: Cladding layer 31c: Diffused metal region 31d: Alloy metal layer 33: Region 34: Transparent conductive layer 36,37: Reflective metal layer 40: Substrate L: Laser light TJTJ: Tunneling junction layer

FIG. 1 is a diagram showing an example of a cross-sectional structure of a surface-emitting laser of the first embodiment of the present disclosure. FIG. 2 is a diagram showing an example of an upper surface structure of the surface-emitting laser of FIG. 1. FIG. 3 is a diagram showing an example of a method for manufacturing the surface-emitting laser of FIG. 1. FIG. 4 is a diagram showing an example of a manufacturing process that is continuous with FIG. 3. FIG. 5 is a diagram showing an example of a manufacturing process that is continuous with FIG. 4. FIG. 6 is a diagram showing an example of a manufacturing process that is continuous with FIG. 5. FIG. 7 is a diagram showing an example of a manufacturing process that is continuous with FIG. 6. FIG. 8 is a diagram showing an example of a manufacturing process that is continuous with FIG. 7. FIG. 9 is a diagram showing an example of a manufacturing process that is continuous with FIG. 8. FIG. 10 is a diagram showing an example of a manufacturing process that is continuous with FIG. 9. FIG. 11 is a diagram showing an example of a manufacturing process that is continuous with FIG. 10. FIG. 12 is a diagram showing an example of a cross-sectional configuration of a surface-emitting laser of a comparative example. FIG. 13 is a diagram showing an example of a relationship between carrier concentration and sheet resistance. FIG. 14 is a diagram showing an example of I-V characteristics of a surface-emitting laser of an embodiment and a comparative example. FIG. 15 is a diagram showing an example of a variation of the cross-sectional configuration of the surface-emitting laser of FIG. 1. FIG. 16 is a diagram showing an example of a variation of the cross-sectional configuration of the surface-emitting laser of FIG. 1. FIG. 17 is a diagram showing an example of a variation of the cross-sectional configuration of the surface-emitting laser of FIG. 1. FIG. 18 is a diagram showing a variation of the cross-sectional configuration of the surface emitting laser of FIG. 1 . FIG. 19 is a diagram showing a variation of the cross-sectional configuration of the surface emitting laser of FIG. 1 . FIG. 20 is a diagram showing an example of the upper surface configuration of the surface emitting laser of FIG. 19 . FIG. 21 is a diagram showing a variation of the cross-sectional configuration of the surface emitting laser of FIG. 1 . FIG. 22 is a diagram showing a variation of the cross-sectional configuration of the surface emitting laser of FIG. 1 . FIG. 23 is a diagram showing a variation of the cross-sectional configuration of the surface emitting laser of FIG. 1 . FIG. 24 is a diagram showing a variation of the cross-sectional configuration of the surface emitting laser of FIG. 1 . FIG. 25 is a diagram showing a variation of the cross-sectional configuration of the surface emitting laser of FIG. 1 . FIG. 26 is a diagram showing a variation of the cross-sectional structure of the surface emitting laser of FIG. 1. FIG. 27 is a diagram showing a variation of the cross-sectional structure of the surface emitting laser of FIG. 1. FIG. 28 is a diagram showing a variation of the cross-sectional structure of the surface emitting laser of FIG. 1. FIG. 29 is a diagram showing a variation of the cross-sectional structure of the surface emitting laser of FIG. 1. FIG. 30 is a diagram showing a variation of the cross-sectional structure of the surface emitting laser of FIG. 1. FIG. 31 is a diagram showing a variation of the cross-sectional structure of the surface emitting laser of FIG. 1. FIG. 32 is a diagram showing a cross-sectional structure example of the surface emitting laser of the second embodiment of the present disclosure. FIG. 33 is a diagram showing an example of the upper surface structure of the surface emitting laser of FIG. 32. FIG34 is a diagram showing a variation of the cross-sectional structure of the surface-emitting laser of FIG32.

1: Surface emitting laser

1S: Light exit surface

10: Substrate

20: Vertical resonator structure

20A: Countertop

21: Semiconductor DBR layer

22,24,25: Interlayer

22A: Recess

22S: Reveal your face

23: Active layer

26: Dielectric DBR layer

27: Contact layer

28: High concentration p layer

29: High concentration n layers

31,32: Electrode layer

L:Laser light

Claims (21)

A surface emitting laser, comprising: a first DBR (Distributed Bragg Reflector) layer; a second DBR layer; an active layer disposed between the first DBR layer and the second DBR layer; a first spacer layer of the first conductivity type disposed between the active layer and the first DBR layer; a second spacer layer of the second conductivity type disposed between the active layer and the second DBR layer; a tunneling junction layer disposed between the active layer and the second DBR layer; a first electrode layer electrically connected to the first spacer layer without passing through the first DBR layer; and The second electrode layer is electrically connected to the second spacer layer without passing through the second DBR layer; and the first spacer layer has a flat exposed surface in a region not opposite to the tunnel junction layer; the first electrode layer is formed to be in contact with a portion of the first spacer layer that is deeper than the exposed surface. The surface emitting laser of claim 1, wherein the first spacer layer has a recess in the exposed surface; and the first electrode layer is formed to bury the recess. In the surface emitting laser of claim 1, the first electrode layer is formed to be in contact with a portion of the exposed surface and also in contact with a portion of the first spacer layer that is deeper than the exposed surface. The surface emitting laser of claim 2, wherein the first electrode layer has a structure in which Ti, Pt, and Au are sequentially layered on the inner surface side of the concave portion. The surface emitting laser of claim 2, wherein the first electrode layer comprises: a metal layer of Ti, Pt, and Au stacked in sequence from the inner surface side of the recess, and a coating layer formed on the metal layer. The surface emitting laser of claim 1, wherein the first electrode layer comprises: an alloy metal layer in contact with the exposed surface; and a diffused metal region in the first spacer layer which is deeper than the exposed surface and in contact with the alloy metal layer. As in claim 6, the surface emitting laser, wherein the first electrode layer further comprises a metal layer formed on the alloy metal layer and comprising a material different from the alloy metal layer. The surface emitting laser of claim 1, wherein the exposed surface and the interface between the active layer and the first spacer layer are formed in the same plane. As in the surface emitting laser of claim 1, the first electrode layer is formed in an annular region surrounding the second electrode layer in a top view. As in the surface emitting laser of claim 2, the cross-sectional shape of the aforementioned recess in the stacking direction is a right pyramidal shape. As in the surface emitting laser of claim 2, the shape of the aforementioned recess is a pestle-shaped. The surface emitting laser of claim 1 has a laminated structure including the first spacer layer, the active layer, the tunneling junction layer and the second spacer layer; and the tunneling junction layer is formed in a region surrounded by a region that has been made highly resistive by ion implantation into the laminated structure in a top view. The surface emitting laser of claim 1 further comprises a transparent conductive layer, wherein the transparent conductive layer is disposed between the second spacer and the second DBR layer and is electrically connected to the second electrode. The surface emitting laser of claim 1, wherein the first spacer layer and the second spacer layer are composed of InP-based semiconductors; and the first DBR layer is a non-doped semiconductor DBR layer; and the second DBR layer is a dielectric DBR layer. The surface emitting laser of claim 1, wherein the first spacer layer and the second spacer layer are composed of InP semiconductors; and the first DBR layer and the second DBR layer are dielectric DBR layers. The surface emitting laser of claim 15 further comprises a reflective metal layer connected to the first DBR layer on the opposite side of the active layer; and the reflective metal layer, when observed from the active layer, corresponds to the terminal end of the reflective mirror on the first DBR layer side. The surface emitting laser of claim 1, wherein the first spacer layer and the second spacer layer are composed of InP semiconductors; and the first DBR layer is a non-doped GaAs semiconductor DBR layer; and the second DBR layer is a dielectric DBR layer. The surface emitting laser of claim 1, wherein the first DBR layer and the second DBR layer are configured to emit laser light from the side of the second DBR layer. The surface emitting laser of claim 1 further comprises a reflective metal layer connected to the side of the second DBR layer opposite to the active layer; and the reflective metal layer, when observed from the active layer, corresponds to the terminal end of the reflective mirror on the side of the second DBR layer. The surface emitting laser of claim 1 comprises a mesa portion, which at least comprises the active layer, the tunnel junction layer and the second spacer layer. The surface emitting laser of claim 1 has a laminated structure including the first DBR layer, the first spacer layer, the active layer, the tunneling junction layer, the second spacer layer and the second DBR layer; and the laminated structure further includes a groove having the exposed surface as the bottom surface; the first electrode layer is formed to be connected to a portion of the first spacer layer that is deeper than the exposed surface in the groove.