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WO2024119543A1 - 一种dram芯片及其写入补偿方法和存储控制单元 - Google Patents

一种dram芯片及其写入补偿方法和存储控制单元 Download PDF

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Publication number
WO2024119543A1
WO2024119543A1 PCT/CN2022/140172 CN2022140172W WO2024119543A1 WO 2024119543 A1 WO2024119543 A1 WO 2024119543A1 CN 2022140172 W CN2022140172 W CN 2022140172W WO 2024119543 A1 WO2024119543 A1 WO 2024119543A1
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Prior art keywords
voltage
data
written
switch
storage
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PCT/CN2022/140172
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English (en)
French (fr)
Inventor
戴瑾
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北京超弦存储器研究院
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Publication of WO2024119543A1 publication Critical patent/WO2024119543A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of integrated circuit technology, and in particular to a DRAM chip, a write compensation method thereof, and a storage control unit.
  • a DRAM (dynamic random access memory) storage unit in some embodiments, is composed of a capacitor C and a selection MOS (metal oxide semiconductor field effect transistor) tube M1 responsible for switching.
  • a selection MOS metal oxide semiconductor field effect transistor
  • Some embodiments of the present disclosure provide a DRAM chip and a write compensation method and a storage control unit thereof, which can perform voltage compensation on leakage voltage.
  • a DRAM chip which may include a plurality of memory cells and a plurality of write circuits, each memory cell including a capacitor and a transistor; each write circuit is connected to a group of memory cells via a bit line; a parasitic MOS tube exists between two adjacent memory cells sharing the same word line, and the parasitic MOS tube is turned on or off together with the transistor as the potential of the word line changes;
  • Each of the write circuits comprises: a switch component and a plurality of configuration power supply terminals;
  • the switch component is configured to be connected to the bit line, and selects a corresponding configuration power supply terminal to input a corresponding power supply signal into the bit line according to the data to be written into the selected storage cell and the data to be written into two adjacent storage cells of the selected storage cell.
  • the DRAM chip may further include: a write compensation calculation unit;
  • the write compensation calculation unit is configured to receive the data to be stored input by an external device, write each row of the data to be stored into the multiple storage units through the multiple write circuits, and generate a corresponding switch selection signal for each of the write circuits.
  • the multiple configuration power supply terminals include multiple configuration voltage terminals; the multiple configuration voltage terminals provide multiple different first type voltages and multiple different second type voltages; the first type voltage refers to a voltage greater than or equal to a preset first voltage threshold, the second type voltage refers to a voltage less than or equal to a preset second voltage threshold, and the first voltage threshold is greater than the second voltage threshold;
  • Each switch assembly may include: a first switch, a second switch, and a third switch;
  • the first switch is configured to select the second switch to be connected to the bit line, or the third switch to be connected to the bit line, according to the data to be written into the selected memory cell;
  • the switch selection signal includes a signal for controlling the first switch to select the second switch to be connected to the bit line, or a signal for selecting the third switch to be connected to the bit line;
  • the second switch is configured to output different first type voltages according to the storage data of two adjacent memory cells of the selected memory cell after being connected to the bit line;
  • the switch selection signal includes a selection signal of the different first type voltages;
  • the third switch is configured to output different second type voltages according to storage data of two adjacent memory cells of the selected memory cell after being connected to the bit line; and the switch selection signal includes a selection signal of the different second type voltages.
  • the first switch may be configured such that when the data to be written to the selected memory cell is "1", the second switch is selected to be connected to the bit line, and the bit line is connected to the first type voltage; when the data to be written to the selected memory cell is "0", the third switch is selected to be connected to the bit line, and the bit line is connected to the second type voltage;
  • the first type voltage and the second type voltage may respectively include three voltages of different magnitudes
  • the three voltages included in the first type voltage are connected to the first group of input ports of the first switch through the second switch, and the second switch is configured to select one of the three voltages included in the first type voltage to be output according to whether the data to be written into two adjacent storage cells of the selected storage cell is the same as the data to be written into the selected storage cell;
  • the three voltages included in the second type voltage are connected to the second group of input ports of the first switch through the third switch, and the third switch is configured to select one of the three voltages included in the second type voltage for output according to whether the data to be written into two adjacent storage cells of the selected storage cell are the same as the data to be written into the selected storage cell.
  • the memory array may further include an isolation transistor; and each bit line is respectively connected to an isolation transistor.
  • Some embodiments of the present disclosure further provide a write compensation method for a DRAM chip, based on the DRAM chip; the method may include:
  • one of the preset multiple configuration power supply terminals is selected to output a power supply signal.
  • the method may further include:
  • a switch selection signal is obtained, and one of the preset multiple configured power supply terminals is selected to output a power supply signal according to the switch selection signal.
  • the multiple configuration power terminals include multiple configuration voltage terminals; the multiple configuration voltage terminals provide multiple different first type voltages and multiple different second type voltages; the first type voltage refers to a voltage greater than or equal to a preset first voltage threshold, the second type voltage refers to a voltage less than or equal to a preset second voltage threshold, and the first voltage threshold is greater than the second voltage threshold.
  • the first type voltage may include: a first voltage, a second voltage and a third voltage; wherein the first voltage is smaller than the second voltage, and the second voltage is smaller than the third voltage;
  • the step of selecting one of a plurality of preset configuration power supply terminals to output a power supply signal according to the data to be written into the selected storage unit and whether the data to be written into the two storage units are the same as the data to be written into the selected storage unit may include:
  • the bit line input voltage is the third voltage.
  • the second type voltage may include: a fourth voltage, a fifth voltage and a sixth voltage; wherein the fourth voltage is smaller than the fifth voltage, and the fifth voltage is smaller than the sixth voltage;
  • bit line input voltage is a fourth voltage
  • bit line input voltage is the fifth voltage
  • the bit line input voltage is a sixth voltage.
  • Some embodiments of the present disclosure also provide a storage control unit of a DRAM chip, which may include a processor and a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, and when the instructions are executed by the processor, the write compensation method of the DRAM chip is implemented.
  • the DRAM chip of the embodiment of the present disclosure includes multiple storage cells and multiple write circuits, each storage cell includes a capacitor and a transistor; each write circuit is connected to a group of storage cells through a bit line; there is a parasitic MOS tube between two adjacent storage cells in the storage cells sharing the same word line, and the parasitic MOS tube is turned on or off together with the transistor as the word line potential changes; each of the write circuits includes: a switch component and multiple configuration power supply terminals; the switch component is configured to be connected to the bit line, and selects the corresponding configuration power supply terminal according to the data to be written to the selected storage cell and the data to be written to the two adjacent storage cells of the selected storage cell, and inputs the corresponding power supply signal into the bit line, thereby realizing voltage compensation for the leakage voltage.
  • FIG1 is a schematic diagram of a parasitic MOS in a storage array in the related art
  • FIG2 is a schematic diagram of the structure of a storage unit in the related art
  • FIG3 is a schematic diagram of a partial structure of a DRAM chip according to some embodiments of the present disclosure.
  • FIG4 is a schematic diagram of a group of switch components connected to a plurality of configuration voltage terminals in some embodiments of the present disclosure
  • FIG5 is a schematic diagram of connecting multiple groups of switch components to multiple configuration voltage terminals in some embodiments of the present disclosure
  • FIG6 is a schematic diagram of a partial structure of a memory array including an isolation transistor according to some embodiments of the present disclosure
  • FIG7 is a flow chart of a write compensation method for a storage array according to some embodiments of the present disclosure.
  • FIG. 8 is a block diagram of the storage control unit of the storage array according to some embodiments of the present disclosure.
  • the specification may have presented the method and/or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be appreciated by those of ordinary skill in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and/or process should not be limited to the steps performed in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.
  • the gate of the MOS tube M1 is connected to form a word line WL.
  • all storage cells on a word line must be opened, and parallel reading and writing are performed on different bit lines BL.
  • Some types of 3D-DRAM three-dimensional dynamic random access memory have parasitic MOS tubes M2 due to the manufacturing process, which generates leakage between adjacent storage capacitors when the word line is opened.
  • the structural feature of the transistor is that different regions of the word line WL in the vertical direction are correspondingly provided with different transistors M1 (for example, M1-1, M1-2, M1-3, M1-4, M1-5, M1-6), and the semiconductor layer S is shared, resulting in the presence of parasitic MOS (M2) between adjacent MOS tubes M1. If the semiconductor layer S between the two transistors M1 is disconnected, there is no parasitic MOS.
  • the embodiment of the present disclosure is to solve the problem of parasitic MOS between adjacent MOS tubes M1 when the semiconductor layer S is shared.
  • the embodiment of the present disclosure provides a DRAM chip 1, as shown in FIG3, which may include a plurality of storage cells 11 and a plurality of write circuits 12, each storage cell 11 including a transistor 111 and a capacitor 112; each write circuit 12 is connected to a group of storage cells 11 via a bit line (such as BL1, BL2, BL3, ..., BLn, etc.); a parasitic MOS tube exists between two adjacent storage cells sharing the same word line WL1, and the parasitic MOS tube is turned on or off together with the transistor as the potential of the word line changes;
  • a bit line such as BL1, BL2, BL3, ..., BLn, etc.
  • Each of the write circuits 12 comprises: a switch component 121 and a plurality of configuration power supply terminals 122;
  • the switch component 121 is configured to be connected to the bit lines (such as BL1, BL2, BL3, ..., BLn, etc.), and selects the corresponding configuration power supply terminal to input the corresponding power supply signal into the bit lines (such as BL1, BL2, BL3, ..., BLn, etc.) according to the data to be written into any of the storage cells 11 selected for writing data and the data to be written into two adjacent storage cells of the selected storage cell 11.
  • the bit lines such as BL1, BL2, BL3, ..., BLn, etc.
  • turning on or off together may refer to turning on or off at the same time, or may refer to turning on or off the parasitic MOS and the transistor together when the word line potential changes.
  • the parasitic MOS and the transistor are currently turned off, and when the word line potential changes, the parasitic MOS and the transistor are turned on; when the word line potential changes again, the parasitic MOS and the transistor are turned off.
  • the multiple configuration power supply terminals 122 may include multiple configuration voltage terminals; the multiple configuration voltage terminals provide multiple different first type voltages and multiple different second type voltages; the first type voltage refers to a voltage greater than or equal to a preset first voltage threshold, the second type voltage refers to a voltage less than or equal to a preset second voltage threshold, and the first voltage threshold is greater than the second voltage threshold.
  • the multiple configuration power supply terminals 122 may include multiple configuration current terminals; the multiple configuration current terminals provide multiple different first type currents and multiple different second type currents; the first type current refers to a current greater than or equal to a preset first current threshold, the second type current refers to a current less than or equal to a preset second voltage threshold, and the first current threshold is greater than the second current threshold.
  • the embodiment of the present disclosure is described below by taking the multiple configuration power supply terminals 122 including multiple configuration voltage terminals as an example.
  • the transistor 111 includes a first electrode P1, a second electrode P2 and a third electrode P3, wherein the first electrode P1 is a first gate; the capacitor 112 includes a first end and a second end; wherein the first gate in each storage cell 11 is connected to the first word line WL1, the second electrode P2 in each storage cell 11 is respectively connected to a bit line BL (for example, BL1, BL2, BL3, ..., BLn), the third electrode P3 in each storage cell 11 is connected to the first end of the capacitor 112 of each storage cell 11, and the second end of the capacitor 112 is set to an input reference voltage end (the detailed type of the reference voltage is related to whether the transistor 111 is an N-type transistor or a P-type transistor).
  • the reference voltage can be a reference zero voltage, that is, the second end of the capacitor 112 can be grounded.
  • a switch component 121 is connected to each bit line BL of the DRAM chip. Through the switch component 121, different configuration voltages can be input according to different situations, thereby achieving the effect of compensating for leakage voltage.
  • the data to be written into the storage cell 11 may be "1" or "0", and the data to be written into two adjacent storage cells may also be “1" or "0". Since the data to be written into the selected storage cell 11 is different and the data to be written into the two adjacent storage cells of the selected storage cell is different, the voltages to be compensated are different. Therefore, corresponding configuration voltages may be input according to different combinations of the data to be written into the storage cell 11 and the data to be written into the two adjacent storage cells, so that the configuration voltage can compensate for the leakage voltage without the voltage being too large.
  • the DRAM chip may further include: a write compensation calculation unit;
  • the write compensation calculation unit may be configured to receive data to be stored input from an external device, write each row of data to be stored into the multiple storage units through the multiple write circuits, and generate a corresponding switch selection signal for each of the write circuits.
  • the switch component 121 may be an integrated chip or may be composed of a switch circuit.
  • the detailed structure and composition of the switch component 121 are not limited here and may be defined according to different application scenarios.
  • the detailed components of the switch component 121 are not limited in detail, and may include but are not limited to MOS tubes and/or logic circuits, etc.
  • each switch component 121 may include: a first switch 1211, a second switch 1212, and a third switch 1213; the first switch 1211, the second switch 1212, and the third switch 1213 are all multiple-choice switches;
  • the first switch 1211 is configured to select the second switch 1212 to be connected to the bit line BL, or the third switch 1213 to be connected to the bit line BL, according to the data to be written to the selected memory cell 11;
  • the switch selection signal includes a signal for controlling the first switch to select the second switch to be connected to the bit line, or a signal for selecting the third switch to be connected to the bit line;
  • the second switch 1212 is configured to output different first type voltages according to the storage data of two adjacent memory cells of the selected memory cell after being connected to the bit line BL; the switch selection signal includes a selection signal of the different first type voltages;
  • the third switch 1213 is configured to output different second type voltages according to the storage data of two adjacent memory cells of the selected memory cell after being connected to the bit line BL; the switch selection signal includes a selection signal of the different second type voltages.
  • the first switch 1211 is configured to select the second switch 1212 to be connected to the bit line BL when the data to be written to the selected memory cell 11 is "1", and the bit line BL is connected to the first type voltage; when the data to be written to the selected memory cell 11 is "0", the third switch 1213 is selected to be connected to the bit line BL, and the bit line BL is connected to the second type voltage;
  • the first type voltage and the second type voltage may respectively include three voltages of different magnitudes
  • the three voltages included in the first type voltage are connected to the first group of input ports of the first switch 1211 through the second switch 1212, and the second switch 1212 is configured to select one of the three voltages included in the first type voltage to be output according to whether the data to be written to two storage cells adjacent to the selected storage cell 11 is the same as the data to be written to the storage cell 11;
  • the three voltages included in the second type voltage are connected to the second group of input ports of the first switch 1211 through the third switch 1213, and the third switch 1213 is configured to select one of the three voltages included in the second type voltage for output according to whether the data to be written into two storage cells adjacent to the selected storage cell 11 is the same as the data to be written into the storage cell 11.
  • the second switch 1212 when the data to be written into the storage unit 11 is "1", the second switch 1212 is selected to be connected to the bit line BL, and when the data to be written into the storage unit 11 is "0", the third switch 1213 is selected to be connected to the bit line BL; and vice versa.
  • the first type voltage and the second type voltage can be defined according to different application scenarios, and the detailed voltages are not limited here.
  • the first type voltage can be a high voltage
  • the second type voltage can be a low voltage.
  • the second switch 1212 when the data to be written into the selected memory cell 11 is "1", the second switch 1212 can be selected to be connected to the bit line BL, a high voltage can be input to the bit line BL, and different high voltages can be output according to the different storage data of two adjacent memory cells of the selected memory cell; when the data to be written into the selected memory cell 11 is "0", the third switch 1213 can be selected to be connected to the bit line BL, a low voltage can be input to the bit line BL, and different low voltages can be output according to the different storage data of two adjacent memory cells of the selected memory cell.
  • the second switch 1212 when the data to be written into the selected memory cell 11 is "0", the second switch 1212 may be selected to be connected to the bit line BL, a high voltage may be input to the bit line BL, and different high voltages may be output according to the different storage data of the two memory cells adjacent to the selected memory cell 11; or when the data to be written into the selected memory cell 11 is "1", the third switch 1213 may be selected to be connected to the bit line BL, a low voltage may be input to the bit line BL, and different low voltages may be output according to the different storage data of the two memory cells adjacent to the selected memory cell 11.
  • the data that need to be written into the two storage cells adjacent to the selected storage cell 11 may be "1" or "0", and there are the following three situations: the data that need to be written into the two storage cells adjacent to the selected storage cell 11 are both "0", the data that need to be written into the two storage cells adjacent to the selected storage cell 11 is one "0" and the other "1", and the data that need to be written into the two storage cells adjacent to the selected storage cell 11 are both "1".
  • the corresponding bit line input voltage can be a normal input voltage V_1; at this time, if the data to be written into the two storage cells adjacent to the selected storage cell 11 is both "1", and the leakage between the selected storage cell 11 and the two storage cells is small, then the corresponding bit line input voltage can be a normal input voltage V_1; at this time, if the data to be written into the two storage cells adjacent to the selected storage cell 11 is both "1", and the leakage between the selected storage cell 11 and the two storage cells is small, then the corresponding bit line input voltage can be a normal input voltage V_1 when the data written into the selected storage cell 11 is "1".
  • the storage data of the two adjacent storage cells to the selected storage cell are "0" and "1” respectively, and the possibility of the selected storage cell 11 leaking to the adjacent storage cell storing the data "0" increases. Therefore, when the data written to the selected storage cell 11 is "1", the corresponding bit line input voltage can be increased to a higher input voltage V_1+ (V_1+ is greater than V_1); at this time, if the data to be written to the two adjacent storage cells to the selected storage cell are both "0", the possibility of the selected storage cell 11 leaking to the two storage cells increases. Therefore, when the data written to the selected storage cell 11 is "1", the write voltage can be increased to a higher input voltage V_1++ (V_1++ is greater than V_1+).
  • the corresponding bit line input voltage can be a low voltage V_0-- with a relatively high absolute value; at this time, if the data to be written into the two storage cells adjacent to the selected storage cell is one "0" and the other "1", then only the adjacent storage cell that needs to write the data "1" to the selected storage cell 11 will be input to the selected storage cell 11.
  • the data leakage of the storage cell 11 is relatively large. Therefore, when the data written to the selected storage cell 11 is "0", the corresponding bit line input voltage can be reduced to a low voltage V_0- with a slightly higher absolute value (V_0-- is less than V_0-, and the absolute value of V_0-- is greater than the absolute value of V_0-); at this time, if the data to be written to the two storage cells adjacent to the selected storage cell are both "0", the probability of the two storage cells leaking to the selected storage cell 11 is reduced again.
  • V_0 is less than V_0
  • V_0 the absolute value of V_0
  • the leakage voltage compensation can be achieved through the above scheme.
  • the entire row is also read out during the DRAM read operation, and then the read data is written back.
  • the embodiment of the present disclosure can also be applied.
  • the switch component 121 can be connected to the sense amplifier to receive the write data amplified by the sense amplifier (i.e., the data that the storage unit needs to write back again), that is, the write data this time is provided by the output end of the sense amplifier, and the switch component 121 can also select the required input voltage input bit line BL according to the write data (i.e., the data that the aforementioned selected storage unit needs to write), thereby performing voltage compensation on the input voltage and writing the read data back to the storage unit.
  • the memory array may further include an isolation transistor 13 ; each bit line BL is respectively connected to an isolation transistor 13 ;
  • the isolation transistor 13 may include: a fourth electrode P4, a fifth electrode P5 and a sixth electrode P6; the fourth electrode P4 is a second gate;
  • each isolation transistor 13 is connected to the second word line WL2, and the fifth electrode P5 and the sixth electrode P6 of each isolation transistor 13 are connected in series to the connected bit line BL (for example, may include BL1, BL2, BL3, ..., BLn);
  • each transistor 111 is connected to the second word line WL1 , and the second electrode P2 and the third electrode P3 of each transistor 111 are connected in series to the connected bit line BL (eg, may include BL1 , BL2 , BL3 , . . . , BLn).
  • bit line BL eg, may include BL1 , BL2 , BL3 , . . . , BLn).
  • the bit line BL of the DRAM needs to pass through an isolation transistor (e.g., an isolation MOS tube) before being connected to the read/write circuit, and this isolation transistor also has the same parasitic MOS problem.
  • an isolation transistor e.g., an isolation MOS tube
  • the embodiment of the present disclosure can also be used, and the detailed compensation voltage can be adjusted accordingly according to the needs.
  • the embodiment of the present disclosure further provides a write compensation method for a DRAM chip, based on the DRAM chip; as shown in FIG7 , the method may include steps S101-S103:
  • S102 selecting one of a plurality of preset configured power supply terminals to output a power supply signal according to the data to be written into the selected storage unit and whether the data to be written into the two storage units are the same as the data to be written into the selected storage unit.
  • one of the three voltages included in the first type voltage can be selected for output, or one of the three voltages included in the second type voltage can be selected for output, based on the data that needs to be written to the selected storage cell and whether the data that need to be written to the two storage cells adjacent to the selected storage cell are the same as the data that need to be written to the selected storage cell.
  • the method may further include: before selecting one of the preset multiple configured power supply terminals to output the power signal, obtaining a switch selection signal, and selecting one of the preset multiple configured power supply terminals to output the power signal according to the switch selection signal.
  • one of three voltages included in the first type voltage is selected for output according to the switch selection signal, or one of three voltages included in the second type voltage is selected for output.
  • the data to be written into the selected memory cell may be "1" or "0"
  • the type of the bit line input voltage may include a high voltage and a low voltage.
  • the input voltage of the bit line may be controlled to be a high voltage or a low voltage.
  • a high voltage may be input into the bit line BL
  • a low voltage may be input into the bit line BL
  • the storage data of two storage cells adjacent to a selected storage cell may be "1" or "0", and there are the following three situations: the data to be written into the two storage cells adjacent to the selected storage cell are both "0", the data to be written into the two storage cells adjacent to the selected storage cell are one "0" and the other "1", and the data to be written into the two storage cells are both "1".
  • high voltages of different magnitudes may be input, or low voltages of different magnitudes may be input, respectively.
  • the first type voltage may include: a first voltage, a second voltage and a third voltage; wherein the first voltage is lower than the second voltage, and the second voltage is lower than the third voltage.
  • selecting one of the preset multiple configuration power supply terminals to output a power supply signal may include:
  • the third voltage output is selected.
  • the corresponding bit line input voltage can be a normal input voltage V_1 (i.e., the first voltage); at this time, if the data to be written into the two storage cells adjacent to the selected storage cell is one "0" and the other "1", the selected storage cell 11 writes the data to the storage cell 11.
  • the second type voltage may include: a fourth voltage, a fifth voltage and a sixth voltage; wherein the fourth voltage is lower than the fifth voltage, and the fifth voltage is lower than the sixth voltage.
  • selecting one of the preset multiple configuration power supply terminals to output a power supply signal may also include:
  • the corresponding bit line input voltage is a low voltage (or negative voltage): at this time, if the data to be written into the two storage cells adjacent to the selected storage cell 11 are both "1", and the leakage of these two storage cells to the selected storage cell 11 is relatively large, then when the data written into the selected storage cell 11 is "0", the corresponding bit line input voltage can be a low voltage V_0-- with a relatively high absolute value; at this time, if the data to be written into the two storage cells adjacent to the selected storage cell is one "0" and the other "1", then only the adjacent storage cell that needs to write the data "1" to the selected storage cell will be written to the adjacent storage cell.
  • V_0-- is less than V_0-
  • V_0-- is greater than the absolute value of V_0-
  • V_0 is less than V_0
  • V_0 the absolute value of V_0
  • the leakage voltage compensation can be achieved through the above scheme.
  • the embodiment of the present disclosure also provides a storage control unit 2 of a DRAM chip, as shown in FIG8 , which may include a processor 21 and a computer-readable storage medium 22 , wherein the computer-readable storage medium 22 stores instructions, and when the instructions are executed by the processor 21 , the write compensation method of the DRAM chip is implemented.
  • any of the aforementioned embodiments of the write compensation method for the DRAM chip can be applied to the embodiment of the storage control unit 2, and will not be described one by one here.
  • Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium).
  • a computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data).
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer.
  • communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

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Abstract

本公开实施例公开了一种DRAM芯片及其写入补偿方法和存储控制单元，该DRAM芯片包括多个存储单元（11）和多个写入电路（12），每个存储单元（11）包括一个晶体管（111）和一个电容（112）；每个写入电路通过一条位线与一组存储单元（11）相连；共用同一字线的存储单元（11）中相邻的两个存储单元（11）之间存在寄生MOS管（M2），寄生MOS管（M2）随着字线电位的变化与晶体管（11）一起打开或关闭；每个写入电路（12）包括：一个开关组件（121）和多个配置电源端（122）；开关组件（121）设置为与位线相连，根据被选中的存储单元（11）需要写入的数据以及所述被选中的存储单元（11）的两个相邻存储单元（11）需要写入的数据选择相应的配置电源端（122）将对应的电源信号输入位线。

Description

一种DRAM芯片及其写入补偿方法和存储控制单元 技术领域
本公开实施例涉及但不限于集成电路技术领域，尤指一种DRAM芯片及其写入补偿方法和存储控制单元。
背景技术
DRAM(动态随机存取内存)存储单元，在一些实施例中由一个电容C和一个负责开关的选择MOS(金属氧化物半导体场效应晶体管)管M1组成。
发明概述
以下是对本文详细描述的主题的概述，本概述并非是为了限制权利要求的保护范围。
本公开一些实施例提供了一种DRAM芯片及其写入补偿方法和存储控制单元，能够对漏电电压进行电压补偿。
本公开一些实施例提供了一种DRAM芯片，可以包括多个存储单元和多个写入电路，每个存储单元包括一个电容和一个晶体管；每个写入电路通过一条位线与一组存储单元相连；共用同一字线的存储单元中相邻的两个存储单元之间存在寄生MOS管，所述寄生MOS管随着字线电位的变化与所述晶体管一起打开或关闭；
每个所述写入电路包括：一个开关组件和多个配置电源端；
所述开关组件，设置为与所述位线相连，根据被选中的存储单元需要写入的数据以及所述被选中的存储单元的两个相邻存储单元需要写入的数据选择相应的配置电源端将对应的电源信号输入所述位线。
在本公开一些示例性实施例中，所述DRAM芯片还可以包括：写补偿计算单元；
所述写补偿计算单元，设置为接收外部设备输入的待存储数据，将每行待存储数据通过所述多个写入电路写入所述多个存储单元，并对于每个所述 写入电路产生相应的开关选择信号。
在本公开一些示例性实施例中，所述多个配置电源端包括多个配置电压端；所述多个配置电压端提供多个不同的第一类型电压和多个不同的第二类型电压；所述第一类型电压是指大于或等于预设的第一电压阈值的电压，所述第二类型电压是指小于或等于预设的第二电压阈值的电压，所述第一电压阈值大于所述第二电压阈值；
每个开关组件可以包括：第一开关、第二开关和第三开关；
所述第一开关，设置为根据所述被选中的存储单元需要写入的数据选择所述第二开关与所述位线相连，或者所述第三开关与所述位线相连；所述开关选择信号包括控制所述第一开关选择所述第二开关与所述位线相连的信号，或者选择所述第三开关与所述位线相连的信号；
所述第二开关，设置为在与所述位线连接后，根据所述被选中的存储单元的两个相邻存储单元的存储数据输出不同的第一类型电压；所述开关选择信号包括所述不同的第一类型电压的选择信号；
所述第三开关，设置为在与所述位线连接后，根据所述被选中的存储单元的两个相邻存储单元的存储数据输出不同的第二类型电压；所述开关选择信号包括所述不同的第二类型电压的选择信号。
在本公开一些示例性实施例中，所述第一开关，可以设置为当所述被选中的存储单元需要写入的数据为“1”时，选择所述第二开关与所述位线相连，所述位线接通所述第一类型电压；当所述被选中的存储单元的存储单元需要写入的数据为“0”时，选择所述第三开关与所述位线相连，所述位线接通所述第二类型电压；
所述第一类型电压和所述第二类型电压分别可以包括三个不同大小的电压；
所述第一类型电压包含的三个电压通过所述第二开关连接到所述第一开关的第一组输入端口，所述第二开关设置为根据所述被选中的存储单元的两个相邻的存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，在所述第一类型电压包含的三个电压中择一输出；
所述第二类型电压包含的三个电压通过所述第三开关连接到所述第一开关的第二组输入端口，所述第三开关设置为根据所述被选中的存储单元的两个相邻的存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，在所述第二类型电压包含的三个电压中择一输出。
在本公开一些示例性实施例中，所述的存储阵列还可以包括隔离晶体管；每条位线上分别连接有一个隔离晶体管。
本公开一些实施例还提供了一种DRAM芯片的写入补偿方法，基于所述的DRAM芯片；所述方法可以包括：
获取被选中的存储单元需要写入的数据，以及与所述被选中的存储单元共用一个字线的两个存储单元需要写入的数据，其中，所述两个存储单元分别与所述被选中的存储单元相邻；
根据所述被选中的存储单元需要写入的数据，以及所述两个存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，从预设的多个配置电源端中择一输出电源信号。
在本公开一些示例性实施例中，所述方法还可以包括：
在从预设的多个配置电源端中择一输出电源信号之前，获取开关选择信号，根据所述开关选择信号从预设的多个配置电源端中择一输出电源信号。
在本公开一些示例性实施例中，所述多个配置电源端包括多个配置电压端；所述多个配置电压端提供多个不同的第一类型电压和多个不同的第二类型电压；所述第一类型电压是指大于或等于预设的第一电压阈值的电压，所述第二类型电压是指小于或等于预设的第二电压阈值的电压，所述第一电压阈值大于所述第二电压阈值。
在本公开一些示例性实施例中，所述第一类型电压可以包括：第一电压、第二电压和第三电压；其中，所述第一电压小于所述第二电压，所述第二电压小于所述第三电压；
所述根据所述被选中的存储单元需要写入的数据，以及所述两个存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，从预设的多个配置电源端中择一输出电源信号，可以包括：
当所述被选中的存储单元需要写入的数据为“1”时：
如果所述两个存储单元需要写入的数据均为“1”，选择第一电压输出；
如果所述两个存储单元中一个存储单元需要写入的数据为“1”，另一个存储单元需要写入的数据为“0”，选择第二电压输出；
如果所述两个存储单元需要写入的数据均为0，所述位线输入电压为第三电压。
在本公开一些示例性实施例中，所述第二类型电压可以包括：第四电压、第五电压和第六电压；其中，所述第四电压小于所述第五电压，所述第五电压小于所述第六电压；
当所述被选中的存储单元需要写入的数据为“0”时：
如果所述两个存储单元需要写入的数据均为“1”，所述位线输入电压为第四电压；
如果所述两个存储单元中一个存储单元需要写入的数据为“1”，另一个存储单元的存储数据为“0”，所述位线输入电压为第五电压；
如果所述两个存储单元的存储数据均为“0”，所述位线输入电压为第六电压。
本公开一些实施例还提供了一种DRAM芯片的存储控制单元，可以包括处理器和计算机可读存储介质，所述计算机可读存储介质中存储有指令，当所述指令被所述处理器执行时，实现所述的DRAM芯片的写入补偿方法。
本公开一些实施例的有益效果包括：本公开实施例的DRAM芯片包括多个存储单元和多个写入电路，每个存储单元包括一个电容和一个晶体管；每个写入电路通过一条位线与一组存储单元相连；共用同一字线的存储单元中相邻的两个存储单元之间存在寄生MOS管，所述寄生MOS管随着字线电位的变化与所述晶体管一起打开或关闭；每个所述写入电路包括：一个开关组件和多个配置电源端；所述开关组件，设置为与所述位线相连，根据被选中的存储单元需要写入的数据以及所述被选中的存储单元的两个相邻存储单元需要写入的数据选择相应的配置电源端将对应的电源信号输入所述位线，实现了对漏电电压进行电压补偿。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为相关技术中存储阵列中的寄生MOS示意图；
图2为相关技术中存储单元间的结构示意图；
图3为本公开一些实施例的DRAM芯片局部结构示意图；
图4为本公开一些实施例的一组开关组件与多个配置电压端相连的示意图；
图5为本公开一些实施例的多组开关组件与多个配置电压端相连的示意图；
图6为本公开一些实施例的包括隔离晶体管的存储阵列局部结构示意图；
图7为本公开一些实施例的存储阵列的写入补偿方法流程图；
图8为本公开一些实施例的存储阵列的存储控制单元组成框图。
详述
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说显而易见的是，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在详细实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合， 以形成由权利要求限定的独特的发明方案。任何实施例的任何特征或元件也可以与来自其它发明方案的特征或元件组合，以形成另一个由权利要求限定的独特的发明方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
此外，在描述具有代表性的实施例时，说明书可能已经将方法和/或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法和/或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开实施例的精神和范围内。
如图1所示，MOS管M1的栅极连接成字线WL，读写时必须打开一条字线上的所有存储单元，在不同的位线BL上进行并行读写。某些类型的3D-DRAM(三维动态随机存取内存)因为制造工艺，存在寄生MOS管M2，在字线打开时产生相邻存储电容之间的漏电。如图2所示，该晶体管的结构特点是垂直方向的字线WL的不同区域对应设置有不同的晶体管M1(例如M1-1、M1-2、M1-3、M1-4、M1-5、M1-6)，且半导体层S共用，导致相邻MOS管M1之间存在寄生MOS(M2)，如果两个晶体管M1之间的半导体层S断开是不存在寄生MOS的。本公开实施例要解决的就是半导体层S共用情况下相邻MOS管M1之间存在寄生MOS的问题。
本公开实施例提供了一种DRAM芯片1，如图3所示，可以包括多个存储单元11和多个写入电路12，每个存储单元11包括一个晶体管111和一个电容112；每个写入电路12通过一条位线(如BL1、BL2、BL3、…、BLn等)与一组存储单元11相连；共用同一字线WL1的存储单元中相邻的两个存储单元之间存在寄生MOS管，所述寄生MOS管随着字线电位的变化与所述晶体管一起打开或关闭；
每个所述写入电路12包括：一个开关组件121和多个配置电源端122；
所述开关组件121，设置为与所述位线(如BL1、BL2、BL3、…、BLn等)相连，根据任意的被选中写入数据的所述存储单元11需要写入的数据以及被选中的存储单元11的两个相邻存储单元需要写入的数据选择相应的配置电源端将对应的电源信号输入所述位线(如BL1、BL2、BL3、…、BLn等)。
在本公开的示例性实施例中，一起打开或关闭，可以是指同时打开或关闭，或者可以是指字线电位变化时，寄生MOS和晶体管一同打开或一同关闭。比如目前寄生MOS和晶体管是关闭的，当字线电位变化，寄生MOS和晶体管改为打开；当字线电位再次变化，寄生MOS和晶体管改为关闭。
在本公开的示例性实施例中，所述多个配置电源端122可以包括多个配置电压端；所述多个配置电压端提供多个不同的第一类型电压和多个不同的第二类型电压；所述第一类型电压是指大于或等于预设的第一电压阈值的电压，所述第二类型电压是指小于或等于预设的第二电压阈值的电压，所述第一电压阈值大于所述第二电压阈值。或者，所述多个配置电源端122可以包括多个配置电流端；所述多个配置电流端提供多个不同的第一类型电流和多个不同的第二类型电流；所述第一类型电流是指大于或等于预设的第一电流阈值的电流，所述第二类型电流是指小于或等于预设的第二电压阈值的电流，所述第一电流阈值大于所述第二电流阈值。
在本公开的示例性实施例中，下文中以所述多个配置电源端122包括多个配置电压端为例说明本公开实施例方案。
在本公开的示例性实施例中，所述晶体管111包括第一极P1、第二极P2和第三极P3，所述第一极P1为第一栅极；所述电容112包括第一端和第二端；其中，每个存储单元11中的所述第一栅极均与第一字线WL1相连，每个存储单元11中的所述第二极P2分别与一条位线BL(例如，BL1、BL2、BL3、…、BLn)相连，每个存储单元11中的所述第三极P3与每个存储单元11的所述电容112的第一端相连，所述电容112的第二端设置为输入参考电压端(该参考电压的详细类型与晶体管111为N型晶体管或P型晶体管有关)，例如，当晶体管111为N型晶体管时该参考电压可以为参考零电压， 即电容112的第二端可以接地。
在本公开的示例性实施例中，由于寄生MOS的存在，在DRAM芯片的每条位线BL上连接开关组件121，通过开关组件121可以实现根据不同的情况输入不同的配置电压，从而达到补偿漏电电压的效果。
在本公开的示例性实施例中，存储单元11需要写入的数据可能为“1”或“0”，两个相邻存储单元需要写入的数据也可能为“1”或“0”，由于被选中的存储单元11需要写入的数据不同，该被选中的存储单元的两个相邻存储单元需要写入的数据不同，使得需要补偿的电压不同，因此，可以根据存储单元11需要写入的数据和两个相邻存储单元需要写入的数据的不同组合情况分别输入相应的配置电压，从而使得该配置电压能够对漏电电压进行补偿，电压又不会过大。
在本公开的示例性实施例中，所述DRAM芯片还可以包括：写补偿计算单元；
所述写补偿计算单元，可以设置为接收外部设备输入的待存储数据，将每行待存储数据通过所述多个写入电路写入所述多个存储单元，并对于每个所述写入电路产生相应的开关选择信号。
在本公开的示例性实施例中，开关组件121可以为集成芯片，也可以由开关电路组成，在此对于开关组件121的详细结构和组成不做限定，可以根据不同的应用场景自行定义。
在本公开的示例性实施例中，对于开关组件121的详细组件也不做详细限定，可以包括但不限于MOS管和/或逻辑电路等。
在本公开的示例性实施例中，下面给出开关组件121的一种实施例。
在本公开的示例性实施例中，如图4、图5所示(其中图4为一组开关组件121与多个配置电压端相连的示意图，图5为多组开关组件121与多个配置电压端122相连的示意图，其中不同的配置电压端122-1、122-2、122-3、122-4、122-5、122-6分别输出不同的电压)，每个开关组件121可以包括：第一开关1211、第二开关1212和第三开关1213；所述第一开关1211、所述第二开关1212和所述第三开关1213均为多选一开关；
所述第一开关1211，设置为根据所述被选中的存储单元11需要写入的数据选择所述第二开关1212与所述位线BL相连，或者所述第三开关1213与所述位线BL相连；所述开关选择信号包括控制所述第一开关选择所述第二开关与所述位线相连的信号，或者选择所述第三开关与所述位线相连的信号；
所述第二开关1212，设置为在与所述位线BL连接后，根据所述被选中的存储单元的两个相邻存储单元的存储数据输出不同的第一类型电压；所述开关选择信号包括所述不同的第一类型电压的选择信号；
所述第三开关1213，设置为在与所述位线BL连接后，根据所述被选中的存储单元的两个相邻存储单元的存储数据输出不同的第二类型电压；所述开关选择信号包括所述不同的第二类型电压的选择信号。
在本公开的示例性实施例中，所述第一开关1211，设置为当所述被选中的存储单元11需要写入的数据为“1”时，选择所述第二开关1212与所述位线BL相连，所述位线BL接通所述第一类型电压；当所述被选中的存储单元11需要写入的数据为“0”时，选择所述第三开关1213与所述位线BL相连，所述位线BL接通所述第二类型电压；
所述第一类型电压和所述第二类型电压可以分别包括三个不同大小的电压；
所述第一类型电压包含的三个电压通过所述第二开关1212连接到所述第一开关1211的第一组输入端口，所述第二开关1212设置为根据与被选中的存储单元11相邻的两个存储单元需要写入的数据是否与存储单元11需要写入的数据相同，在所述第一类型电压包含的三个电压中择一输出；
所述第二类型电压包含的三个电压通过所述第三开关1213连接到所述第一开关1211的第二组输入端口，所述第三开关1213设置为根据与被选中的存储单元11相邻的两个存储单元需要写入的数据是否与存储单元11需要写入的数据相同，在所述第二类型电压包含的三个电压中择一输出。
在本公开的示例性实施例中，例如，可以在所述存储单元11需要写入的数据为“1”时选择所述第二开关1212与所述位线BL相连，在所述存储单 元11需要写入的数据为“0”时选择所述第三开关1213与所述位线BL相连；反之亦可。
在本公开的示例性实施例中，第一类型电压和第二类型电压可以根据不同的应用场景自行定义，在此对于详细电压不做限定。例如，该第一类型电压可以为高电压，该第二类型电压可以为低电压。
在本公开的示例性实施例中，根据晶体管类型不同，可以在所述被选中的存储单元11需要写入的数据为“1”时，选择所述第二开关1212与所述位线BL相连，向位线BL输入高电压，并且根据被选中的存储单元的两个相邻存储单元的存储数据的不同可以输出不同的高电压；可以在所述被选中的存储单元11需要写入的数据为“0”时，选择所述第三开关1213与所述位线BL相连，向位线BL输入低电压，并且根据被选中的存储单元的两个相邻存储单元的存储数据的不同可以输出不同的低电压。
在本公开的示例性实施例中，根据晶体管类型不同，也可以在所述被选中的存储单元11需要写入的数据为“0”时，选择所述第二开关1212与所述位线BL相连，向位线BL输入高电压，并且根据与被选中的存储单元11相邻的两个存储单元的存储数据的不同可以输出不同的高电压；也可以在所述被选中的存储单元11需要写入的数据为“1”时，选择所述第三开关1213与所述位线BL相连，向位线BL输入低电压，并且根据与被选中的存储单元11相邻的两个存储单元的存储数据的不同可以输出不同的低电压。
在本公开的示例性实施例中，与被选中的存储单元11相邻的两个存储单元需要写入的数据可能为“1”或“0”，存在以下三种情况：与被选中的存储单元11相邻的两个存储单元需要写入的数据均为“0”，与被选中的存储单元11相邻的两个存储单元需要写入的数据一个为“0”，另一个为“1”，与被选中的存储单元11相邻的两个存储单元需要写入的数据均为“1”。
在本公开的示例性实施例中，如果所述被选中的存储单元11需要写入的数据为“1”，且对应的位线输入电压为高电压：此时如果与被选中的存储单元11相邻的两个存储单元需要写入的数据均为“1”，该被选中的存储单元11与这两个存储单元之间的漏电较少，则该被选中的存储单元11写入数据为“1”时对应的位线输入电压可以为一个正常的输入电压V_1；此时如果与 被选中的存储单元相邻的这两个存储单元的存储数据一个为“0”，另一个为“1”，该被选中的存储单元11向存储数据为“0”的相邻存储单元漏电的可能性增加，因此，该被选中的存储单元11写入数据为“1”时对应的位线输入电压可以增加为一个较高的输入电压V_1+(V_1+大于V_1)；此时如果与被选中的存储单元相邻的这两个存储单元需要写入的数据均为“0”，该被选中的存储单元11向这两个存储单元漏电的可能性增加，因此，该被选中的存储单元11写入数据为“1”时的写入电压可以增加为一个更高的输入电压V_1++(V_1++大于V_1+)。
在本公开的示例性实施例中，如果所述被选中的存储单元11需要写入的数据为0，且对应的位线输入电压为低电压(或称负电压)：此时如果与被选中的存储单元11相邻的两个存储单元需要写入的数据均为“1”，这两个存储单元向该被选中的存储单元11漏电的数据较大，则该被选中的存储单元11写入数据为“0”时对应的位线输入电压可以为一个绝对值较高的低电压V_0--；此时如果与被选中的存储单元相邻的这两个存储单元需要写入的数据一个为“0”，另一个为“1”，则只有需要写入数据为“1”的相邻存储单元向该被选中的存储单元11漏电的数据较大，因此，该被选中的存储单元11写入数据为“0”时对应的位线输入电压可以降低为一个绝对值稍高的低电压V_0-(V_0--小于V_0-，V_0--的绝对值大于V_0-的绝对值)；此时如果与被选中的存储单元相邻的这两个存储单元需要写入的数据均为“0”时，这两个存储单元向该被选中的存储单元11漏电的几率再次减小，因此，该被选中的存储单元11写入数据为“0”时对应的位线输入电压可以降低为一个正常的低电压V_0(V_0-小于V_0，V_0-的绝对值大于V_0的绝对值)。
在本公开的示例性实施例中，通过以上方案可以实现度漏电电压的补偿。
在本公开的示例性实施例中，DRAM读操作时同样是整行读出，之后要写回所读出的数据，当再次写回读取的数据时同样可以应用本公开实施例方案。在执行读操作时，读完数据之后，开关组件121可以与读出放大器连接，从而接收读出放大器放大后的写入数据(即存储单元需再次写回的数据)，即此次写入数据由读出放大器的输出端提供，开关组件121同样可以根据该写入数据(即前述的被选中的存储单元需要写入的数据)选择所需的输入电 压输入位线BL，从而对输入电压进行电压补偿，将读取数据再写回到存储单元。
在本公开的示例性实施例中，如图6所示，所述的存储阵列还可以包括隔离晶体管13；每条位线BL上分别连接有一个隔离晶体管13；
所述隔离晶体管13可以包括：第四极P4、第五极P5和第六极P6；所述第四极P4为第二栅极；
每个隔离晶体管13的所述第二栅极均与第二字线WL2相连，每个隔离晶体管13的所述第五极P5和所述第六极P6串联于所连接的位线BL(例如，可以包括BL1、BL2、BL3、…、BLn)上；
每个晶体管111的所述第一栅极均与第二字线WL1相连，每个晶体管111的所述第二极P2和所述第三极P3串联于所连接的位线BL(例如，可以包括BL1、BL2、BL3、…、BLn)上。
在本公开的示例性实施例中，有时DRAM的位线BL在连接到读写电路之前需要通过一个隔离晶体管(例如隔离MOS管)，而这个隔离晶体管也有同样的寄生MOS问题。在这个场景下，本公开实施例方案同样可以使用，详细的补偿电压可以根据需求进行相应调整。
本公开实施例还提供了一种DRAM芯片的写入补偿方法，基于所述的DRAM芯片；如图7所示，所述方法可以包括步骤S101-S103：
S101、获取被选中的存储单元需要写入的数据，以及与所述被选中的存储单元共用一个字线的两个存储单元需要写入的数据，其中，所述两个存储单元分别与所述被选中的存储单元相邻；
S102、根据所述被选中的存储单元需要写入的数据，以及所述两个存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，从预设的多个配置电源端中择一输出电源信号。
在本公开的示例性实施例中，当所述多个配置电源端包括多个配置电压端时，可以根据所述被选中的存储单元需要写入的数据，以及与被选中的存储单元相邻的所述两个存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，从第一类型电压包含的三个电压中择一输出，或者， 从第二类型电压包含的三个电压中择一输出。
在本公开的示例性实施例中，所述方法还可以包括：在从预设的多个配置电源端中择一输出电源信号之前，获取开关选择信号，根据所述开关选择信号从预设的多个配置电源端中择一输出电源信号。
在本公开的示例性实施例中，例如，根据所述开关选择信号选择从第一类型电压包含的三个电压中择一输出，或者，从所述第二类型电压包含的三个电压中择一输出。
在本公开的示例性实施例中，被选中的存储单元需要写入的数据可以为“1”，也可以为“0”；所述位线输入电压的类型可以包括高电压和低电压。根据被选中的存储单元需要写入的数据为“1”或“0”，可以控制输入所述位线的输入电压为高电压或低电压。
在本公开的示例性实施例中，被选中的存储单元需要写入的数据为“1”时，控制输入所述位线的输入电压为高电压还是低电压，可以根据所选用的晶体管的类型(例如N型或P型)来确定，在此不做详细限定。同理，被选中的存储单元需要写入的数据为“0”时，控制输入所述位线的输入电压为高电压还是低电压，可以根据所选用的晶体管的类型(例如N型或P型)来确定，在此不做详细限定。
在本公开的示例性实施例中，例如，可以在被选中的存储单元需要写入的数据为“1”时，向位线BL输入高电压，在被选中的存储单元需要写入的数据为“0”时，向位线BL输入低电压。
在本公开的示例性实施例中，与被选中的存储单元相邻的两个存储单元的存储数据可能为“1”或“0”，存在以下三种情况：该与被选中的存储单元相邻的两个存储单元需要写入的数据均为“0”，该与被选中的存储单元相邻的两个存储单元需要写入的数据一个为“0”，另一个为“1”，该两个存储单元需要写入的数据均为“1”。
在本公开的示例性实施例中，根据以上三种情况，可以分别输入不同大小的高电压，或输入不同大小的低电压。
在本公开的示例性实施例中，所述第一类型电压可以包括：第一电压、 第二电压和第三电压；其中，所述第一电压小于所述第二电压，所述第二电压小于所述第三电压。
在本公开的示例性实施例中，根据所述被选中的存储单元需要写入的数据，以及与被选中的存储单元相邻的两个存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，从预设的多个配置电源端中择一输出电源信号，可以包括：
当所述被选中的存储单元需要写入的数据为“1”时：
如果与所述被选中的存储单元相邻的所述两个存储单元需要写入的数据均为“1”，选择所述第一电压输出；
如果所述两个存储单元中一个存储单元需要写入的数据为“1”，另一个存储单元需要写入的数据为“0”，选择所述第二电压输出；
如果所述两个存储单元需要写入的数据均为“0”时，选择所述第三电压输出。
在本公开的示例性实施例中，如果被选中的存储单元11需要写入的数据为“1”，且对应的位线输入电压为高电压：此时如果与被选中的存储单元11相连的两个存储单元需要写入的数据均为“1”，被选中的存储单元11与这两个存储单元之间的漏电较少，则被选中的存储单元写入数据为“1”时对应的位线输入电压可以为一个正常的输入电压V_1(即第一电压)；此时如果与被选中的存储单元相邻的这两个存储单元需要写入的数据一个为“0”，另一个为“1”，被选中的存储单元11向存储数据为“0”的相邻存储单元漏电的可能性增加，因此，被选中的存储单元11写入数据为“1”时对应的位线输入电压可以增加为一个较高的输入电压V_1+(即第二电压，其中V_1+大于V_1)；此时如果与被选中的存储单元相邻的这两个存储单元需要写入的数据均为“0”，被选中的存储单元11向相邻的两个存储单元漏电的可能性增加，因此，被选中的存储单元11写入数据为“1”时对应的位线输入电压可以增加为一个更高的输入电压V_1++(即第三电压，其中V_1++大于V_1+)。
在本公开的示例性实施例中，所述第二类型电压可以包括：第四电压、 第五电压和第六电压；其中，所述第四电压小于所述第五电压，所述第五电压小于所述第六电压。
在本公开的示例性实施例中，根据所述被选中的存储单元需要写入的数据，以及与被选中的存储单元相邻的所述两个存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，从预设的多个配置电源端中择一输出电源信号，还可以包括：
当所述被选中的存储单元需要写入的数据为“0”时：
如果与所述被选中的存储单元相邻的所述两个存储单元需要写入的数据均为“1”，选择所述第四电压输出；
如果所述两个存储单元中一个存储单元需要写入的数据为“1”，另一个存储单元需要写入的数据为“0”，选择所述第五电压输出；
如果所述两个存储单元需要写入的数据均为“0”，选择所述第六电压输出。
在本公开的示例性实施例中，如果被选中的存储单元11需要写入的数据为“0”，且对应的位线输入电压为低电压(或称负电压)：此时如果与被选中的存储单元11相邻的两个存储单元需要写入的数据均为“1”，这两个存储单元向被选中的存储单元11漏电的数据较大，则被选中的存储单元11写入数据为“0”时对应的位线输入电压可以为一个绝对值较高的低电压V_0--；此时如果与被选中的存储单元相邻的这两个存储单元需要写入的数据一个为“0”，另一个为“1”，则只有需要写入数据为“1”的相邻存储单元向该被选中的存储单元11漏电的数据较大，因此，被选中的存储单元11写入数据为“0”时对应的位线输入电压可以降低为一个绝对值稍高的低电压V_0-(V_0--小于V_0-，V_0--的绝对值大于V_0-的绝对值)；此时如果与被选中的存储单元相邻的这两个存储单元需要写入的数据均为“0”时，这两个存储单元向被选中的存储单元11漏电的几率再次减小，因此，被选中的存储单元11写入数据为“0”时对应的位线输入电压可以降低为一个正常的低电压V_0(V_0-小于V_0，V_0-的绝对值大于V_0的绝对值)。
在本公开的示例性实施例中，通过以上方案可以实现度漏电电压的补偿。
本公开实施例还提供了一种DRAM芯片的存储控制单元2，如图8所示，可以包括处理器21和计算机可读存储介质22，所述计算机可读存储介质22中存储有指令，当所述指令被所述处理器21执行时，实现所述的DRAM芯片的写入补偿方法。
在本公开的示例性实施例中，前述的DRAM芯片的写入补偿方法实施例中的任意实施例均可以适用于该存储控制单元2实施例中，在此不再一一赘述。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。

Claims (10)

  1. 一种DRAM芯片，包括多个存储单元和多个写入电路，每个存储单元包括一个电容和一个晶体管；每个写入电路通过一条位线与一组存储单元相连；共用同一字线的存储单元中相邻的两个存储单元之间存在寄生MOS管，所述寄生MOS管随着字线电位的变化与所述晶体管一起打开或关闭；
    每个所述写入电路包括：一个开关组件和多个配置电源端；
    所述开关组件，设置为与所述位线相连，根据被选中的存储单元需要写入的数据以及所述被选中的存储单元的两个相邻存储单元需要写入的数据选择相应的配置电源端将对应的电源信号输入所述位线。
  2. 根据权利要求1所述的DRAM芯片，还包括：写补偿计算单元；
    所述写补偿计算单元，设置为接收外部设备输入的待存储数据，将每行待存储数据通过所述多个写入电路写入所述多个存储单元，并对于每个所述写入电路产生相应的开关选择信号。
  3. 根据权利要求2所述的DRAM芯片，其中，所述多个配置电源端包括多个配置电压端；所述多个配置电压端提供多个不同的第一类型电压和多个不同的第二类型电压；所述第一类型电压是指大于或等于预设的第一电压阈值的电压，所述第二类型电压是指小于或等于预设的第二电压阈值的电压，所述第一电压阈值大于所述第二电压阈值；
    每个开关组件包括：第一开关、第二开关和第三开关；
    所述第一开关，设置为根据所述被选中的存储单元需要写入的数据选择所述第二开关与所述位线相连，或者所述第三开关与所述位线相连；所述开关选择信号包括控制所述第一开关选择所述第二开关与所述位线相连的信号，或者选择所述第三开关与所述位线相连的信号；
    所述第二开关，设置为在与所述位线连接后，根据所述被选中的存储单元的两个相邻存储单元的存储数据输出不同的第一类型电压；所述开关选择信号包括所述不同的第一类型电压的选择信号；
    所述第三开关，设置为在与所述位线连接后，根据所述被选中的存储单元的两个相邻存储单元的存储数据输出不同的第二类型电压；所述开关选择 信号包括所述不同的第二类型电压的选择信号。
  4. 根据权利要求3所述的DRAM芯片，其中，
    所述第一开关，设置为当所述被选中的存储单元需要写入的数据为1时，选择所述第二开关与所述位线相连，所述位线接通所述第一类型电压；当所述被选中的存储单元需要写入的数据为0时，选择所述第三开关与所述位线相连，所述位线接通所述第二类型电压；
    所述第一类型电压和所述第二类型电压分别包括三个不同大小的电压；
    所述第一类型电压包含的三个电压通过所述第二开关连接到所述第一开关的第一组输入端口，所述第二开关设置为根据所述被选中的存储单元的两个相邻的存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，在所述第一类型电压包含的三个电压中择一输出；
    所述第二类型电压包含的三个电压通过所述第三开关连接到所述第一开关的第二组输入端口，所述第三开关设置为根据所述被选中的存储单元的两个相邻的存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，在所述第二类型电压包含的三个电压中择一输出。
  5. 根据权利要求1-4任意一项所述的DRAM芯片，还包括隔离晶体管；每条位线上分别连接有一个隔离晶体管。
  6. 一种DRAM芯片的写入补偿方法，其特征在于，基于权利要求1-5任意一项所述的DRAM芯片；所述方法包括：
    获取被选中的存储单元需要写入的数据，以及与所述被选中的存储单元共用一个字线的两个存储单元需要写入的数据，其中，所述两个存储单元分别与所述被选中的存储单元相邻；
    根据所述被选中的存储单元需要写入的数据，以及所述两个存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，从预设的多个配置电源端中择一输出电源信号。
  7. 根据权利要求6所述的DRAM芯片的写入补偿方法，还包括：
    在从预设的多个配置电源端中择一输出电源信号之前，获取开关选择信号，根据所述开关选择信号从预设的多个配置电源端中择一输出电源信号。
  8. 根据权利要求6所述的DRAM芯片的写入补偿方法，其中，所述多个配置电源端包括多个配置电压端；所述多个配置电压端提供多个不同的第一类型电压和多个不同的第二类型电压；所述第一类型电压是指大于或等于预设的第一电压阈值的电压，所述第二类型电压是指小于或等于预设的第二电压阈值的电压，所述第一电压阈值大于所述第二电压阈值；
    所述第一类型电压包括：第一电压、第二电压和第三电压；其中，所述第一电压小于所述第二电压，所述第二电压小于所述第三电压；
    所述根据所述被选中的存储单元需要写入的数据，以及所述两个存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，从预设的多个配置电源端中择一输出电源信号，包括：
    当所述被选中的存储单元需要写入的数据为1时：
    如果所述两个存储单元需要写入的数据均为1，选择所述第一电压输出；
    如果所述两个存储单元中一个存储单元需要写入的数据为1，另一个存储单元需要写入的数据为0，选择所述第二电压输出；
    如果所述两个存储单元需要写入的数据均为0时，选择所述第三电压输出。
  9. 根据权利要求6所述的DRAM芯片的写入补偿方法，其中，所述多个配置电源端包括多个配置电压端；所述多个配置电压端提供多个不同的第一类型电压和多个不同的第二类型电压；所述第一类型电压是指大于或等于预设的第一电压阈值的电压，所述第二类型电压是指小于或等于预设的第二电压阈值的电压，所述第一电压阈值大于所述第二电压阈值；
    所述第二类型电压包括：第四电压、第五电压和第六电压；其中，所述第四电压小于所述第五电压，所述第五电压小于所述第六电压；
    所述根据所述被选中的存储单元需要写入的数据，以及所述两个存储单元需要写入的数据是否与所述被选中的存储单元需要写入的数据相同，从预设的多个配置电源端中择一输出电源信号，包括：
    当所述被选中的存储单元需要写入的数据为0时：
    如果所述两个存储单元需要写入的数据均为1，选择所述第四电压输出；
    如果所述两个存储单元中一个存储单元需要写入的数据为1，另一个存储单元需要写入的数据为0，选择所述第五电压输出；
    如果所述两个存储单元需要写入的数据均为0，选择所述第六电压输出。
  10. 一种DRAM芯片的存储控制单元，包括处理器和计算机可读存储介质，所述计算机可读存储介质中存储有指令，当所述指令被所述处理器执行时，实现如权利要求6-9任意一项所述的DRAM芯片的写入补偿方法。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08102191A (ja) * 1994-08-05 1996-04-16 Nippon Steel Corp 半導体記憶装置用センス回路およびｄｒａｍ
CN1383153A (zh) * 2001-01-26 2002-12-04 萧正杰 多口存储单元结构
CN105070315A (zh) * 2015-07-30 2015-11-18 孤山电子科技（上海）有限公司 Sram存储单元、sram电路及其读写方法
CN107622780A (zh) * 2017-09-27 2018-01-23 中国科学院上海微系统与信息技术研究所 三维垂直型存储器读出电路及其读出方法
CN115171750A (zh) * 2022-07-07 2022-10-11 北京超弦存储器研究院 存储器及其访问方法、电子设备
CN115312091A (zh) * 2022-07-07 2022-11-08 北京超弦存储器研究院 一种存储单元、阵列、系统及数据读写方法和控制芯片

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08102191A (ja) * 1994-08-05 1996-04-16 Nippon Steel Corp 半導体記憶装置用センス回路およびｄｒａｍ
CN1383153A (zh) * 2001-01-26 2002-12-04 萧正杰 多口存储单元结构
CN105070315A (zh) * 2015-07-30 2015-11-18 孤山电子科技（上海）有限公司 Sram存储单元、sram电路及其读写方法
CN107622780A (zh) * 2017-09-27 2018-01-23 中国科学院上海微系统与信息技术研究所 三维垂直型存储器读出电路及其读出方法
CN115171750A (zh) * 2022-07-07 2022-10-11 北京超弦存储器研究院 存储器及其访问方法、电子设备
CN115312091A (zh) * 2022-07-07 2022-11-08 北京超弦存储器研究院 一种存储单元、阵列、系统及数据读写方法和控制芯片

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