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WO2024016584A1 - 存储器及其制备方法、电子设备 - Google Patents

存储器及其制备方法、电子设备 Download PDF

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Publication number
WO2024016584A1
WO2024016584A1 PCT/CN2022/140158 CN2022140158W WO2024016584A1 WO 2024016584 A1 WO2024016584 A1 WO 2024016584A1 CN 2022140158 W CN2022140158 W CN 2022140158W WO 2024016584 A1 WO2024016584 A1 WO 2024016584A1
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Prior art keywords
substrate
initial
isolation
structures
memory
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PCT/CN2022/140158
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English (en)
French (fr)
Inventor
李永杰
孟敬恒
平延磊
Original Assignee
北京超弦存储器研究院
长鑫科技集团股份有限公司
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Publication of WO2024016584A1 publication Critical patent/WO2024016584A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs

Definitions

  • the present application relates to the field of semiconductor technology. Specifically, the present application relates to a memory, a preparation method thereof, and electronic equipment.
  • DRAM Dynamic Random Access Memory
  • a dynamic random access memory is composed of multiple memory cells.
  • the memory cells usually include transistors, capacitors and other devices. Each memory cell reads and writes data through word lines and bit lines.
  • this application proposes a memory, a preparation method thereof, and electronic equipment to solve the technical problem that the transistors in the existing memory occupy a large area.
  • embodiments of the present application provide a memory, including:
  • bit lines extending along the X direction
  • An isolation structure includes a plurality of first isolation structures and a plurality of second isolation structures; the first isolation structures extend along the X direction, and each of the bit lines and each of the first isolation structures are alternately arranged along the Y direction, The bottom surface of the first isolation structure is closer to the bottom surface of the substrate than the bottom surface of the bit line; the X direction and the Y direction have a design angle and are both parallel to the substrate;
  • first grooves and wall structures extending along the Y direction; the wall structure includes the active columns and the third wall structures alternately arranged along the Y direction.
  • Two isolation structures the active pillar is located on the side of the bit line away from the substrate, and the second isolation structure is located on the side of the first isolation structure away from the substrate.
  • the bit line includes a plurality of doping structures; along the X direction, the doping structures are located below two adjacent active pillars.
  • the material of the doped structure includes at least one of phosphorus, antimony and arsenic.
  • the bottom of the first trench exposes part of the upper surface of the bit line and part of the upper surface of the first isolation structure.
  • the upper surface of the wall structure is flush.
  • a protective film is provided on the surface of the wall structure.
  • the protective film is made of silicon dioxide and/or silicon nitride.
  • embodiments of the present application provide an electronic device, including the memory provided in the first aspect.
  • embodiments of the present application provide a memory preparation method, including:
  • a plurality of first trenches extending along the Y direction and spaced apart along the X direction are prepared on the first substrate to form a plurality of first isolation structures located at the bottom of the second trenches and a plurality of first isolation structures along the Y direction.
  • a protective film is prepared on the surface of the initial wall structure; using the protective film and each of the first isolation structures as masks, the initial substrate under the bottom surface of the first trench and each of the initial active
  • the portion of the pillar close to the initial substrate is etched to obtain a plurality of through grooves, a plurality of active pillars, and a substrate; the through grooves extend along the X direction and are connected to the first first substrate along the Y direction.
  • the isolation structures are alternately arranged, and the bottom surface of the through groove is higher than the bottom surface of the first isolation structure;
  • Bit lines are prepared within the vias.
  • a protective film on the surface of the initial wall structure including:
  • Part of the initial protective film at the bottom of the first trench is removed to obtain a protective film covering the surface of the initial wall structure.
  • the initial substrate under the bottom surface of the first trench and the portion of each initial active pillar close to the initial substrate are etched to obtain a plurality of through grooves, including:
  • a mixed solution of tetramethylammonium hydroxide or ammonia hydrogen peroxide is used to perform wet etching on the initial substrate below the bottom surface of the first trench and the portion of each initial active column close to the initial substrate.
  • preparing bit lines in the through slots includes:
  • Doping ions are grown on the side walls of the through trenches below each of the first trenches to form a plurality of doping structures, which extend below two adjacent active pillars until each doping structure connected to form the bit lines.
  • the active pillar is located on the side of the bit line away from the substrate, that is, the bit line is located below the active pillar, which replaces the solution in the related art that the bit line is connected to the side of the active pillar, thereby reducing the occupied area of the bit line.
  • This in turn can reduce the area occupied by transistors and help improve memory integration.
  • the doped structure containing doped ions enables the formed bit line to have low resistivity characteristics, and at the same time can increase mobility, which is conducive to reducing the contact resistance between the bit line and the active pillar, thereby improving the performance of the memory.
  • the bottom surface of the first isolation structure is closer to the bottom surface of the substrate than the bottom surface of the bit line.
  • the first isolation structure cannot completely isolate the adjacent bit lines, and there is a possibility of connectivity between adjacent bit lines; when the bottom surface of the bit line is higher than the first isolation structure On the bottom surface, the first isolation structure can completely isolate adjacent bit lines, which is beneficial to reducing the possibility of connectivity between adjacent bit lines, thereby improving the operating stability of the memory.
  • Figure 1 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • Figure 2 is a schematic flow chart of a memory preparation method provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram after preparing a plurality of second trenches extending along the X direction and spaced apart along the Y direction on the initial substrate in a method for manufacturing a memory provided by an embodiment of the present application;
  • Figure 4 is a schematic structural diagram after preparing an initial isolation structure in the second trench in a memory manufacturing method provided by an embodiment of the present application;
  • Figure 5 shows a method for manufacturing a memory provided by an embodiment of the present application.
  • a plurality of first trenches extending in the Y direction and spaced apart in the X direction are prepared on the first substrate to form a plurality of first trenches at the bottom of the second trenches.
  • Figure 6 is a schematic structural diagram after preparing a protective film on the surface of the initial wall structure in a memory preparation method provided by an embodiment of the present application;
  • Figure 7 shows a method for manufacturing a memory provided by an embodiment of the present application.
  • the initial substrate below the bottom surface of the first trench and the portion of each initial active pillar close to the initial substrate are etched to obtain multiple through grooves.
  • FIG. 1 An embodiment of the present application provides a memory.
  • the structural schematic diagram of the memory is shown in FIG. 1 , including: a substrate 1 , a plurality of bit lines 2 , an isolation structure, a plurality of active pillars 4 and a first trench 5 .
  • Bit line 2 extends in the X direction.
  • the isolation structure includes a plurality of first isolation structures 31 and a plurality of second isolation structures 32 .
  • the first isolation structures 31 extend along the X direction.
  • Each bit line 2 and each first isolation structure 31 are alternately arranged along the Y direction.
  • the bottom surface of the first isolation structure 31 is closer to the bottom surface of the substrate 1 than the bottom surface of the bit line 2;
  • the directions have design angles and are all parallel to substrate 1.
  • the bit line 2 is on a side away from the substrate 1
  • the second isolation structure 32 is located on a side of the first isolation structure 31 away from the substrate 1 .
  • the substrate 1 serves as a supporting component of the memory and is used to support other components located on it.
  • the active pillar 4 is located on the side of the bit line 2 away from the substrate 1, that is, the bit line 2 is located below the active pillar 4. This replaces the solution in the related art that the bit line is connected to the side of the active pillar, thereby reducing the bit line 4.
  • the occupied area of line 2 can thereby reduce the occupied area of the transistor, which is beneficial to improving the integration of the memory.
  • the bottom surface of the first isolation structure 31 is closer to the bottom surface of the substrate 1 than the bottom surface of the bit line 2 .
  • the first isolation structure 31 cannot completely isolate the adjacent bit lines 2 , and there is a possibility of communication between the adjacent bit lines 2 ; when the bottom surface of the bit lines 2 When it is higher than the bottom surface of the first isolation structure 31 , the first isolation structure 31 can completely isolate the adjacent bit lines 2 , which is beneficial to reducing the possibility of connection between the adjacent bit lines 2 , thereby improving the working stability of the memory. sex.
  • the X direction and the Y direction have design angles, and the design angles can be designed according to actual needs.
  • the design angle is 90°.
  • the material of the substrate 1 may be silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); it may also be silicon on insulator (SOI) or germanium on insulator (GOI); Or it can also be other materials, such as gallium arsenide and other group III-V compounds.
  • the bit line 2 of this application includes multiple doping structures; along the X direction, the doping structures are located between two adjacent ones. Below source column 4.
  • the bit line 2 is formed by a doping structure, which can help reduce the resistivity of the bit line 2 and improve the mobility, thereby reducing the contact resistance between the bit line 2 and the active pillar 4, thereby improving the semiconductor device performance.
  • the material of the doped structure includes at least one of phosphorus, antimony and arsenic.
  • the doped structure containing doped ions enables the formed bit line 2 to have low resistivity characteristics, and at the same time can increase mobility, which is beneficial to reducing the contact resistance between the bit line 2 and the active pillar 4, thereby Can improve memory usage performance.
  • the doped ions can also be selected from other ions according to specific requirements, such as antimony (Sb), arsenic (As), etc., so that the bit line 2 formed by the doped structure can also have low resistivity characteristics and improve the memory. performance purposes.
  • the doping concentration of ions is greater than 10 20 per square centimeter.
  • the doping concentration of ions is not less than 10 21 and not greater than 10 22 per square centimeter.
  • the bottom of the first trench 5 exposes part of the upper surface of the bit line 2 and part of the upper surface of the first isolation structure 31 .
  • part of the upper surface of the bit line 2 and part of the upper surface of the first isolation structure 31 are exposed, so that the bit line 2 is subsequently formed from the bottom of the first trench 5 downward.
  • the upper surface of the wall structure is flush.
  • the upper surface of the wall structure is flush, which means that the upper surfaces of the active pillars 4 and the second isolation structure 32 are flush, which can provide good flatness and interface state for subsequent film growth, which is conducive to improving the memory. reliability and performance stability.
  • a protective film 6 is provided on the surface of the wall structure.
  • a protective film 6 is provided on the surface of the wall structure, that is, a protective film 6 is provided on the side wall of the first trench 5.
  • the bottom surface of the first trench 5 needs to be wetted. Because the side walls of the first trench 5 are protected by the protective film 6, the damage to the side walls of the first trench 5 is negligible.
  • wet etching has a high selectivity for silicon dioxide and will not cause damage to the first isolation structure 31 .
  • the material of the protective film 6 includes silicon dioxide and/or silicon nitride.
  • inventions of the present application provide an electronic device including a memory.
  • the memory includes: a substrate 1, a plurality of bit lines 2, an isolation structure, a plurality of active pillars 4 and a first trench 5.
  • Bit line 2 extends in the X direction.
  • the isolation structure includes a plurality of first isolation structures 31 and a plurality of second isolation structures 32 .
  • the first isolation structures 31 extend along the X direction.
  • Each bit line 2 and each first isolation structure 31 are alternately arranged along the Y direction.
  • the bottom surface of the first isolation structure 31 is closer to the bottom surface of the substrate 1 than the bottom surface of the bit line 2;
  • the directions have design angles and are all parallel to substrate 1.
  • the bit line 2 is on a side away from the substrate 1
  • the second isolation structure 32 is located on a side of the first isolation structure 31 away from the substrate 1 .
  • the substrate 1 serves as a supporting component of the memory and is used to support other components located thereon.
  • the active pillar 4 is located on the side of the bit line 2 away from the substrate 1, that is, the bit line 2 is located below the active pillar 4. This replaces the solution in the related art that the bit line is connected to the side of the active pillar, thereby reducing the bit line 4.
  • the occupied area of line 2 can thereby reduce the occupied area of the transistor, which is beneficial to improving the integration of the memory.
  • the bottom surface of the first isolation structure 31 is closer to the bottom surface of the substrate 1 than the bottom surface of the bit line 2 .
  • the first isolation structure 31 cannot completely isolate the adjacent bit lines 2 , and there is a possibility of communication between the adjacent bit lines 2 ; when the bottom surface of the bit lines 2 When it is higher than the bottom surface of the first isolation structure 31 , the first isolation structure 31 can completely isolate the adjacent bit lines 2 , which is beneficial to reducing the possibility of connection between the adjacent bit lines 2 , thereby improving the working stability of the memory. sex.
  • the material of the bit line 2 includes at least one of phosphorus, antimony and arsenic.
  • the doped structure containing doped ions enables the formed bit line 2 to have low resistivity characteristics, and at the same time can increase mobility, which is beneficial to reducing the contact resistance between the bit line 2 and the active pillar 4, thereby Can improve memory usage performance.
  • the doped ions can also be selected from other ions according to specific requirements, such as antimony (Sb), arsenic (As), etc., so that the bit line 2 formed by the doped structure can also have low resistivity characteristics, thereby improving the memory performance purposes.
  • the doping concentration of ions is greater than 1020 per square centimeter.
  • the doping concentration of ions is not less than 1021 and not greater than 1022 per square centimeter.
  • the bit line 2 includes a plurality of doping structures; along the X direction, the doping structures are located under two adjacent active pillars 4 .
  • the bit line 2 is formed by a doping structure, which can help reduce the resistivity of the bit line 2 and improve the mobility, thereby reducing the contact resistance between the bit line 2 and the active pillar 4, thereby improving the semiconductor device performance.
  • the bottom of the first trench 5 exposes part of the upper surface of the bit line 2 and part of the upper surface of the first isolation structure 31 .
  • part of the upper surface of the bit line 2 and part of the upper surface of the first isolation structure 31 are exposed, so that the bit line 2 is subsequently formed from the bottom of the first trench 5 downward.
  • the upper surface of the wall structure is flush.
  • the upper surface of the wall structure is flush, which means that the upper surfaces of the active pillars 4 and the second isolation structure 32 are flush, which can provide good flatness and interface state for subsequent film growth, which is conducive to improving the memory. reliability and performance stability.
  • a protective film 6 is provided on the surface of the wall structure.
  • a protective film 6 is provided on the surface of the wall structure, that is, a protective film 6 is provided on the side wall of the first trench 5.
  • the bottom surface of the first trench 5 needs to be wetted. Because the side walls of the first trench 5 are protected by the protective film 6, the damage to the side walls of the first trench 5 is negligible.
  • wet etching has a high selectivity for silicon dioxide and will not cause damage to the first isolation structure 31 .
  • the material of the protective film 6 includes silicon dioxide and/or silicon nitride.
  • an embodiment of the present application provides a memory preparation method.
  • a schematic flow chart of the method is shown in Figure 2. The method includes the following steps S1 to S4.
  • S1 Prepare a plurality of second trenches 72 extending along the X direction and spaced apart along the Y direction on the initial substrate 71; prepare initial isolation structures 73 in the second trenches 72 to obtain a first substrate.
  • FIG. 3 a schematic structural diagram is shown after preparing a plurality of second trenches 72 extending in the X direction and spaced along the Y direction on the initial substrate 71 ; as shown in FIG. 4 , A schematic structural diagram after the initial isolation structure 73 is prepared in the second trench 72 .
  • the second trench 72 can be etched downward from the top surface of the initial substrate 71 through a SADP process (Self Aligned Double Patterning, self-aligned double patterning process).
  • SADP process Self Aligned Double Patterning, self-aligned double patterning process
  • Other methods may also be used in other embodiments, such as SAQP process (Self-Aligned Quadruple Patterning, self-aligned quadruple patterning process) or SALELE process (Self-Aligned Lithe-Etch-Lithe-Etch, self-aligned double line lighting). etching technology) to etch the initial substrate 71.
  • a first mask layer (not shown in the figure) is formed on the initial substrate 71 , and the initial substrate 71 is etched using the first mask layer as a mask to obtain the second trench 72 .
  • the first mask layer may be a hard mask, or may be a mask formed by photoresist photolithography.
  • the top surface of the initial substrate 71 is covered with a hard mask and the second mask layer is obtained by etching, After the trench 72 is formed, the hard mask can be removed, or the hard mask can be retained on the original substrate 71 for use in subsequent steps.
  • the material of the initial isolation structure 73 is a material with lower filling capacity.
  • the material of the initial isolation structure 73 may be any one of silicon dioxide and silicon nitride or a mixture of both.
  • the initial isolation structure 73 may be formed through a deposition process such as an atomic layer deposition process or a vapor deposition process.
  • a high-density plasma chemical vapor deposition process or a plasma enhanced chemical vapor deposition process may be used.
  • the dielectric selective silicon dioxide filled into the second trench 72 forms a shape that is adapted to the shape of the second trench 72, extends along the Y direction, and extends along the X direction. Spaced isolation structure.
  • the initial isolation structure 73 when the initial isolation structure 73 is formed through a deposition process such as an atomic layer deposition process or a vapor deposition process, the top surface of the substrate 1 will be covered while filling the second trench 72, and the top surface of the initial substrate 71 will be covered. By removing the isolation layer on the surface, a plurality of initial isolation structures 73 arranged at intervals along the Y direction are obtained.
  • a deposition process such as an atomic layer deposition process or a vapor deposition process
  • an initial isolation structure 73 is prepared within the second trench 72 , including planarizing the isolation layer and exposing the top surface of the initial substrate 71 .
  • a planarization technology is used to remove the isolation layer located above the top surface of the initial substrate 71.
  • CMP chemical mechanical polishing
  • the planarization process can not only remove the excess isolation layer, but also provide good flatness and interface state for subsequent film growth, improving the reliability and performance stability of the memory.
  • S2 Prepare a plurality of first trenches 5 extending in the Y direction and spaced apart in the X direction on the first substrate to form a plurality of first isolation structures 31 at the bottom of the second trenches 72 and a plurality of first isolation structures 31 located at the bottom of the second trenches 72 and a plurality of first trenches 5 extending in the Y direction and spaced in the X direction.
  • An extended initial wall structure the initial wall structure includes initial active columns and second isolation structures 32 alternately arranged along the Y direction; a plurality of first isolation structures 31 and a plurality of second isolation structures 32 form an isolation structure.
  • a plurality of first trenches 5 extending in the Y direction and spaced apart in the X direction are prepared on the first substrate to form a plurality of first trenches 5 located at the bottom of the second trenches 72 .
  • the extending direction of the first trench 5 is perpendicular to the extending direction of the second trench 72 where the first isolation structure 31 is located.
  • the first trenches 5 are criss-crossed with the isolation structures, so that the initial substrate 71 is separated by the first trenches 5 and the second trenches 72 to form a plurality of initial active pillars.
  • the initial active pillars may be distributed in an array. Along the X direction, two adjacent initial active pillars are separated by the first trench 5; along the Y direction, two adjacent initial active pillars are separated by the second isolation structure 32.
  • the first trench 5 can be etched downward from the top surface of the first substrate through a SADP process (Self Aligned Double Patterning, self-aligned double patterning process), and the bottom wall height of the first trench 5 Control above the bottom surface of the isolation structure.
  • SADP process Self Aligned Double Patterning, self-aligned double patterning process
  • SALELE Self-Aligned Lithe-Etch-Lithe-Etch, self-aligned double line lithography technology
  • the first trench 5 is arranged at an angle with the finally formed bit line 2, and the first trench 5 is adjacent to the active pillar 4, the first trench 5 can subsequently be used as a word line trench to form a word line. , thereby further simplifying the manufacturing process of semiconductor devices.
  • the active pillar 4 is separated by the first trench 5 and the second isolation structure 32. Since the bottom surface of the first trench 5 is higher than the bottom surface of the first isolation structure 31, part of the initial substrate 71 is subsequently removed.
  • the through groove 74 obtained from the initial active pillar can be separated by the first isolation structure 31 , so that the subsequently formed doping structure is also separated by the first isolation structure 31 .
  • a protective film 6 on the surface of the initial wall structure including:
  • An initial protective film is prepared along the first trench 5, and the initial protective film covers the bottom of the first trench 5 and the surface of the initial wall structure.
  • Part of the initial protective film at the bottom of the first trench 5 is removed to obtain a protective film 6 covering the surface of the initial wall structure.
  • FIG. 6 is a schematic diagram of the structure after the protective film 6 is prepared on the surface of the initial wall structure. Part of the initial protective film at the bottom of the first trench 5 is removed, so that the initial substrate 71 is subsequently etched downward from the bottom of the first trench 5 .
  • the material of the protective film 6 may be silicon nitride.
  • the initial substrate 71 below the bottom surface of the first trench 5 and the portion of each initial active pillar close to the initial substrate 71 are etched to obtain a plurality of through grooves 74, including:
  • a mixed solution of tetramethylammonium hydroxide or ammonia hydrogen peroxide is used to wet etch the initial substrate 71 below the bottom surface of the first trench 5 and the portion of each initial active pillar close to the initial substrate 71 .
  • the initial substrate 71 under the bottom surface of the first trench 5 and the portion of each initial active pillar close to the initial substrate 71 are etched to obtain a structure after multiple through grooves 74 Schematic diagram.
  • the initial substrate 71 under the bottom surface of the first trench 5 is wet etched. Since the sidewalls of the first trench 5 are protected by the protective film 6 and the first isolation structure 31 will not be etched away, the first The initial substrate 71 below the bottom surface of the trench 5 is etched away to form multiple grooves. Grooves arranged in the same row along the Channel 74. Along the direction perpendicular to the substrate 1 , the bottom of the through groove 74 is higher than the bottom surface of the first isolation structure 31 .
  • the first isolation structure 31 cannot completely isolate the adjacent bit lines 2 . There is a possibility of communication between them; when the bottom of the through groove 74 is higher than the bottom surface of the first isolation structure 31, the first isolation structure 31 can completely isolate the adjacent bit lines 2, which is beneficial to reducing the interference between the adjacent bit lines 2.
  • the possibility of connectivity will help improve the operating temperature of the memory.
  • the wet etching method uses tetramethylammonium hydroxide (TMAH solution) as a cleaning solution. Since the TMAH solution has a high selectivity for silicon dioxide, during the process of removing the above-mentioned part of the initial substrate 71 to create the groove, the groove 25 can be formed smoothly, and a protective film is formed on the first trench 5 6, the damage to the side wall of the first trench 5 is negligible.
  • TMAH solution tetramethylammonium hydroxide
  • ammonia hydrogen peroxide mixed solution or other liquids can also be used as the cleaning liquid.
  • bit line 2 is prepared in the through groove 74, including:
  • Doping ions are grown on the side walls of the through trenches 74 below each first trench 5 to form a plurality of doping structures.
  • the doping structures extend below two adjacent active pillars 4 until the doping structures are connected. , forming bit line 2.
  • doping ions are grown on the side walls of the through grooves 74 below each first trench 5 to form multiple doping structures.
  • the doping structures continue to grow until the doping structures are connected and the entire doping structure is connected.
  • Bit line 2 is formed in through slot 74 .
  • a CVD (Chemical Vapor Deposition) process is used to start growing from the sidewall of the through groove 74 below the first trench 5, and a doping structure is formed in the through groove 74 that gradually fills the interior of the through groove 74. .
  • the doped structures gradually approach and contact each other to form the bit line 2 located in the through trench 74 .
  • the CVD process can use high-density plasma chemical vapor deposition process or plasma enhanced chemical vapor deposition process.
  • the bit line 2 formed by doping ions can help reduce the resistivity of the bit line 2 and improve the mobility, thereby reducing the contact resistance between the bit line 2 and the active pillar 4, thereby improving the use of the memory. performance.
  • the doped structure can also be formed through an atomic layer deposition process, such as a single atomic layer sequential deposition process, so that the deposited layer can obtain a uniform thickness and excellent consistency, that is, the bit lines formed by the doped structure can be improved. 2 performance.
  • an atomic layer deposition process such as a single atomic layer sequential deposition process
  • the doped ions in the doped structure include phosphorus (P).
  • the doped structure containing P ions enables the formed bit line 2 to have low resistivity characteristics, and at the same time can increase mobility, which is beneficial to reducing the contact resistance between the bit line 2 and the active pillar 4, thereby enabling Improve memory usage performance.
  • the doped ions can also be selected from other ions according to specific requirements, such as antimony (Sb), arsenic (As), etc., so that the bit line 2 formed by the doped structure can also have low resistivity characteristics and improve the memory. performance purposes.
  • the doping concentration of ions is greater than 10 20 per square centimeter.
  • the doping concentration of ions is not less than 10 21 and not greater than 10 22 per square centimeter.
  • the active pillar is located on the side of the bit line away from the substrate, that is, the bit line is located below the active pillar, instead of the solution in the related art that the bit line is connected to the side of the active pillar, thereby reducing
  • the small bit line occupies an area, thereby reducing the transistor occupancy area, which is beneficial to improving memory integration.
  • the bottom surface of the first isolation structure in the direction perpendicular to the substrate, is closer to the bottom surface of the substrate than the bottom surface of the bit line.
  • the first isolation structure cannot completely isolate the adjacent bit lines, and there is a possibility of connectivity between adjacent bit lines; when the bottom surface of the bit line is higher than the first isolation structure On the bottom surface, the first isolation structure can completely isolate adjacent bit lines, which is beneficial to reducing the possibility of connectivity between adjacent bit lines, thereby improving the operating stability of the memory.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can be alternated, changed, combined, or deleted.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted.
  • steps, measures, and solutions in the prior art with various operations, methods, and processes disclosed in this application can also be replaced, changed, rearranged, decomposed, combined, or deleted.
  • first and second are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of this application, unless otherwise stated, “plurality” means two or more.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components.
  • connection or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components.

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Abstract

本申请实施例提供了一种存储器及其制备方法、电子设备。该存储器包括衬底、多条位线、隔离结构、多个有源柱和第一沟槽。位线沿X方向延伸。隔离结构包括多个第一隔离结构和多个第二隔离结构。第一隔离结构沿X方向延伸，各位线与各第一隔离结构沿Y方向交替排列，第一隔离结构的底面比位线的底面靠近衬底的底面；X方向与Y方向具有设计角度，且均平行于衬底。沿X方向，交替设置有均沿Y方向延伸的第一沟槽和墙体结构；墙体结构包括沿Y方向交替排布的有源柱和第二隔离结构；有源柱位于位线远离衬底的一侧，第二隔离结构位于第一隔离结构远离衬底的一侧。本申请能够减小位线的占用面积，缩小晶体管的占用面积，有利于提高存储器的集成度。

Description

存储器及其制备方法、电子设备 技术领域
本申请涉及半导体技术领域，具体而言，本申请涉及一种存储器及其制备方法、电子设备。
背景技术
随着现今科技快速的发展，半导体存储器被广泛地应用于电子设备中。动态随机存取存储器(Dynamic Random Access Memory，DRAM)属于一种挥发性存储器，对于储存大量数据的应用而言，动态随机存取存储器是最常被利用的解决方案。通常，动态随机存取存储器是由多个存储单元构成，存储单元通常包括晶体管、电容等器件，各存储单元通过字线和位线进行数据的读取和写入。
但是，目前存储器中的晶体管仍然存在占用面积较大的问题。
发明内容
本申请针对现有方式的缺点，提出一种存储器及其制备方法、电子设备，用以解决现有存储器中的晶体管占用面积较大的技术问题。
第一个方面，本申请实施例提供了一种存储器，包括：
衬底；
多条位线，所述位线沿X方向延伸；
隔离结构，包括多个第一隔离结构和多个第二隔离结构；所述第一隔离结构沿所述X方向延伸，各所述位线与各所述第一隔离结构沿Y方向交替排列，所述第一隔离结构的底面比所述位线的底面靠近所述衬底的底面；所述X方向与所述Y方向具有设计角度，且均平行于所述衬底；
多个有源柱；
沿所述X方向，交替设置有均沿所述Y方向延伸的第一沟槽和墙体结构；所述墙体结构包括沿所述Y方向交替排布的所述有源柱和所述第二隔离结构；所述有源柱位于所述位线远离衬底的一侧，所述第二隔离结构位于所述第一隔离结构远离所述衬底的一侧。
可选地，所述位线包括多个掺杂结构；沿所述X方向，所述掺杂结构位于相邻两个有源柱的下方。
可选地，所述掺杂结构的材料包括磷、锑和砷中至少一种。
可选地，所述第一沟槽的槽底露出部分所述位线的上表面和部分所述第一隔离结构的上表面。
可选地，所述墙体结构的上表面平齐。
可选地，所述墙体结构的表面设置保护膜。
可选地，所述保护膜的材料均包括二氧化硅和/或氮化硅。
第二个方面，本申请实施例提供了一种电子设备，包括第一个方面提供的存储器。
第三个方面，本申请实施例提供了一种存储器的制备方法，包括：
在初始衬底上制备多条沿X方向延伸且沿Y方向间隔排布的第二沟槽；在所述第二沟槽内制备初始隔离结构，得到第一基板；
在所述第一基板上制备多条沿Y方向延伸且沿X方向间隔排布的第一沟槽，形成多个位于所述第二沟槽底部的第一隔离结构和多个沿所述Y方向延伸的初始墙体结构；所述初始墙体结构包括沿Y方向交替排列的初始有源柱和第二隔离结构；多个所述第一隔离结构和多个所述第二隔离结构形成隔离结构；
在所述初始墙体结构的表面制备保护膜；以所述保护膜和各所述第一隔离结构为掩膜，对所述第一沟槽底面下方的初始衬底和各所述初始有源柱靠近所述初始衬底的部分进行刻蚀，得到多个通槽、多个有源柱、以及衬底；所述通槽沿所述X方向延伸并沿所述Y方向与所述第一隔离结构交替排布，所述通槽的底面高于所述第一隔离结构的底面；
在所述通槽内制备位线。
可选地，在所述初始墙体结构的表面制备保护膜，包括：
沿所述第一沟槽随形制备初始保护膜，所述初始保护膜覆盖所述第一沟槽的槽底和所述初始墙体结构的表面；
去除所述第一沟槽槽底的部分初始保护膜，得到覆盖所述初始墙体结构表面的保护膜。
可选地，对所述第一沟槽底面下方的初始衬底和各所述初始有源柱靠近所述初始衬底的部分进行刻蚀，得到多个通槽，包括：
采用四甲基氢氧化铵或氨过氧化氢混合溶液对所述第一沟槽底面下方的初始衬底和各所述初始有源柱靠近所述初始衬底的部分进行湿法刻蚀。
可选地，在所述通槽内制备位线，包括：
在各所述第一沟槽下方的通槽的侧壁上生长掺杂离子，形成多个掺杂结构，所述掺杂结构延伸至相邻两个有源柱的下方，直至各掺杂结构连通，形成所述位线。
本申请实施例提供的技术方案带来的有益技术效果包括：
有源柱位于位线远离衬底的一侧，即位线位于有源柱的下方，代替了相关技术中位线与有源柱的侧面连接的方案，由此能够减小位线的占用面积，进而能够缩小晶体管的占用面积，有利于提高存储器的集成度。含有掺杂离子的掺杂结构使形成的位线具有低电阻率的特性，同时能够提高迁移率，有利于降低位线与有源柱之间的接触电阻，从而能够提高存储器的使用性能。
沿垂直于衬底的方向，第一隔离结构的底面比位线的底面靠近衬底的底面。当位线的底面低于第一隔离结构的底面时，第一隔离结构不能完全将相邻位线隔离，相邻位线之间存在连通的可能；当位线的底面高于第一隔离结构的底面时，第一隔离结构可以完全将相邻位线隔离，有利于降低相邻位线之间的连通的可能性，从而有利于提升存储器的工作稳定性。
本申请附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本申请实施例提供的一种存储器的结构示意图；
图2为本申请实施例提供的一种存储器的制备方法的流程示意图；
图3为本申请实施例提供的一种存储器的制备方法中在初始衬底上制备多条沿X方向延伸且沿Y方向间隔排布的第二沟槽之后的结构示意图；
图4为本申请实施例提供的一种存储器的制备方法中在第二沟槽内制备初始隔离结构之后的结构示意图；
图5为本申请实施例提供的一种存储器的制备方法中在第一基板上制备多条沿Y方向延伸且沿X方向间隔排布的第一沟槽，形成多个位于第二沟槽底部的第一隔离结构和多个沿Y方向延伸的初始墙体结构后的结构示意图；
图6为本申请实施例提供的一种存储器的制备方法中在初始墙体结构的表面制备保护膜之后的结构示意图；
图7为本申请实施例提供的一种存储器的制备方法中对第一沟槽底面下方的初始衬底和各初始有源柱靠近初始衬底的部分进行刻蚀，得到多个通槽后的结构示意图。
附图标记说明：
1-衬底；
2-位线；
31-第一隔离结构；32-第二隔离结构；
4-有源柱；
5-第一沟槽；
6-保护膜；
71-初始衬底；72-第二沟槽；73-初始隔离结构；74-通槽。
具体实施方式
下面结合本申请中的附图描述本申请的实施例。应理解，下面结合附图所阐述的实施方式，是用于解释本申请实施例的技术方案的示例性描述，对本申请实施例的技术方案不构成限制。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但不排除实现为本技术领域所支持其他特征、信息、数据、步骤、操作、元件、组件和/或它们的组合等。这里使用的术语“和/或”指该术语所限定的项目中的至少一个，例如“A和/或B”可以实现为“A”，或者实现为“B”，或者实现为“A和B”。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。需要指出的是，下述实施方式之间可以相互参考、借鉴或结合，对于不同实施方式中相同的术语、相似的特征以及相似的实施步骤等，不再重复描述。本实施例对存储器不作限制，下面将以动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的存储器还可以为其他的结构。
本申请实施例提供了一种存储器，该存储器的结构示意图如图1所示，包括：衬底1、多条位线2、隔离结构、多个有源柱4和第一沟槽5。
位线2沿X方向延伸。
隔离结构包括多个第一隔离结构31和多个第二隔离结构32。第一隔离结构31沿X方向延伸，各位线2与各第一隔离结构31沿Y方向交替排列，第一隔离结构31的底面比位线2的底面靠近衬底1的底面；X方向与Y方向具有设计角度，且均平行于衬底1。
沿X方向，交替设置有均沿Y方向延伸的第一沟槽5和墙体结构； 墙体结构包括沿Y方向交替排布的有源柱4和第二隔离结构32；有源柱4位于位线2远离衬底1的一侧，第二隔离结构32位于第一隔离结构31远离衬底1的一侧。
本实施例中，衬底1作为存储器的支撑部件，用于支撑设在其上的其他部件。有源柱4位于位线2远离衬底1的一侧，即位线2位于有源柱4的下方，代替了相关技术中位线与有源柱的侧面连接的方案，由此能够减小位线2的占用面积，进而能够缩小晶体管的占用面积，有利于提高存储器的集成度。
沿垂直于衬底1的方向，第一隔离结构31的底面比位线2的底面靠近衬底1的底面。当位线2的底面低于第一隔离结构31的底面时，第一隔离结构31不能完全将相邻位线2隔离，相邻位线2之间存在连通的可能；当位线2的底面高于第一隔离结构31的底面时，第一隔离结构31可以完全将相邻位线2隔离，有利于降低相邻位线2之间的连通的可能性，从而有利于提升存储器的工作稳定性。
可以理解的是，X方向与Y方向具有设计角度，设计角度可根据实际需要设计。本实施例中，设计角度为90°。
具体地，衬底1的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。
考虑到位线自身存在寄生电阻，会对其传输的信号造成影响，进而影响存储器的可靠性，本申请的位线2包括多个掺杂结构；沿X方向，掺杂结构位于相邻两个有源柱4的下方。
本实施例中，通过掺杂结构形成位线2，能够有利于降低位线2的电阻率，同时能够提高迁移率，从而降低位线2与有源柱4之间的接触电阻，从而提高半导体器件的性能。
可选地，掺杂结构的材料包括磷、锑和砷中至少一种。
本实施例中，含有掺杂离子的掺杂结构使形成的位线2具有低电阻率的特性，同时能够提高迁移率，有利于降低位线2与有源柱4之间的接触电阻， 从而能够提高存储器的使用性能。
可以理解的，掺杂的离子也可以根据具体需求选择其他离子，例如锑(Sb)、砷(As)等，亦可以达到使掺杂结构形成的位线2具有低电阻率的特性，提高存储器的性能的目的。本实施例中，离子的掺杂浓度大于10 20每平方厘米，例如，离子的掺杂浓度不小于10 21且不大于10 22每平方厘米。
可选地，第一沟槽5的槽底露出部分位线2的上表面和部分第一隔离结构31的上表面。
本实施例中，通过露出部分位线2的上表面和部分第一隔离结构31的上表面，以便后续由第一沟槽5的槽底向下形成位线2。
可选地，墙体结构的上表面平齐。
本实施例中，墙体结构的上表面平齐代表着有源柱4和第二隔离结构32的上表面平齐，能够为后续的薄膜生长提供良好的平坦度和界面态，有利于提高存储器的可靠性和性能稳定性。
可选地，墙体结构的表面设置保护膜6。
本实施例中，墙体结构的表面设置保护膜6，即第一沟槽5的侧壁设置有保护膜6，在形成位线2的过程中，需对第一沟槽5的底面进行湿法刻蚀，因第一沟槽5的侧壁在保护膜6的保护作用下，第一沟槽5的侧壁受损程度可以忽略不计。而且湿法刻蚀对二氧化硅具有较高的选择比，不会对第一隔离结构31造成损伤。
可选地，保护膜6的材料均包括二氧化硅和/或氮化硅。
基于同一发明构思，本申请实施例提供了一种电子设备，包括存储器。存储器包括：衬底1、多条位线2、隔离结构、多个有源柱4和第一沟槽5。
位线2沿X方向延伸。
隔离结构包括多个第一隔离结构31和多个第二隔离结构32。第一隔离结构31沿X方向延伸，各位线2与各第一隔离结构31沿Y方向交替排列，第一隔离结构31的底面比位线2的底面靠近衬底1的底面；X方向与Y方向具有设计角度，且均平行于衬底1。
沿X方向，交替设置有均沿Y方向延伸的第一沟槽5和墙体结构； 墙体结构包括沿Y方向交替排布的有源柱4和第二隔离结构32；有源柱4位于位线2远离衬底1的一侧，第二隔离结构32位于第一隔离结构31远离衬底1的一侧。
本实施例中，衬底1作为存储器的支撑部件，用于支撑设在其上的其他部件。有源柱4位于位线2远离衬底1的一侧，即位线2位于有源柱4的下方，代替了相关技术中位线与有源柱的侧面连接的方案，由此能够减小位线2的占用面积，进而能够缩小晶体管的占用面积，有利于提高存储器的集成度。
沿垂直于衬底1的方向，第一隔离结构31的底面比位线2的底面靠近衬底1的底面。当位线2的底面低于第一隔离结构31的底面时，第一隔离结构31不能完全将相邻位线2隔离，相邻位线2之间存在连通的可能；当位线2的底面高于第一隔离结构31的底面时，第一隔离结构31可以完全将相邻位线2隔离，有利于降低相邻位线2之间的连通的可能性，从而有利于提升存储器的工作稳定性。
可选地，位线2的材料包括磷、锑和砷中至少一种。
本实施例中，含有掺杂离子的掺杂结构使形成的位线2具有低电阻率的特性，同时能够提高迁移率，有利于降低位线2与有源柱4之间的接触电阻，从而能够提高存储器的使用性能。
可以理解的，掺杂的离子也可以根据具体需求选择其他离子，例如锑(Sb)、砷(As)等，亦可以达到使掺杂结构形成的位线2具有低电阻率的特性，提高存储器的性能的目的。本实施例中，离子的掺杂浓度大于1020每平方厘米，例如，离子的掺杂浓度不小于1021且不大于1022每平方厘米。
可选地，位线2包括多个掺杂结构；沿X方向，掺杂结构位于相邻两个有源柱4的下方。
本实施例中，通过掺杂结构形成位线2，能够有利于降低位线2的电阻率，同时能够提高迁移率，从而降低位线2与有源柱4之间的接触电阻，从而提高半导体器件的性能。
可选地，第一沟槽5的槽底露出部分位线2的上表面和部分第一隔离结构31的上表面。
本实施例中，通过露出部分位线2的上表面和部分第一隔离结构31的上表面，以便后续由第一沟槽5的槽底向下形成位线2。
可选地，墙体结构的上表面平齐。
本实施例中，墙体结构的上表面平齐代表着有源柱4和第二隔离结构32的上表面平齐，能够为后续的薄膜生长提供良好的平坦度和界面态，有利于提高存储器的可靠性和性能稳定性。
可选地，墙体结构的表面设置保护膜6。
本实施例中，墙体结构的表面设置保护膜6，即第一沟槽5的侧壁设置有保护膜6，在形成位线2的过程中，需对第一沟槽5的底面进行湿法刻蚀，因第一沟槽5的侧壁在保护膜6的保护作用下，第一沟槽5的侧壁受损程度可以忽略不计。而且湿法刻蚀对二氧化硅具有较高的选择比，不会对第一隔离结构31造成损伤。
可选地，保护膜6的材料均包括二氧化硅和/或氮化硅。
基于同一发明构思，本申请实施例提供了一种存储器的制备方法，该方法的流程示意图如图2所示，该方法包括如下步骤S1至S4。
S1：在初始衬底71上制备多条沿X方向延伸且沿Y方向间隔排布的第二沟槽72；在第二沟槽72内制备初始隔离结构73，得到第一基板。
本实施例中，如图3所示为在初始衬底71上制备多条沿X方向延伸且沿Y方向间隔排布的第二沟槽72之后的结构示意图；如图4所述为在第二沟槽72内制备初始隔离结构73之后的结构示意图。
具体地，可以通过SADP工艺(Self Aligned Double Patterning,，自对准双重图案工艺)自初始衬底71的顶面向下刻蚀形成第二沟槽72。其他实施例中也可以采用其他方式，例如SAQP工艺(Self-Aligned Quadruple Patterning，自对准四重图案工艺)或SALELE工艺(Self-Aligned Lithe-Etch-Lithe-Etch，自对准双线条光刻技术)对初始衬底71进行刻蚀。示例性地，在初始衬底71上形成第一掩膜层(图中未示出)，以第一掩膜层为掩膜对初始衬底71进行刻蚀得到第二沟槽72。应理解，第一掩膜 层可以为硬掩膜，也可以是通过光刻胶光刻形成的掩膜，当采用在初始衬底71顶面覆盖硬掩膜并通过刻蚀的方式获得第二沟槽72后，可以去除硬掩膜，也可以保留该硬掩膜于初始衬底71上，以用作后续步骤中使用。
可选地，初始隔离结构73的材料为填充性较低的材料。
本实施例中，初始隔离结构73的材料可以为二氧化硅和氮化硅中的任一种或两种的混合。初始隔离结构73可以通过原子层沉积工艺、气相沉积工艺等沉积工艺形成。例如，可以采用高密度等离子体化学气相沉积工艺或者等离子体增强化学气相沉积工艺。示例性地，填充入第二沟槽72内的介质选择二氧化硅，填充入第二沟槽72内的二氧化硅形成与第二沟槽72形状适配、沿Y方向延伸并沿X方向间隔分布的隔离结构。
可以理解的是，通过原子层沉积工艺、气相沉积工艺等沉积工艺在形成初始隔离结构73时，在填充第二沟槽72的同时会将衬底1的顶面覆盖，将初始衬底71顶面的隔离层去除即得到沿Y方向间隔排布的多个初始隔离结构73。
应理解，上述选择二氧化硅填充入第二沟槽72内作为初始隔离结构73仅为填充介质的一个具体实施方式，旨在于获取具有漏电流小、寄生电容小、使岛与岛之间的隔离电压大这一特性的隔离结构，其他应用在本申请中并能达到相同效果的材料，例如氮化硅亦在本申请的保护范围内。
可选地，在第二沟槽72内制备初始隔离结构73，包括平坦化隔离层并暴露出初始衬底71的顶面。
本实施例中，采用平坦化技术将位于初始衬底71顶面上方的隔离层去除，例如采用化学机械抛光(Chemical Mechanical Polishing，简称CMP)处理隔离层，对初始衬底71的上表面进行平坦化处理，通过平坦化处理，既能够去除多余的隔离层，又能够为后续的薄膜生长提供良好的平坦度和界面态，提高存储器的可靠性和性能稳定性。
S2：在第一基板上制备多条沿Y方向延伸且沿X方向间隔排布的第一沟槽5，形成多个位于第二沟槽72底部的第一隔离结构31和多个沿Y方向延伸的初始墙体结构；初始墙体结构包括沿Y方向交替排列的初始有源柱和第二隔离结构32；多个第一隔离结构31和多个第二隔离结构32 形成隔离结构。
本实施例中，如图5所示为在第一基板上制备多条沿Y方向延伸且沿X方向间隔排布的第一沟槽5，形成多个位于第二沟槽72底部的第一隔离结构31和多个沿Y方向延伸的初始墙体结构后的结构示意图。图5中，第一沟槽5的延伸方向与第一隔离结构31所在的第二沟槽72的延伸方向垂直。如此，第一沟槽5与隔离结构纵横交错，从而使得初始衬底71被第一沟槽5和第二沟槽72分隔出多个初始有源柱。初始有源柱可以呈阵列分布，沿X方向，相邻两个初始有源柱被第一沟槽5分隔；沿Y方向，相邻两个初始有源柱被第二隔离结构32分隔。
示例性地，可以通过SADP工艺(Self Aligned Double Patterning,，自对准双重图案工艺)自第一基板的顶面向下刻蚀形成第一沟槽5，且将第一沟槽5的底壁高度控制在隔离结构底面的上方。也可以采用其他方式例如SAQP工艺(Self-Aligned Quadruple Patterning，自对准四重图案工艺)或SALELE(Self-Aligned Lithe-Etch-Lithe-Etch，自对准双线条光刻技术)获得第一沟槽5。
另外，由于第一沟槽5与最终形成的位线2呈夹角设置，且第一沟槽5与有源柱4邻接，因此，第一沟槽5可以后续作为字线槽来形成字线，从而进一步简化的半导体器件的制作工艺。
S3：在初始墙体结构的表面制备保护膜6；以保护膜6和各第一隔离结构31为掩膜，对第一沟槽5底面下方的初始衬底71和各初始有源柱靠近初始衬底71的部分进行刻蚀，得到多个通槽74、多个有源柱4、以及衬底1；通槽74沿X方向延伸并沿Y方向与第一隔离结构31交替排布，通槽74的底面高于第一隔离结构31的底面。
本实施例中，通过第一沟槽5与第二隔离结构32分隔有源柱4，由于第一沟槽5的底面高于第一隔离结构31的底面，从而使得后续去除部分初始衬底71和初始有源柱得到的通槽74能够被第一隔离结构31隔开，进而使得后续形成的掺杂结构也经第一隔离结构31隔开。
可选地，在上述步骤S3中，在初始墙体结构的表面制备保护膜6，包括：
沿第一沟槽5随形制备初始保护膜，初始保护膜覆盖第一沟槽5的槽底和初始墙体结构的表面。
去除第一沟槽5槽底的部分初始保护膜，得到覆盖初始墙体结构表面的保护膜6。
本实施例中，如图6所示为在初始墙体结构的表面制备保护膜6之后的结构示意图。去除第一沟槽5槽底的部分初始保护膜，以便后续由第一沟槽5的槽底向下对初始衬底71进行刻蚀。
可选地，保护膜6的材料可以为氮化硅。
可选地，在上述步骤S3中，对第一沟槽5底面下方的初始衬底71和各初始有源柱靠近初始衬底71的部分进行刻蚀，得到多个通槽74，包括：
采用四甲基氢氧化铵或氨过氧化氢混合溶液对第一沟槽5底面下方的初始衬底71和各初始有源柱靠近初始衬底71的部分进行湿法刻蚀。
本实施例中，如图7所示为对第一沟槽5底面下方的初始衬底71和各初始有源柱靠近初始衬底71的部分进行刻蚀，得到多个通槽74后的结构示意图。对第一沟槽5底面下方的初始衬底71进行湿法刻蚀，因第一沟槽5的侧壁有保护膜6保护和第一隔离结构31均不会被刻蚀掉，所以第一沟槽5底面下方的初始衬底71被刻蚀掉，形成多个凹槽。沿X方向同一行排布的凹槽之间相互刻穿，即将各初始有源柱靠近初始衬底71的部分进行湿法刻蚀，使得沿X方向同一行排布的凹槽相互连通以形成通槽74。沿垂直于衬底1的方向，通槽74的槽底高于第一隔离结构31的底面。由于通槽74内后续形成位线2，当通槽74的槽底低于第一隔离结构31的底面时，第一隔离结构31不能完全将相邻位线2隔离，相邻位线2之间存在连通的可能；当通槽74的槽底高于第一隔离结构31的底面时，第一隔离结构31可以完全将相邻位线2隔离，有利于降低相邻位线2之间的连通的可能性，从而有利于提升存储器的工作温度性。
示例性地，湿法蚀刻法采用四甲基氢氧化铵(TMAH溶液)作为清洗液。由于TMAH溶液对二氧化硅具有较高的选择比，所以在去除上述部分初始衬底71以达到开设凹槽目的的过程中，凹槽25能够顺利形成，且 在第一沟槽5上保护膜6的作用下，第一沟槽5的侧壁受损程度可以忽略不计。
应理解，上述的采用四甲基氢氧化铵作为腐蚀液仅为本申请的一个具体实施方式，在其他实施例中还可以采用氨过氧化氢混合溶液(APM溶液)或其他液体作为清洗液。
S4：在通槽74内制备位线2。
可选地，在上述步骤S4中，在通槽74内制备位线2，包括：
在各第一沟槽5下方的通槽74的侧壁上生长掺杂离子，形成多个掺杂结构，掺杂结构延伸至相邻两个有源柱4的下方，直至各掺杂结构连通，形成位线2。
本实施例中，在各第一沟槽5下方的通槽74的侧壁上生长掺杂离子，形成多个掺杂结构，掺杂结构不断的生长，直至各掺杂结构相连通，在整个通槽74内形成位线2。
具体地，采用CVD(Chemical Vapor Deposition，气相沉积)的工艺自第一沟槽5下方的通槽74的侧壁开始生长，并在通槽74内形成逐渐布满通槽74内部的掺杂结构。沿X方向，掺杂结构逐渐靠近并接触，形成位于通槽74内的位线2。其中，CVD工艺可以采用高密度等离子体化学气相沉积工艺或者等离子体增强化学气相沉积工艺。
通过掺杂离子形成的位线2，能够有利于降低位线2的电阻率，同时有利于提高迁移率，从而能够降低位线2与有源柱4之间的接触电阻，进而提高存储器的使用性能。
在其他实施例中，掺杂结构也可以是通过原子层沉积工艺形成，例如单原子层逐次沉积工艺，使沉积层获得均匀的厚度和优异的一致性，即提升了掺杂结构形成的位线2的性能。
可选地，掺杂结构中掺杂的离子包括磷(P)。
本实施例中，含有P离子的掺杂结构使形成的位线2具有低电阻率的特性，同时能够提高迁移率，有利于降低位线2与有源柱4之间的接触电阻，从而能够提高存储器的使用性能。
可以理解的，掺杂的离子也可以根据具体需求选择其他离子，例如锑(Sb)、砷(As)等，亦可以达到使掺杂结构形成的位线2具有低电阻率的特性，提高存储器的性能的目的。本实施例中，离子的掺杂浓度大于10 20每平方厘米，例如，离子的掺杂浓度不小于10 21且不大于10 22每平方厘米。
应用本申请实施例，至少能够实现如下有益效果：
1.本申请实施例中有源柱位于位线远离衬底的一侧，即位线位于有源柱的下方，代替了相关技术中位线与有源柱的侧面连接的方案，由此能够减小位线的占用面积，进而能够缩小晶体管的占用面积，有利于提高存储器的集成度。
2.本申请实施例中沿垂直于衬底的方向，第一隔离结构的底面比位线的底面靠近衬底的底面。当位线的底面低于第一隔离结构的底面时，第一隔离结构不能完全将相邻位线隔离，相邻位线之间存在连通的可能；当位线的底面高于第一隔离结构的底面时，第一隔离结构可以完全将相邻位线隔离，有利于降低相邻位线之间的连通的可能性，从而有利于提升存储器的工作稳定性。
本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。
在本申请的描述中，词语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方向或位置关系，为基于附图所示的示例性的方向或位置关系，是为了便于描述或简化描述本申请的实施例，而不是指示或暗示所指的装置或部件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示 相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
应该理解的是，虽然附图的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤的实施顺序并不受限于箭头所指示的顺序。除非本文中有明确的说明，否则在本申请实施例的一些实施场景中，各流程中的步骤可以按照需求以其他的顺序执行。而且，各流程图中的部分或全部步骤基于实际的实施场景，可以包括多个子步骤或者多个阶段。这些子步骤或者阶段中的部分或全部可以在同一时刻被执行，也可以在不同的时刻被执行在执行时刻不同的场景下，这些子步骤或者阶段的执行顺序可以根据需求灵活配置，本申请实施例对此不限制。
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请的方案技术构思的前提下，采用基于本申请技术思想的其他类似实施手段，同样属于本申请实施例的保护范畴。

Claims (13)

  1. 一种存储器，其特征在于，包括：
    衬底；
    多条位线，所述位线沿X方向延伸；
    隔离结构，包括多个第一隔离结构和多个第二隔离结构；所述第一隔离结构沿所述X方向延伸，各所述位线与各所述第一隔离结构沿Y方向交替排列，所述第一隔离结构的底面比所述位线的底面靠近所述衬底的底面；所述X方向与所述Y方向具有设计角度，且均平行于所述衬底；
    多个有源柱；
    沿所述X方向，交替设置有均沿所述Y方向延伸的第一沟槽和墙体结构；所述墙体结构包括沿所述Y方向交替排布的所述有源柱和所述第二隔离结构；所述有源柱位于所述位线远离衬底的一侧，所述第二隔离结构位于所述第一隔离结构远离所述衬底的一侧。
  2. 根据权利要求1所述的存储器，其特征在于，所述位线包括多个掺杂结构；沿所述X方向，所述掺杂结构位于相邻两个有源柱的下方。
  3. 根据权利要求2所述的存储器，其特征在于，所述掺杂结构的材料包括磷、锑和砷中至少一种。
  4. 根据权利要求1所述的存储器，其特征在于，所述第一沟槽的槽底露出部分所述位线的上表面和部分所述第一隔离结构的上表面。
  5. 根据权利要求1所述的存储器，其特征在于，所述墙体结构的上表面平齐。
  6. 根据权利要求5所述的存储器，其特征在于，所述墙体结构的表面设置保护膜。
  7. 根据权利要求6所述的存储器，其特征在于，所述保护膜的材料均包括二氧化硅和/或氮化硅。
  8. 一种电子设备，其特征在于，包括存储器，所述存储器包括：
    衬底；
    多条位线，所述位线沿X方向延伸；
    隔离结构，包括多个第一隔离结构和多个第二隔离结构；所述第一隔离 结构沿所述X方向延伸，各所述位线与各所述第一隔离结构沿Y方向交替排列，所述第一隔离结构的底面比所述位线的底面靠近所述衬底的底面；所述X方向与所述Y方向具有设计角度，且均平行于所述衬底；
    多个有源柱；
    沿所述X方向，交替设置有均沿所述Y方向延伸的第一沟槽和墙体结构；所述墙体结构包括沿所述Y方向交替排布的所述有源柱和所述第二隔离结构；所述有源柱位于所述位线远离衬底的一侧，所述第二隔离结构位于所述第一隔离结构远离所述衬底的一侧。
  9. 根据权利要求8所述的电子设备，其特征在于，所述位线的材料包括磷、锑和砷中至少一种。
  10. 一种存储器的制备方法，其特征在于，包括：
    在初始衬底上制备多条沿X方向延伸且沿Y方向间隔排布的第二沟槽；在所述第二沟槽内制备初始隔离结构，得到第一基板；
    在所述第一基板上制备多条沿Y方向延伸且沿X方向间隔排布的第一沟槽，形成多个位于所述第二沟槽底部的第一隔离结构和多个沿所述Y方向延伸的初始墙体结构；所述初始墙体结构包括沿Y方向交替排列的初始有源柱和第二隔离结构；多个所述第一隔离结构和多个所述第二隔离结构形成隔离结构；
    在所述初始墙体结构的表面制备保护膜；以所述保护膜和各所述第一隔离结构为掩膜，对所述第一沟槽底面下方的初始衬底和各所述初始有源柱靠近所述初始衬底的部分进行刻蚀，得到多个通槽、多个有源柱、以及衬底；所述通槽沿所述X方向延伸并沿所述Y方向与所述第一隔离结构交替排布，所述通槽的底面高于所述第一隔离结构的底面；
    在所述通槽内制备位线。
  11. 根据权利要求10所述的制备方法，其特征在于，在所述初始墙体结构的表面制备保护膜，包括：
    沿所述第一沟槽随形制备初始保护膜，所述初始保护膜覆盖所述第一沟槽的槽底和所述初始墙体结构的表面；
    去除所述第一沟槽槽底的部分初始保护膜，得到覆盖所述初始墙体结构表面的保护膜。
  12. 根据权利要求10所述的制备方法，其特征在于，对所述第一沟槽底 面下方的初始衬底和各所述初始有源柱靠近所述初始衬底的部分进行刻蚀，得到多个通槽，包括：
    采用四甲基氢氧化铵或氨过氧化氢混合溶液对所述第一沟槽底面下方的初始衬底和各所述初始有源柱靠近所述初始衬底的部分进行湿法刻蚀。
  13. 根据权利要求10所述的制备方法，其特征在于，在所述通槽内制备位线，包括：
    在各所述第一沟槽下方的通槽的侧壁上生长掺杂离子，形成多个掺杂结构，所述掺杂结构延伸至相邻两个有源柱的下方，直至各掺杂结构连通，形成所述位线。
PCT/CN2022/140158 2022-07-22 2022-12-19 存储器及其制备方法、电子设备 WO2024016584A1 (zh)

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CN113611671A (zh) * 2021-08-06 2021-11-05 长鑫存储技术有限公司 北京超弦存储器研究院 半导体结构及其制备方法
CN113644062A (zh) * 2020-04-27 2021-11-12 长鑫存储技术有限公司 半导体结构及其形成方法、存储器及其形成方法
CN114141712A (zh) * 2021-11-30 2022-03-04 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
CN114420644A (zh) * 2022-01-07 2022-04-29 长鑫存储技术有限公司 半导体结构及其制造方法

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CN113644062A (zh) * 2020-04-27 2021-11-12 长鑫存储技术有限公司 半导体结构及其形成方法、存储器及其形成方法
CN113611671A (zh) * 2021-08-06 2021-11-05 长鑫存储技术有限公司 北京超弦存储器研究院 半导体结构及其制备方法
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