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WO2022040836A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2022040836A1
WO2022040836A1 PCT/CN2020/110688 CN2020110688W WO2022040836A1 WO 2022040836 A1 WO2022040836 A1 WO 2022040836A1 CN 2020110688 W CN2020110688 W CN 2020110688W WO 2022040836 A1 WO2022040836 A1 WO 2022040836A1
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layer
type semiconductor
fabricating
epitaxial structure
semiconductor layer
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PCT/CN2020/110688
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English (en)
French (fr)
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向鹏
程凯
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苏州晶湛半导体有限公司
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Priority to PCT/CN2020/110688 priority Critical patent/WO2022040836A1/zh
Priority to CN202080104572.8A priority patent/CN116235302A/zh
Publication of WO2022040836A1 publication Critical patent/WO2022040836A1/zh
Priority to US17/968,981 priority patent/US12183576B2/en

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
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    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/04—Pattern deposit, e.g. by using masks
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    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
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    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
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Definitions

  • the present application relates to the field of semiconductors, and in particular, to a semiconductor structure and a preparation method thereof.
  • the present application provides a semiconductor structure and a preparation method thereof, which can prevent the doping elements in the first epitaxial structure from precipitating upward into the upper epitaxial structure, ensure the electron mobility of the upper epitaxial structure, and improve the performance of the device.
  • the fabrication method includes the following steps:
  • steps S2 and S3 are repeated N times until the concentration of the doping element in the first epitaxial structure is lower than the preset value.
  • the first epitaxial structure is a buffer layer, and the doping element is located in the buffer layer; the second epitaxial structure at least includes a channel layer and a barrier layer that are stacked in sequence.
  • the first epitaxial structure includes a buffer layer, a first N-type semiconductor layer, a second N-type semiconductor layer, and a P-type semiconductor layer that are stacked in sequence, and the doping element is located in the P-type semiconductor layer;
  • the second epitaxial structure includes at least a third N-type semiconductor layer.
  • the first epitaxial structure includes at least a buffer layer and a first P-type semiconductor layer that are stacked in sequence, and the doping element is located in the P-type semiconductor layer;
  • the second epitaxial structure at least includes N-type semiconductor layers that are stacked in sequence. a semiconductor layer and a second P-type semiconductor layer.
  • the first N-type semiconductor layer is an N-type heavily doped GaN layer
  • the second N-type semiconductor layer is an N-type lightly doped GaN layer
  • the third N-type semiconductor layer is an N-type heavily doped GaN layer Doped GaN layer.
  • the first P-type semiconductor layer is a P-type GaN layer
  • the N-type semiconductor layer is an N-type GaN layer
  • the second P-type semiconductor layer is a P-type GaN layer.
  • the material of the sacrificial layer includes one or a combination of InN, InGaN, InAlN, InAlGaN, and GaN.
  • the thickness of the sacrificial layer may be 1 nm-1 um.
  • a protective layer is further included between the first epitaxial structure and the sacrificial layer.
  • the material of the protective layer includes one or more combinations of AlN, AlInGaN, and AlGaN.
  • the doping element in the first epitaxial structure is iron or magnesium.
  • the preset value is below the order of 2 ⁇ 10 18 atoms/cm 3 .
  • steps S1 , S2 , S3 and S4 are sequentially completed in the same reaction chamber.
  • step S3 the temperature in the reaction chamber is higher than 400 degrees Celsius, and gas is used to etch the sacrificial layer.
  • the gas may be hydrogen, ammonia, hydrogen chloride, or chlorine.
  • step S3 the sacrificial layer is completely etched or partially etched.
  • the substrate may be Si, SiC, GaN, AlN, or sapphire.
  • the sacrificial layer is formed on the first epitaxial structure and the sacrificial layer is etched, so that the concentration of the doping element in the first epitaxial structure is lower than a predetermined value, thereby preventing The doping elements in the first epitaxial structure are precipitated upward into the upper epitaxial structure to ensure the mobility of electrons in the upper epitaxial structure, so as to improve the performance of the device.
  • the iron and magnesium doping atoms in the first epitaxial structure can be precipitated and gathered on the surface of the sacrificial layer in contact with the first epitaxial structure and in the sacrificial layer.
  • the sacrificial layer is etched, so as to achieve the effect of reducing or removing the epitaxial structure in which iron and magnesium dopant atoms are precipitated upward into the upper layer.
  • the dopant atoms will also gather on the surface of the first epitaxial structure due to the surface energy, direct etching of the first epitaxial structure will cause defects in the first epitaxial structure.
  • the material of the first epitaxial structure is also difficult to etch.
  • the present invention also proposes to first grow a protective layer on the first epitaxial layer structure before growing the sacrificial layer, and the protective layer materials are AlN, AlInGaN, One or more combinations of AlGaN.
  • FIG. 1(a)-FIG. 1(f) are process flow diagrams of a method for fabricating a semiconductor structure and a method for fabricating a semiconductor structure according to Embodiment 1 of the present application.
  • FIG. 2( f ) are process flow diagrams of a method for fabricating a semiconductor structure and a method for fabricating a semiconductor structure according to Embodiment 2 of the present application.
  • FIG. 3(a)-FIG. 3(f) are process flow diagrams of a method for fabricating a semiconductor structure and a method for fabricating a semiconductor structure according to Embodiment 3 of the present application.
  • This embodiment provides a method for preparing a semiconductor structure, and the method for preparing a semiconductor structure includes the following steps:
  • Step 100 forming a first epitaxial structure on the substrate, and the first epitaxial structure is doped with doping elements;
  • Step 200 forming a sacrificial layer on the first epitaxial structure
  • Step 300 etching the sacrificial layer
  • Step 400 Continue to grow an epitaxial structure on the first epitaxial structure on which the sacrificial layer is etched;
  • steps 200 and 300 are repeated N times until the concentration of the doping element in the first epitaxial structure is lower than the preset value.
  • the concentration of the doping element in the first epitaxial structure is lower than a predetermined value, thereby preventing the doping element in the first epitaxial structure from rising upward
  • Precipitation into the epitaxial structure of the upper layer ensures the mobility of electrons in the epitaxial structure of the upper layer, so as to improve the performance of the device.
  • iron and magnesium doping atoms can be gathered on the surface of the sacrificial layer in contact with the first epitaxial structure and in the sacrificial layer, and then the sacrificial layer can be etched, thereby To achieve the effect of reducing or removing iron and magnesium doping atoms that precipitate upward into the epitaxial structure of the upper layer.
  • the first epitaxial structure is a buffer layer
  • the second epitaxial structure at least includes a channel layer and a barrier layer.
  • Each step specifically includes:
  • Step 100 As shown in FIG. 1( a ), a buffer layer 20 is formed on the substrate 10 , the buffer layer 20 is doped with doping elements, wherein the doping element in the buffer layer 20 is iron or magnesium, and the buffer layer 20 is Layer 20 is a Group III nitride epitaxial layer.
  • the material of the substrate 10 includes Si, SiC, GaN, AlN, and sapphire.
  • Step 200 As shown in FIG. 1( b ), a sacrificial layer 30 is formed on the buffer layer 20 , so that iron and magnesium doping atoms in the buffer layer 20 are precipitated and gathered on the surface of the sacrificial layer 30 in contact with the buffer layer 20 and
  • the material of the sacrificial layer 30 includes one or more combinations of InN, InGaN, InAlN, InAlGaN, and GaN, and the thickness is 1 nm-1 um.
  • Step 300 As shown in FIG. 1( c ), the sacrificial layer 30 is etched, so that the iron and magnesium doping atoms precipitated in the sacrificial layer 30 are taken away together, and the doping enriched on the surface of the buffer layer 20 is reduced element content.
  • the temperature in the reaction chamber is higher than 400 degrees Celsius, so that the sacrificial layer can be directly etched in the reaction chamber without using other tools or etching methods.
  • the etching sacrificial layer 30 is etched with a gas, and the etching gas is preferably one or more combinations of hydrogen, ammonia, hydrogen chloride, and chlorine.
  • Step 400 forming a channel layer 40 and a barrier layer 50 on the buffer layer 20 after the etching of the sacrificial layer 30 is completed.
  • a protective layer may also be included between the substrate 10 and the buffer layer 20, and the material is one or a combination of AlN, AlInGaN, and AlGaN.
  • step 300 there are two situations after the sacrificial layer 30 is etched.
  • the first situation as shown in FIG. 1(c), the sacrificial layer 30 still has a part on the buffer layer; As shown in FIG. 1(e), the sacrificial layer 30 is completely etched away.
  • step 400 in step 400, as shown in FIG. 1(d), the channel layer 40 and the barrier layer 50 are formed on the residual sacrificial layer 30; in the second case As shown in FIG. 1( f ), the channel layer 40 and the barrier layer 50 are directly formed on the buffer layer 20 .
  • the doping element repeats steps 200 and 300 for N times until the concentration of the doping element in the buffer layer 20 is lower than the preset value.
  • the preset value is defined according to the requirements of different device parameters, and then the number of times that steps 200 and 300 need to be repeated is determined according to the preset value.
  • the number N of repeating steps 200 and 300 is less than or equal to 100,000.
  • Step 100, step 200, step 300 and step 400 are completed in sequence in the same reaction chamber, and the epitaxial material does not need to be removed from the reaction chamber in the middle. The risk of surface contamination by foreign impurities due to the removal of epitaxial material out of the reaction chamber is eliminated.
  • the concentration of the doping element in the buffer layer is lower than a predetermined value, thereby preventing the doping element in the buffer layer from precipitating upward and entering the upper structure, ensuring that The mobility of electrons in the channel layer, as well as improving the performance of the device.
  • iron and magnesium doping atoms can be gathered on the surface of the sacrificial layer in contact with the buffer layer and in the sacrificial layer, and then the sacrificial layer can be etched to reduce or remove iron , The effect of magnesium dopant atoms precipitating upwards into the superstructure.
  • the fabrication steps of the semiconductor structure fabrication method of this embodiment are basically the same as those in Embodiment 1, except that the first epitaxial structure includes a buffer layer and a first N-type semiconductor layer that are stacked in sequence. , a second N-type semiconductor layer and a P-type semiconductor layer, wherein the doping element is located in the P-type semiconductor layer; the second epitaxial structure at least includes a third N-type semiconductor layer.
  • Step 100 As shown in FIG. 2( a ), a first epitaxial structure is formed on the substrate in sequence, and the first epitaxial structure includes the buffer layer 20 , the first N-type semiconductor layer 61 , the second N-type semiconductor layer 62 and the P
  • the P-type semiconductor layer 70 is doped with doping elements, wherein the doping element in the P-type semiconductor layer 70 is iron or magnesium; the buffer layer 20 is the first epitaxial structure of group III nitride.
  • Step 200 As shown in FIG. 2(b), a sacrificial layer 30 is formed on the P-type semiconductor layer 70, so that iron and magnesium doping atoms in the P-type semiconductor layer 70 are precipitated and gathered on the sacrificial layer 30 and the P-type semiconductor layer
  • the material of the sacrificial layer 30 includes one or more combinations of InN, InGaN, InAlN, InAlGaN, and GaN, and the thickness is 1 nm-1 um.
  • Step 300 As shown in FIG. 2( c ), the sacrificial layer 30 is etched, so that the iron and magnesium doping atoms precipitated in the sacrificial layer 30 are taken away together, and the concentration of the doped atoms on the surface of the P-type semiconductor layer 70 is reduced. content of dopant elements.
  • the temperature in the reaction chamber is higher than 400 degrees Celsius, so that the sacrificial layer can be directly etched in the reaction chamber without using other tools or etching methods.
  • the sacrificial layer 30 is etched with a gas, and the etched gas is preferably one or a combination of hydrogen, ammonia, hydrogen chloride, and chlorine.
  • Step 400 As shown in FIG. 2( d ), a third N-type semiconductor layer 63 is formed on the P-type semiconductor layer 70 where the etching of the sacrificial layer 30 is completed.
  • the first N-type semiconductor layer 61 is an N-type heavily doped GaN layer; the second N-type semiconductor layer 62 is an N-type lightly doped GaN layer; the P-type semiconductor layer 70 is a P-type GaN layer; the third N-type semiconductor layer 63 It is an N-type heavily doped GaN layer.
  • step 300 after the sacrificial layer 30 is etched, there are two situations.
  • the first situation as shown in FIG. 70; the second case: as shown in FIG. 2(e), the sacrificial layer 30 is all etched away.
  • a third N-type semiconductor layer 63 is formed on the residual sacrificial layer 30; in the second case, as shown in FIG. 2(d) As shown in FIG. 2( f ), the third N-type semiconductor layer 63 is directly formed on the P-type semiconductor layer 70 .
  • steps 200 and 300 are repeated N times until the concentration of the doping element in the P-type semiconductor layer 70 is lower than the preset value.
  • the preset value is defined according to the requirements of different device parameters, and then the number of times that steps 200 and 300 need to be repeated is determined according to the preset value.
  • the number N of repeating steps 200 and 300 is less than or equal to 100,000.
  • Step 100, step 200, step 300 and step 400 are completed in sequence in the same reaction chamber, and the epitaxial material does not need to be removed from the reaction chamber in the middle. The risk of surface contamination by foreign impurities due to the removal of epitaxial material out of the reaction chamber is eliminated.
  • the concentration of the doping element in the P-type semiconductor layer 70 is lower than a predetermined value, thereby preventing doping in the P-type semiconductor layer 70
  • the impurity elements are precipitated upward into the upper structure, ensuring the mobility of electrons in the channel layer, and improving the performance of the device.
  • iron and magnesium doping atoms can be gathered on the surface of the sacrificial layer 30 in contact with the buffer layer, and then the sacrificial layer can be etched to reduce or remove iron , The effect of magnesium dopant atoms precipitating upwards into the superstructure.
  • the preparation steps of the preparation method of the semiconductor structure in this embodiment are basically the same as the preparation steps in Embodiment 1, and the difference lies in:
  • the first epitaxial structure at least includes a buffer layer and a first P-type semiconductor layer stacked in sequence, and the doping element is located in the P-type semiconductor layer;
  • the second epitaxial structure at least includes an N-type semiconductor layer and a first P-type semiconductor layer stacked in sequence. Two P-type semiconductor layers.
  • Step 100 As shown in FIG. 3( a ), a first epitaxial structure is formed on the substrate 10 , and the first epitaxial structure includes a buffer layer 20 and a first P-type semiconductor layer 81 ; wherein the buffer layer 20 is group III nitrogen
  • the first P-type semiconductor layer 81 is doped with doping elements, and the doping elements are iron or magnesium.
  • Step 200 As shown in FIG. 3( b ), a sacrificial layer 30 is formed on the first P-type semiconductor layer 81 , so that the iron and magnesium doping atoms in the first P-type semiconductor layer 81 are precipitated and gathered in the sacrificial layer 30
  • the material of the sacrificial layer 30 includes one or more combinations of InN, InGaN, InAlN, InAlGaN, and GaN, and the thickness is 1 nm-1 um.
  • Step 300 As shown in FIG. 3( c ), the sacrificial layer 30 is etched, so that the iron and magnesium doping atoms precipitated in the sacrificial layer 30 are taken away together, and the concentration of the first P-type semiconductor layer 81 is reduced.
  • the content of dopant elements on the surface Preferably, the temperature in the reaction chamber is higher than 400 degrees Celsius, so that the sacrificial layer can be directly etched in the reaction chamber without using other tools or etching methods.
  • the sacrificial layer 30 is etched with a gas, and the etched gas is preferably one or a combination of hydrogen, ammonia, hydrogen chloride, and chlorine.
  • Step 400 As shown in FIG. 3( d ), an N-type semiconductor layer 90 and a second P-type semiconductor layer 82 are sequentially formed on the first P-type semiconductor layer 81 on which the etching of the sacrificial layer 30 is completed.
  • the first P-type semiconductor layer 81 is a P-type GaN layer; the N-type semiconductor layer 90 is an N-type GaN layer; and the second P-type semiconductor layer 82 is a P-type GaN layer.
  • step 300 after the sacrificial layer 30 is etched, there are two situations.
  • the first situation as shown in FIG. On the semiconductor layer 81; the second case: as shown in FIG. 3(e), the sacrificial layer 30 is all etched away.
  • step 400 in step 400, as shown in FIG. 3(d), an N-type semiconductor layer 90 is formed on the remaining sacrificial layer 30; in the second case, as shown in FIG. 3 As shown in (f), the N-type semiconductor layer 90 is directly formed on the first P-type semiconductor layer 81 .
  • steps 200 and 300 are repeated N times until the concentration of the doping element in the first P-type semiconductor layer 81 is lower than the preset value.
  • the preset value is defined according to the requirements of different device parameters, and then the number of times that steps 200 and 300 need to be repeated is determined according to the preset value.
  • the number N of repeating steps 200 and 300 is less than or equal to 100,000.
  • Step 100, step 200, step 300 and step 400 are completed in sequence in the same reaction chamber, and the epitaxial material does not need to be removed from the reaction chamber in the middle. The risk of surface contamination by foreign impurities due to the removal of epitaxial material out of the reaction chamber is eliminated.
  • the concentration of the doping element in the first P-type semiconductor layer 81 is lower than a predetermined value, thereby preventing the first P-type
  • the doping elements in the semiconductor layer 81 are precipitated upward into the upper layer structure, so as to ensure the mobility of electrons in the channel layer and improve the performance of the device.
  • iron and magnesium doping atoms can be gathered on the surface of the sacrificial layer 30 in contact with the buffer layer, and then the sacrificial layer can be etched to reduce or Remove the effect of iron and magnesium doping atoms precipitating upwards into the superstructure.

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Abstract

本申请提供一种半导体结构及其制备方法。该半导体结构包括：衬底；依次层叠设置于所述衬底上的外延层以及外延结构；其中，所述外延层中掺杂有掺杂元素，且在形成过程中，通过在所述外延层上形成牺牲层并反复刻蚀所述牺牲层，以使所述外延层中的掺杂元素的浓度低于一预设值。该制作方法用于制备该半导体结构。本申请通过在外延层上形成牺牲层并反复刻蚀牺牲层，以使外延层中的掺杂元素的浓度低于一预设值，从而防止外延层中的掺杂元素向上析出进入上层结构，保证沟道层电子的迁移率，以及提高器件的性能。

Description

半导体结构及其制备方法 技术领域
本申请涉及半导体领域，尤其涉及一种半导体结构及其制备方法。
背景技术
在制作半导体器件中，通常在使用GaN电力电子及射频材料时，需要引入铁、镁等掺杂元素来提高外延层的电阻率，减少外延层的漏电。但铁、镁存在所谓的记忆效应，即，外延层中的铁、镁掺杂元素会向上析出进入上层的外延结构，使得并不需要掺杂的上层结构也存在大量的铁、镁掺杂元素，这就会降低上层的外延结构电子的迁移率，进而降低器件的性能。
因此，如何防止外延层中的掺杂元素向上析出进入上层结构，是目前亟待解决的难题。
发明内容
本申请提供一种半导体结构及其制备方法，能够防止第一外延结构中的掺杂元素向上析出进入上层的外延结构，保证上层的外延结构的电子的迁移率，以及提高器件的性能。
为实现上述目的，根据本申请实施例提供一种半导体结构的制作方法，所述制作方法包括以下步骤：
S1：在衬底上形成第一外延结构，所述第一外延结构中掺杂有掺杂元素；
S2：在所述第一外延结构上形成牺牲层；
S3：刻蚀所述牺牲层；
S4：在完成刻蚀所述牺牲层的所述第一外延结构上继续生长第二外延结构；
其中，在进入步骤S4前，重复N次步骤S2和S3，直至所述第一外延结构中的掺杂元素的浓度低于预设值。
可选的，所述第一外延结构为缓冲层，所述掺杂元素位于缓冲层中；第二外延结构至少包括依次层叠设置的沟道层以及势垒层。
可选的，所述第一外延结构包括依次层叠设置的缓冲层、第一N型半导体层、第二N型半导体层以及P型半导体层，所述掺杂元素位于P型半导体层中；第二外延结构至少包括第三N型半导体层。
可选的，所述第一外延结构至少包括依次层叠设置的缓冲层、第一P型半导体层，所述掺杂元素位于P型半导体层中；第二外延结构至少包括依次层叠设置的N型半导体层和第二P型半导体层。
可选的，所述第一N型半导体层为N型重掺杂GaN层；所述第二N型半导体层为N型轻掺杂GaN层；所述第三N型半导体层为N型重掺杂GaN层。
可选的，所述第一P型半导体层为P型GaN层；所述N型半导体层为N型GaN层；所述第二P型半导体层为P型GaN层。
可选的，所述牺牲层的材料包括InN、InGaN、InAlN、InAlGaN、GaN中的一种或多种组合。
可选的，所述牺牲层的厚度可以是1nm–1um。
可选的，所述第一外延结构与牺牲层之间还包括保护层。
可选的，所述保护层的材料包括AlN、AlInGaN、AlGaN中的一种或多种组合。
可选的，所述第一外延结构中的掺杂元素为铁或镁。
可选的，所述预设值为2×10 18个原子/cm 3量级以下。
可选的，步骤S1、S2、S3以及S4在同一个反应腔内依次完成。
可选的，在步骤S3中，反应腔内的温度高于400摄氏度，使用气体对所述牺牲层进行刻蚀。
可选的，所述气体可以为氢气、氨气、氯化氢、氯气。
可选的，在步骤S3中，所述牺牲层，被完全刻蚀或部分刻蚀。
可选的，所述衬底可以为Si、SiC、GaN、AlN、蓝宝石。
上述实施例的半导体结构及其制备方法中，通过在第一外延结构上形成牺牲层，并刻蚀牺牲层，以使第一外延结构中掺杂元素的浓度低于一预设值，从而防止第一外延结构中的掺杂元素向上析出进入上层的外延结构，保证上层的外延结构的电子的迁移率，以提高器件的性能。
具体的，通过在第一外延结构上形成牺牲层，能够使第一外延结构中的铁、镁掺杂原子析出并聚集在牺牲层与第一外延结构接触的表面及牺牲层内，再通过对牺牲层进行刻蚀，从而达到降低或者去除铁、镁掺杂原子向上析出进入上层的外延结构的效果。虽然掺杂原子也会因表面能的原因聚集在第一外延结构的表面，但是直接对第一外延结构刻蚀会使第一外延结构产生缺陷，另外，第一外延结构的材料也较难刻蚀。进一步的，为了减少对刻蚀过程对第一外延层结构的破坏，本发明还提出在生长牺牲层之前，首先在第一外延层结构上生长一层保护层，保护层材料为AlN、AlInGaN、AlGaN中的一种或多种组合。
附图说明
图1(a)-图1(f)是本申请实施例1的半导体结构的制备方法以及半导体结构的制备方法的工艺流程图。
图2(a)-图2(f)是本申请实施例2的半导体结构的制备方法以及半导体结构的制备方法的工艺流程图。
图3(a)-图3(f)是本申请实施例3的半导体结构的制备方法以及半导体结构的制备方法的工艺流程图。
附图标记说明
衬底10
缓冲层20
牺牲层30
沟道层40
势垒层50
第一N型半导体层61
第二N型半导体层62
第三N型半导体层63
P型半导体层70
第一P型半导体层81
第二P型半导体层82
N型半导体层90
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。除非另作定义，本申请使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请说明书以及权利要求书中使用的“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。“多个”包括两个，相当于至少两个。在本申请 说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
实施例1
本实施例提供一种半导体结构的制备方法，所述半导体结构的制备方法包括以下步骤：
步骤100：在衬底上形成第一外延结构，所述第一外延结构中掺杂有掺杂元素；
步骤200：在所述第一外延结构上形成牺牲层；
步骤300：刻蚀所述牺牲层；
步骤400：在完成刻蚀所述牺牲层的所述第一外延结构上继续生长外延结构；
其中，在进入步骤400前，重复N次步骤200和步骤300，直至所述第一外延结构中的掺杂元素的浓度低于所述预设值。
这样，通过在第一外延结构上形成牺牲层并刻蚀牺牲层，以使第一外延结构中的掺杂元素的浓度低于一预设值，从而防止第一外延结构中的掺杂元素向上析出进入上层的外延结构，保证上层的外延结构的电子的迁移率，以提高器件的性能。也就是说，通过在第一外延结构上形成牺牲层，能够将铁、镁掺杂原子聚集在牺牲层与第一外延结构接触的表面及牺牲层内，再通过对牺牲层进行刻蚀，从而达到降低或者去除铁、镁掺杂原子向上析出进入上层的外延结构的效果。
在本实施例的半导体结构的制备方法中，具体地，所述第一外延结构为缓冲层，所述第二外延结构至少包括沟道层以及势垒层。每步骤具体包括：
步骤100：如图1(a)所示，在衬底10上形成缓冲层20，缓冲层20中掺杂有掺杂元素，其中，缓冲层20中的掺杂元素为铁或镁，且缓冲层20为三族氮化物外延层。衬底10的材料包括Si、SiC、GaN、AlN、蓝宝石。
步骤200：如图1(b)所示，在缓冲层20上形成牺牲层30，以使缓冲层20中的铁、镁掺杂原子析出并聚集在牺牲层30与缓冲层20接触的表面及牺牲层30内，牺牲层30的材料包括InN、InGaN、InAlN、InAlGaN、GaN中的一种或多种组合，厚度为1nm–1um。
步骤300：如图1(c)所示，刻蚀牺牲层30，从而将析出在牺牲层30中的铁、镁掺杂原子一同带走，并减少富集在缓冲层20的表面的掺杂元素的含量。较佳的，在反应腔内温度高于400摄氏度，以实现在反应腔中直接对牺牲层进行刻蚀，而不用借助其他工具或者刻蚀方法。使用气体对蚀牺牲层30进行刻蚀，刻蚀的气体优选为氢气、 氨气、氯化氢、氯气中的一种或多种组合。
步骤400：在完成刻蚀牺牲层30的缓冲层20上形成沟道层40以及势垒层50。
在步骤100中，衬底10与缓冲层20之间还可以包含保护层，材料为AlN、AlInGaN、AlGaN中的一种或多种组合。
在步骤300中，在刻蚀完牺牲层30后存在两种情况，第一种情况：如图1(c)所示，牺牲层30还留有部分在缓冲层上；第二种情况：如图1(e)所示，牺牲层30全部被刻蚀掉。
相对应的，在第一种情况下，在步骤400中，如图1(d)所示，是在残留的牺牲层30上形成沟道层40以及势垒层50；在第二种情况下，如图1(f)所示，是在缓冲层20上直接形成沟道层40以及势垒层50。
在进入步骤400前，掺杂元素重复N次步骤200和步骤300，直至缓冲层20中的掺杂元素的浓度低于所述预设值。其中，所述预设值根据不同器件参数的需求来进行限定，然后根据该预设值来确定需要重复步骤200和步骤300的次数。较佳地，重复步骤200和步骤300的次数N小于等于10万。
步骤100、步骤200、步骤300以及步骤400在同一个反应腔内依次完成，中间不需要把外延材料移出该反应腔，一方面从而能够提高制备效率，以及提高成品良率；另一方面，避免了外延材料移出反应腔而导致表面受到外界杂质的污染的风险。
这样，通过在缓冲层上形成牺牲层并刻蚀牺牲层，以使缓冲层中的掺杂元素的浓度低于一预设值，从而防止缓冲层中的掺杂元素向上析出进入上层结构，保证沟道层电子的迁移率，以及提高器件的性能。
具体的，通过在缓冲层上形成牺牲层，能够将铁、镁掺杂原子聚集在牺牲层与缓冲层接触的表面及牺牲层内，再通过对牺牲层进行刻蚀，从而达到降低或者去除铁、镁掺杂原子向上析出进入上层结构的效果。
实施例2
本实施例的半导体结构的制备方法的制备步骤基本和实施例1中的制备步骤相同，其不同的之处在于，所述第一外延结构包括依次层叠设置的缓冲层、第一N型半导体层、第二N型半导体层以及P型半导体层，所述掺杂元素位于P型半导体层中；第二外延结构至少包括第三N型半导体层。
步骤100：如图2(a)所示，在衬底上依次形成第一外延结构，该第一外延结构包括缓冲层20、第一N型半导体层61、第二N型半导体层62以及P型半导体层70，P型半导体层70中掺杂有掺杂元素，其中，P型半导体层70中的掺杂元素为铁或镁；缓冲层20为三族氮 化物第一外延结构。
步骤200：如图2(b)所示，在P型半导体层70上形成牺牲层30，以使P型半导体层70中的铁、镁掺杂原子析出并聚集在牺牲层30与P型半导体层70接触的表面，牺牲层30的材料包括InN、InGaN、InAlN、InAlGaN、GaN中的一种或多种组合，厚度为1nm–1um。
步骤300：如图2(c)所示，刻蚀牺牲层30，从而将析出在牺牲层30中的铁、镁掺杂原子一同带走，并减少富集在P型半导体层70的表面的掺杂元素的含量。较佳的，在反应腔内温度高于400摄氏度，以实现在反应腔中直接对牺牲层进行刻蚀，而不用借助其他工具或者刻蚀方法。使用气体对蚀牺牲层30进行刻蚀，刻蚀的气体优选为氢气、氨气、氯化氢、氯气中的一种或多种组合。
步骤400：如图2(d)所示，在完成刻蚀牺牲层30的P型半导体层70上形成第三N型半导体层63。
第一N型半导体层61为N型重掺杂GaN层；第二N型半导体层62为N型轻掺杂GaN层；P型半导体层70为P型GaN层；第三N型半导体层63为N型重掺杂GaN层。
与实施例1相同，在步骤300中，在刻蚀完牺牲层30后存在两种情况，第一种情况：如图2(c)所示，牺牲层30还留有部分在P型半导体层70上；第二种情况：如图2(e)所示，牺牲层30全部被刻蚀掉。
相对应的，在第一种情况下，在步骤400中，如图2(d)所示，是在残留的牺牲层30上形成第三N型半导体层63；在第二种情况下，如图2(f)所示，是在P型半导体层70上直接形成第三N型半导体层63。
在进入步骤400前，重复N次步骤200和步骤300，直至P型半导体层70中的掺杂元素的浓度低于所述预设值。其中，所述预设值根据不同器件参数的需求来进行限定，然后根据该预设值来确定需要重复步骤200和步骤300的次数。较佳地，重复步骤200和步骤300的次数N小于等于10万。
步骤100、步骤200、步骤300以及步骤400在同一个反应腔内依次完成，中间不需要把外延材料移出该反应腔，一方面从而能够提高制备效率，以及提高成品良率；另一方面，避免了外延材料移出反应腔而导致表面受到外界杂质的污染的风险。
这样，通过在P型半导体层70上形成牺牲层并刻蚀牺牲层，以使P型半导体层70中的掺杂元素的浓度低于一预设值，从而防止P型半导体层70中的掺杂元素向上析出进入上层结构，保证沟道层电子的迁移率，以及提高器件的性能。
具体的，通过在P型半导体层70上形成牺牲层，能够将铁、镁 掺杂原子聚集在牺牲层30与缓冲层接触的表面，再通过对牺牲层进行刻蚀，从而达到降低或者去除铁、镁掺杂原子向上析出进入上层结构的效果。
实施例3
本实施例的半导体结构的制备方法的制备步骤基本和实施例1中的制备步骤相同，其不同的之处在于，
所述第一外延结构至少包括依次层叠设置的缓冲层、第一P型半导体层，所述掺杂元素位于P型半导体层中；第二外延结构至少包括依次层叠设置的N型半导体层和第二P型半导体层。
具体的如下：
步骤100：如图3(a)所示，在衬底10上形成第一外延结构，该第一外延结构包括缓冲层20、第一P型半导体层81；其中，缓冲层20为三族氮化物外延层；第一P型半导体层81中掺杂有掺杂元素，掺杂元素为铁或镁。
步骤200：如图3(b)所示，在第一P型半导体层81上形成牺牲层30，以使第一P型半导体层81中的铁、镁掺杂原子析出并聚集在牺牲层30与第一P型半导体层81接触的表面及牺牲层30内，牺牲层30的材料包括InN、InGaN、InAlN、InAlGaN、GaN中的一种或多种组合，厚度为1nm–1um。
步骤300：如图3(c)所示，刻蚀牺牲层30，从而将析出在牺牲层30中的铁、镁掺杂原子一同带走，并减少富集在第一P型半导体层81的表面的掺杂元素的含量。较佳的，在反应腔内温度高于400摄氏度，以实现在反应腔中直接对牺牲层进行刻蚀，而不用借助其他工具或者刻蚀方法。使用气体对蚀牺牲层30进行刻蚀，刻蚀的气体优选为氢气、氨气、氯化氢、氯气中的一种或多种组合。
步骤400：如图3(d)所示，在完成刻蚀牺牲层30的第一P型半导体层81上依次形成N型半导体层90以及第二P型半导体层82。
第一P型半导体层81为P型GaN层；N型半导体层90为N型GaN层；以及第二P型半导体层82为P型GaN层。
与实施例1相同，在步骤300中，在刻蚀完牺牲层30后存在两种情况，第一种情况：如图3(c)所示，牺牲层30还留有部分在第一P型半导体层81上；第二种情况：如图3(e)所示，牺牲层30全部被刻蚀掉。
相对应的，在第一种情况下，在步骤400中，如图3(d)所示，是在残留的牺牲层30上形成N型半导体层90；在第二种情况下，如图3(f)所示，是在第一P型半导体层81上直接形成N型半导体层90。
在进入步骤400前，重复N次步骤200和步骤300，直至第 一P型半导体层81中的掺杂元素的浓度低于所述预设值。其中，所述预设值根据不同器件参数的需求来进行限定，然后根据该预设值来确定需要重复步骤200和步骤300的次数。较佳地，重复步骤200和步骤300的次数N小于等于10万。
步骤100、步骤200、步骤300以及步骤400在同一个反应腔内依次完成，中间不需要把外延材料移出该反应腔，一方面从而能够提高制备效率，以及提高成品良率；另一方面，避免了外延材料移出反应腔而导致表面受到外界杂质的污染的风险。
这样，通过在第一P型半导体层81上形成牺牲层并刻蚀牺牲层，以使第一P型半导体层81中的掺杂元素的浓度低于一预设值，从而防止第一P型半导体层81中的掺杂元素向上析出进入上层结构，保证沟道层电子的迁移率，以及提高器件的性能。
具体的，通过在第一P型半导体层81上形成牺牲层，能够将铁、镁掺杂原子聚集在牺牲层30与缓冲层接触的表面，再通过对牺牲层进行刻蚀，从而达到降低或者去除铁、镁掺杂原子向上析出进入上层结构的效果。以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (17)

  1. 一种半导体结构的制作方法，其特征在于，所述制作方法包括以下步骤：
    S1：在衬底上形成第一外延结构，所述第一外延结构中掺杂有掺杂元素；
    S2：在所述第一外延结构上形成牺牲层；
    S3：刻蚀所述牺牲层；
    S4：在完成刻蚀所述牺牲层的所述第一外延结构上继续生长第二外延结构；
    其中，在进入步骤S4前，重复N次步骤S2和S3，直至所述第一外延结构中的掺杂元素的浓度低于预设值。
  2. 如权利要求1所述的半导体结构的制作方法，其特征在于，所述第一外延结构为缓冲层，所述掺杂元素位于缓冲层中；第二外延结构至少包括依次层叠设置的沟道层以及势垒层。
  3. 如权利要求1所述的半导体结构的制作方法，其特征在于，所述第一外延结构包括依次层叠设置的缓冲层、第一N型半导体层、第二N型半导体层以及P型半导体层，所述掺杂元素位于P型半导体层中；第二外延结构至少包括第三N型半导体层。
  4. 如权利要求1所述的半导体结构的制作方法，其特征在于，所述第一外延结构至少包括依次层叠设置的缓冲层、第一P型半导体层，所述掺杂元素位于P型半导体层中；第二外延结构至少包括依次层叠设置的N型半导体层和第二P型半导体层。
  5. 如权利要求3所述的半导体结构的制作方法，其特征在于，所述第一N型半导体层为N型重掺杂GaN层；所述第二N型半导体层为N型轻掺杂GaN层；所述第三N型半导体层为N型重掺杂GaN层。
  6. 如权利要求4所述的半导体结构的制作方法，其特征在于，所述第一P型半导体层为P型GaN层；所述N型半导体层为N型GaN层；所述第二P型半导体层为P型GaN层。
  7. 如权利要求1所述的半导体结构的制作方法，其特征在于，所述牺牲层的材料包括InN、InGaN、InAlN、InAlGaN、GaN中的一种或多种组合。
  8. 如权利要求1所述的半导体结构的制作方法，其特征在于，所述牺牲层的厚度可以是1nm–1um。
  9. 如权利要求1所述的半导体结构的制作方法，其特征在于，所述第一外延结构与牺牲层之间还包括保护层。
  10. 如权利要求9所述的半导体结构的制作方法，其特征在于， 所述保护层的材料包括AlN、AlInGaN、AlGaN中的一种或多种组合。
  11. 如权利要求1所述的半导体结构的制作方法，其特征在于，所述第一外延结构中的掺杂元素为铁或镁；所述掺杂元素的浓度可以恒定，也可以随厚度变化。
  12. 如权利要求1所述的半导体结构的制作方法，其特征在于，所述预设值为2×10 18个原子/cm 3量级以下。
  13. 如权利要求1所述的半导体结构的制作方法，其特征在于，步骤S1、S2、S3以及S4在同一个反应腔内依次完成。
  14. 如权利要求1所述的半导体结构的制作方法，其特征在于，在步骤S3中，反应腔内的温度高于400摄氏度，使用气体对所述牺牲层进行刻蚀。
  15. 如权利要求14所述的半导体结构的制作方法，其特征在于，所述气体可以为氢气、氨气、氯化氢、氯气中的一种或多种组合。
  16. 如权利要求1所述的半导体结构的制作方法，其特征在于，在步骤S3中，所述牺牲层，被完全刻蚀或部分刻蚀。
  17. 如权利要求1所述的半导体结构的制作方法，其特征在于，所述衬底可以为Si、SiC、GaN、AlN、蓝宝石。
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