WO2021111590A1

WO2021111590A1 - Laminate, method for producing patterned substrate, electronic device and package device

Info

Publication number: WO2021111590A1
Application number: PCT/JP2019/047637
Authority: WO
Inventors: ベジ佐々木
Original assignee: ベジ佐々木
Priority date: 2019-12-05
Filing date: 2019-12-05
Publication date: 2021-06-10
Also published as: JPWO2021111590A1; JP2025038061A

Abstract

A laminate 100 according to the present invention comprises an insulating layer 10, a conductor layer 30 that is provided on the insulating layer 10, and an etching delay layer 20 that is provided on one surface and/or the other surface of the conductor layer 30. The conductor layer 30 and the etching delay layer 20 are not patterned.

Description

Laminated board, patterning substrate manufacturing method, electronic equipment and mounting equipment

The present invention relates to a laminated board having an insulating layer and a conductor layer, a method for manufacturing the laminated board, an electronic device, and a mounting device.

Conventionally, a laminated board in which a conductor layer is provided as an insulating layer has been known. As an example, Patent Document 1 proposes a copper-clad laminate having an insulating layer made of polyimide and a first copper foil layer laminated on one side of the insulating layer made of polyimide.

Japanese Unexamined Patent Publication No. 2016-60138

When etching a conductor layer in a laminate including a copper-clad laminate, the etching rate of the conductor layer located on the upper side is faster than the etching rate of the conductor layer located on the lower side, and the upper side is relative to the lower side. Short patterning tends to form. If the upper side is shorter than the lower side in the shape of the cross section of the conductor layer, there may be a problem that the designed current amount does not flow in the conductor layer.

INDUSTRIAL APPLICABILITY According to the present invention, in the shape of the cross section of the conductor layer, a laminated board and a laminated board capable of reducing the amount that the length of one side opposite to the insulating layer becomes shorter than the length of the other side of the insulating layer side can be reduced. Methods, electronic devices and mounting devices are provided.

[Concept 1]
The laminated board according to the present invention
Insulation layer and
The conductor layer provided in the insulating layer and
Etching delay layers provided on one surface, the other surface, or both sides of the one surface and the other surface of the conductor layer,
With
The conductor layer and the etching delay layer may not be patterned.

[Concept 2]
In the laminated board according to the concept 1,
The etching delay layer may be provided on substantially the entire surface of one surface of the conductor layer.

[Concept 3]
In a laminated board according to either concept 1 or 2.
An oxide layer may be provided between the insulating layer and the conductor layer.

[Concept 4]
In a laminated board according to any one of the concepts 1 to 3,
The conductor layer is a layer containing copper as a main component.
The etching delay layer may be a layer containing an alloy containing nickel, titanium, zinc, silver, tin, iron, gold, aluminum, stainless steel, tungsten, platinum, chromium, lead or cobalt as a main component.

[Concept 5]
In a laminated board according to any one of the concepts 1 to 4,
The thickness of the etching delay layer may be 1/2 to 1/1000 of the thickness of the conductor layer.

[Concept 6]
In the laminated board according to the concept 5,
The thickness of the etching delay layer may be 1/2 to 1/10 of the thickness of the conductor layer.

[Concept 7]
In a laminated board according to any one of the concepts 1 to 6,
The etching delay layer may be provided on both sides of the conductor layer.

[Concept 8]
In a laminated board according to any one of the concepts 1 to 7,
The conductor layer may have a thickness of 100 μm or more.

[Concept 9]
In a laminated board according to any one of the concepts 1 to 8,
Oxidized layers may be provided on both one side and the other side of the conductor layer.

[Concept 10]
The method for manufacturing a patterning substrate according to the present invention is
A step of preparing a laminated plate having an insulating layer, a conductor layer provided on the insulating layer, and etching delay layers provided on one surface or both one side and the other side of the conductor layer.
A step of patterning the conductor layer and the etching delay layer by etching the substrate to be processed, and
May be provided.

[Concept 11]
The electronic device according to the present invention
The laminated board according to any one of the concepts 1 to 9 and
Electronic components provided on the laminated board and
May be provided.

[Concept 12]
The mounting device according to the present invention is
The electronic device according to the concept 11 may be provided.

In the non-patterned laminated board, when the aspect in which the etching delay layer is provided on one surface of the conductor layer is adopted, the length of one side opposite to the insulating layer in the shape of the cross section of the conductor layer (on the upper side). The amount of length) shortened with respect to the length (length of the lower side) of the other side of the insulating layer side can be reduced, and the cross-sectional shape of the conductor layer can be made closer to a rectangular shape or a square shape.

FIG. 1 is a side sectional view of a laminated board according to an example of the first embodiment of the present invention. FIG. 2A is a side sectional view of a laminated board according to another example of the first embodiment of the present invention, and FIG. 2B is still another example of the first embodiment of the present invention. It is a side sectional view of the laminated board by. FIG. 3 is a side sectional view showing a mode in which a part of the conductor layer before patterning is pushed into the insulating layer. FIG. 4 is a side sectional view showing a mode in which a part of the conductor layer after patterning is pushed into the insulating layer. FIG. 5 is a side sectional view showing a mode in which all the side surfaces of the conductor layer before patterning are pushed into the insulating layer. FIG. 6 is a side sectional view showing a mode in which all the side surfaces of the conductor layer after patterning are pushed into the insulating layer. FIG. 7 is a side sectional view showing a mode in which a part of the conductor layer after patterning is pushed into the insulating layer in a mode having a redox layer. FIG. 8 is a side sectional view showing a mode in which the entire side surface of the conductor layer after patterning is pushed into the insulating layer in a mode having a redox layer. FIG. 9A is a side sectional view showing a laminated plate having an etching delay layer, and FIG. 9B is a side showing an aspect in which the etching delay layer is patterned after FIG. 9A. 9 (c) is a cross-sectional view showing a mode in which the conductor layer is patterned after FIG. 9 (b), and FIG. 9 (d) is after FIG. 9 (c). 9A is a side sectional view showing an aspect in which the etching delay layer is removed, and FIG. 9E is a lateral sectional view showing an aspect in which the conductor layer is pushed into the insulating layer after FIG. 9D. is there. FIG. 10 (a) is a side sectional view showing an example of an embodiment for forming a redox layer, and FIG. 10 (b) is a lateral sectional view showing an embodiment having a first redox layer and a second reduced dioxide layer. It is a figure. FIG. 11 is a side sectional view showing an example in which an etching process is performed after a part of the conductor layer is pushed in. FIG. 12A is a side sectional view for explaining an embodiment in which etching is performed when the etching delay layer is not provided, and FIG. 12B is an etching when the etching delay layer is provided. It is a side sectional view for demonstrating the aspect which performed. FIG. 13A is a side sectional view showing a mode in which the conductor layer is pushed into the insulating layer after the etching delay layer is removed, and FIG. 13B is a drawing corresponding to FIG. 13A. FIG. 13 (c) is a side sectional view showing an embodiment in which the oxidation-reduction layer is provided on the lower surface and the side surface of the conductor layer. FIG. 13 (c) is a drawing corresponding to FIG. It is a side sectional view which showed the mode provided on the lower surface, the side surface and the upper surface of a layer. FIG. 14 is a side sectional view showing an aspect in which a redox layer having an uneven shape is provided. FIG. 15A is a side sectional view of a laminated board according to an example of the second embodiment of the present invention. FIG. 15B (a) is a side sectional view of a laminated board according to another example of the second embodiment of the present invention, and FIG. 15B (b) is still another example of the second embodiment of the present invention. It is a side sectional view of the laminated board by. FIG. 16A is a side sectional view of a laminated plate according to an example of the third embodiment of the present invention, and FIG. 16B is a redox layer provided in the third embodiment of the present invention. 16 (c) is a side sectional view of the laminated plate showing another example in which the redox layer is provided, and FIG. 16 (c) is a side sectional view of the laminated plate showing another example. Is a side sectional view of a laminated plate according to still another example provided with a redox layer. FIG. 17 is a diagram showing an example of an electronic device that can be provided by the present invention. FIG. 18 is a side sectional view showing an example of a multilayer substrate that can be adopted in the present invention. FIG. 19 is a side sectional view showing an example of a double-sided plate that can be adopted in the present invention.

First Embodiment << Configuration >>
As shown in FIG. 1, the laminated board 100 according to the present embodiment is formed on one surface (upper surface in FIG. 1) of the insulating layer 10, the conductor layer 30 provided on the insulating layer 10, and the conductor layer 30. It may have an etching delay layer 20 provided. The conductor layer 30 and the etching delay layer 20 may not be patterned. That is, it may be the laminated board 100 before being etched or the like. The laminated board 100 provided in the present embodiment may be a printed circuit board, a metal-clad laminated board such as a copper-clad laminated board (CCL: Copper Clad Laminate), or the like. The conductor layer 30 may be a double-sided plate provided on both sides of the insulating layer 10 (see FIG. 19).

The conductor layer 30 may be provided on substantially the entire surface of one surface of the insulating layer 10, and the etching delay layer 20 may be provided on substantially the entire surface of one surface of the conductor layer 30. The fact that the conductor layer 30 is provided on substantially the entire surface of one surface of the insulating layer 10 means that the conductor layer 30 covers an area of 95% or more of the insulating layer 10 in a plan view from one side (upper side in FIG. 1). It means that it covers, and it means that the area of the insulating layer 10 that is not covered by the conductor layer 30 is 5% or less. Similarly, the fact that the etching delay layer 20 is provided on substantially the entire surface of one surface of the conductor layer 30 means that the etching delay layer 20 is 95 of the conductor layer 30 in a plan view from one side (upper side in FIG. 1). It means that it covers an area of% or more, and means that the conductor layer 30 that is not covered by the etching delay layer 20 has an area of 5% or less.

The conductor layer 30 may be a metal foil, metal plating, a rolled plate, or the like. The conductor layer 30 may be a copper layer made of copper. The conductor layer 30 may be other than copper, and may be, for example, gold, silver, aluminum, or an alloy containing these metals. The conductor layer 30 may be a metal containing copper as a main component. In the present application, the term "main component" means that the mixture is contained in an amount exceeding 50% by weight. The thickness of the conductor layer 30 may be 100 μm or more, or 150 μm or more. The thickness of the conductor layer 30 may be 500 μm or less, or 300 μm or less.

The etching delay layer 20 may be a nickel layer made of nickel. The etching delay layer 20 may be made of a material that delays etching and may be other than nickel, but it is advantageous to use nickel from the viewpoint of versatility and cost. The etching delay layer 20 may be a material containing nickel as a main component. Further, the etching delay layer 20 may be a material containing titanium, zinc, silver, tin, iron, gold, aluminum, stainless steel, tungsten or platinum, or an alloy containing any two or more of them as a main component. ..

It is beneficial that the thickness of the etching delay layer 20 is in the range of 1/2 to 1/1000 of the thickness of the conductor layer 30. As a general rule, when the thickness of the conductor layer 30 is increased, the ratio of the thickness of the etching delay layer 20 is relatively small.

The etching delay layer 20 may be removed after the etching process is completed. In this case, the etching process is performed, and the etching delay layer 20 is not provided on the laminated plate 100 having the patterned conductor layer 30.

The insulating layer 10 may be made of, for example, resin, glass, ceramic or the like. The insulating layer 10 may be a mixture of two or more kinds of insulating substances. For example, the insulating layer 10 may contain a fibrous or granular insulator. The insulating layer 10 may be a semi-cured sheet (prepreg) in which a base material such as paper or glass fiber is impregnated with a resin and dried. The insulating layer 10 may contain a heat conductive substance such as silicon nitride. The semi-cured state is a state in which it is not completely solidified and is deformable.

As the material of the insulating layer 10, a heat-curable resin, an ultraviolet curable resin, or the like may be used. If there is a certain degree of heat resistance, a thermoplastic resin may be used as the material of the insulating layer 10. As the thermosetting resin, a polyimide resin, an epoxy resin, a phenol resin, a cyanate resin or the like may be used. The thermoplastic resin may have a thermal deformation temperature of 50 degrees or higher.

A redox layer 40 may be provided between the insulating layer 10 and the conductor layer 30. The redox layer 40 may have an uneven shape on the surface on the insulating layer 10 side (see FIG. 14).

The redox layer 40 may contain an oxide of a material constituting the conductor layer 30. Further, the redox layer 40 may have an uneven shape in whole or in part. The uneven shape may have a substantially triangular cross section, a substantially rectangular shape, a substantially semicircular shape, or a substantially circular shape, and the fibers are entangled with each other. Such a mesh shape may be formed, and the uneven shape may be configured as various shapes. In the present embodiment, the "substantially XX shape" means that the shape is approximately XX when viewed by a person skilled in the art.

As shown in FIG. 2A, the redox layer 40 may be provided between the conductor layer 30 and the etching delay layer 20. The redox layer 40 may be provided on one surface and the other surface of the conductor layer 30 (see FIG. 2A), or on both sides of one surface and the other surface (see FIG. 2B).

The redox layer 40 may contain copper oxide as a main component. Copper oxide may include cuprous oxide, cupric oxide, or both cuprous oxide and cupric oxide. Here, the "main component" means that the content is contained in an amount exceeding 50% by weight.

As shown in FIG. 10B, the redox layer 40 has a first redox layer 41 and a second redox layer 42 provided on the insulating layer 10 side of the first redox layer 41. May be good. When the redox layer 40 is composed of copper oxide, for example, the first redox layer 41 _{contains first copper oxide (Cu 2} O) and the second redox layer 42 contains second copper oxide (Cu O). May be contained. Further, the primary redox layer 41 may be made of cuprous oxide (Cu ₂ O), and the reduced carbon dioxide layer 42 may be made of cupric oxide (Cu O).

The redox layer 40 may be composed of only copper oxide. In other words. All of the redox layer 40 may be composed of copper oxide. In this case, the redox layer 40 is composed of an oxidized layer (oxide layer). The copper oxide may be cuprous oxide (Cu ₂ O), cupric oxide (Cu O), or both cuprous oxide and cupric oxide. Since the cuprous oxide becomes the cupric oxide as the oxidation reaction proceeds, the treatment time with the treatment liquid 120 (see FIG. 10A) placed in the container 110 is adjusted to oxidize the copper oxide with the cuprous oxide. The mixing ratio of the second copper may be adjusted.

The insulating layer 10 may be in a semi-cured state. A part or all of the patterned conductor layer 30 may be embedded in the semi-cured insulating layer 10 by pushing it into the insulating layer 10 (see FIGS. 3 to 6). When the conductor layer 30 is embedded in the insulating layer 10, a pressing force may be applied to the conductor layer 30, but the present invention is not limited to this mode, and the conductor layer 30 is embedded in the insulating layer 10 by its own weight. It may be. When the conductor layer 30 is embedded in the insulating layer 10, the patterned conductor layer 30 may be embedded in the insulating layer 10 (see FIGS. 4 and 6), or the conductor before patterning. The layer 30 may be embedded in the insulating layer 10 (see FIGS. 3 and 5). Further, as long as the etching delay layer 20 is removed, the entire conductor layer 30 including one surface (upper surface) may be completely embedded inside the insulating layer 10 (FIGS. 13 (a)-(FIG. 13 (a)- c) See).

In FIG. 13B, the redox layer 40 is provided over the entire lower surface and side surface of the conductor layer 30, but the redox layer 40 is not provided on the upper surface where the etching delay layer 20 is provided. It is shown. This embodiment can be realized by performing a redox reaction or an oxidation reaction of the conductor layer 30 after performing the etching treatment, and then removing the etching delay layer 20. On the other hand, when the redox reaction or the oxidation reaction of the conductor layer 30 is performed after the etching treatment is performed to remove the etching delay layer 20, the redox layer 40 is formed over the entire surface of the conductor layer 30. (See FIG. 13 (c)).

After embedding a part or all of the patterned conductor layer 30 in the semi-cured insulating layer 10 by pushing it in, the insulating layer 10 may be cured by applying heat or irradiating it with ultraviolet rays. When a thermoplastic resin is used as the insulating layer 10, the insulating layer 10 may be cured by allowing it to cool or cool.

Further, in the embodiment in which the redox layer 40 is provided, the redox layer 40 is provided in the region that has entered the insulating layer 10, and the redox layer 40 is not provided in the region (side surface) exposed from the insulating layer 10. Good (see Figure 7). Such an embodiment can be generated by removing the region of the redox layer 40 generated on the entire side surface of the conductor layer 30 that protrudes from the insulating layer 10. The redox layer 40 may be provided on the entire side surface of the conductor layer 30, and the entire conductor layer 30 and the redox layer 40 may be provided in the insulating layer 10 (see FIG. 8).

≪Manufacturing process≫
An example of the processing process using the laminated board according to the present embodiment will be described with reference to FIG.

A laminated plate 100 having an insulating layer 10, a conductor layer 30 provided on the insulating layer 10, and an etching delay layer 20 provided on one surface of the conductor layer 30 is prepared (see FIG. 9A).

Next, the conductor layer 30 and the etching delay layer 20 are patterned by etching the laminated plate 100 in a state of being appropriately masked (see FIGS. 9 (b) and 9 (c)). A liquid having a component different from that of the etching solution (first etching solution) for patterning the etching delay layer 20 and the etching solution (second etching solution) for patterning the conductor layer 30 may be used.

As an example, the etching delay layer 20 is patterned with the first etching solution in a state of being appropriately masked (see FIG. 9B). After that, the conductor layer 30 is patterned with the second etching solution in a state of being appropriately masked (see FIG. 9C).

After the etching is completed, the etching delay layer 20 is removed with a chemical solution (a removing solution for removing the etching delay layer 20 or a second etching solution) (see FIG. 9D).

After that, a part or all of the patterned conductor layer 30 is pushed into the semi-cured insulating layer 10 (see FIG. 9E).

Next, the insulating layer 10 is cured by allowing the semi-cured insulating layer 10 to cool or cool. As a result, a laminated plate 100 in which a part of the conductor layer 30 is embedded in the insulating layer 10 is generated.

In the above description, the conductor layer 30 is pushed into the semi-cured insulating layer 10 after the etching delay layer 20 is removed, but the present invention is not limited to this. For example, the etching delay layer 20 may be removed after the conductor layer 30 is pushed into the semi-cured insulating layer 10. Alternatively, the conductor layer 30 may be pushed into the semi-cured insulating layer 10 and then etched, then the etching delay layer 20 may be removed, and then the insulating layer 10 may be cured. Even in this case, by removing a part of the conductor layer 30 by etching, the semi-cured insulating layer 10 moves so as to match the height, and the conductor layer 30 as shown in FIG. 9E is provided. It is also possible to obtain an insulating layer 10 having the same height in the uncovered region. However, the present invention is not limited to this aspect, and by curing the semi-cured insulating layer 10 early, as shown in FIG. 11, laminated plates 100 having different heights of the insulating layer 10 are generated. May be good. In the aspect shown in FIG. 11, the insulating layer 10 has a concave shape at the place where the conductor layer 30 was present.

"effect"
Next, the effects of the present embodiment having the above-described configuration, which have not been described yet, will be mainly described.

When the etching delay layer 20 is provided on one surface of the conductor layer 30 and the laminated plate in which the conductor layer 30 and the etching delay layer 20 are not patterned is adopted, the shape of the cross section of the conductor layer 30 is rectangular or square. It can be made closer to the shape. When the etching process is performed, the conductor layer 30 located on the upper side is etched more than the conductor layer 30 located on the lower side, and a pattern in which the upper side is shorter than the lower side tends to be formed (FIG. 12). (A). In this regard, by providing the etching delay layer 20 on one surface of the conductor layer 30, the etching rate of the conductor layer 30 located on the upper side can be slowed down, and as a result, the shape of the conductor layer 30 to be patterned can be reduced. It can be made closer to a rectangular shape or a square shape (see FIG. 12 (b)).

In this embodiment, since the etching process is focused on in this way, it is an important point that the conductor layer 30 and the etching delay layer 20 are not patterned. Generally, it is attempted to reduce the cost by increasing the etching rate and shortening the processing time, but in the present embodiment, the conductor layer 30 is processed in order to make the conductor layer 30 close to a rectangular shape or a square shape. It accepts the disadvantage of slowing down the time, and is based on the completely opposite idea to those skilled in the art.

According to this aspect, it is advantageous in that a current amount close to the design value can be passed by bringing the conductor layer 30 close to a rectangular shape or a square shape. In other words, when designing, the conductor pattern such as copper is calculated on the assumption that the cross section is rectangular or square, but in reality, the cross section of the conductor pattern such as copper is trapezoidal. , A current amount different from the amount used in the design value will flow. In this respect, it is advantageous in that this point can be improved by adopting the aspect of the present embodiment.

The thicker the conductor layer 30, the stronger the tendency for the upper side in the cross section of the conductor layer 30 to be shorter than the lower side. Therefore, it is beneficial to adopt the embodiment of the present embodiment. In particular, in the conductor layer 30 having a thickness of 100 μm or more (typically, a thick copper type conductor layer), the difference in shape of the conductor layer 30 between the case where the etching delay layer 20 is provided and the case where the etching delay layer 20 is not provided. Becomes prominent. Therefore, it is beneficial to adopt this embodiment when adopting the conductor layer 30 having a thickness of 100 μm or more.

By adjusting the thickness of the etching delay layer 20, the etching rate on one side (upper side) can be adjusted. In particular, when the thickness of the etching delay layer 20 is 1/10 or more of the thickness of the conductor layer 30, it is useful when adjusting the etching rate, and when it is 1/5 or more, it is even more useful.

Second Embodiment Next, a second embodiment of the present invention will be described.

As shown in FIG. 15A, in the present embodiment, the etching delay layer 20 is provided on both one surface and the other surface of the conductor layer 30. Other configurations are the same as those in the first embodiment, and any aspect described in the first embodiment can be adopted. The members described in the first embodiment will be described using the same reference numerals. In the present embodiment, the etching delay layer 20 provided on one surface side (upper side) of the conductor layer 30 is also referred to as a first etching delay layer 20a, and is provided on the other surface side (lower side) of the conductor layer 30. The etching delay layer 20 is also referred to as a second etching delay layer 20b.

By providing the second etching delay layer 20b on the other side, the height position of the bottom surface of the conductor layer 30 can be increased. As a result, the conductor layer 30 is not positioned at a position where the etching solution stays (the etching solution does not circulate) and the etching effect is lowered, and the conductor layer 30 is located at a position where the flow of the etching solution is smooth and the etching effect can be expected. The lower end of the can be positioned. Therefore, it is possible to prevent the etching rate of the conductor layer 30 located on the insulating layer 10 side (lower side) from becoming slow, and the conductor layer 30 located between the first etching delay layer 20a and the second etching delay layer 20b. The cross-sectional shape of is close to a rectangular shape or a square shape.

From the viewpoint of increasing the height position of the bottom surface of the conductor layer 30, it is beneficial that the thickness of the second etching delay layer 20b is 1/5 or more of the thickness of the conductor layer 30. By adopting the second etching delay layer 20b having such a thickness, it is possible to prevent the conductor layer 30 from being located on the lower side where the etching process is difficult to proceed.

The thickness of the first etching delay layer 20a and the thickness of the second etching delay layer 20b may be different, and even if the thickness of the second etching delay layer 20b is twice or more the thickness of the first etching delay layer 20a. Good. For example, the thickness of the first etching delay layer 20a may be 1/10 or more of the thickness of the conductor layer 30, and the thickness of the second etching delay layer 20b may be 1/5 or more of the thickness of the conductor layer 30.

The first etching delay layer 20a and the second etching delay layer 20b may be made of the same material (for example, nickel), but each may be made of a different material.

When the insulating layer 10 is in a semi-cured state, the conductor layer 30 is pushed so that a general part (80% or more) of the second etching delay layer 20b is embedded in the insulating layer 10. May be good. Further, by pushing the conductor layer 30, all of the second etching delay layer 20b may be embedded in the insulating layer 10. Such indentation may be performed after patterning has been performed.

As shown in FIGS. 15B (a) and 15B, the redox layer (oxide layer) 40 may be provided between the conductor layer 30 and the etching delay layer 20. The redox layer 40 may be provided on one side and the other side of the conductor layer 30 (see FIG. 15B (a)), or on both sides of one side and the other side (see FIG. 15B (b)).

Third Embodiment Next, a third embodiment of the present invention will be described.

As shown in FIG. 16A, in the present embodiment, the etching delay layer 20 (second etching delay layer 20b) is provided on the other surface of the conductor layer 30. Other configurations are the same as those of the first embodiment, and any aspect described in the first embodiment and the second embodiment can be adopted. The members described in the first embodiment or the second embodiment will be described with reference to the same reference numerals.

Unlike the first embodiment and the second embodiment, in this embodiment, the etching delay layer 20 (first etching delay layer 20a) is not provided on one side, and the etching delay is delayed only on the other side. A layer 20 is provided. Even in such an embodiment, the cross-sectional shape of the conductor layer 30 can be made close to a rectangular shape or a square shape for the reason described in the second embodiment.

As shown in FIG. 16B, the redox layer (oxide layer) 40 may be provided between the conductor layer 30 and the etching delay layer 20. The redox layer 40 is provided on one side of the conductor layer 30 (see FIG. 16C), the other side (see FIG. 16C), or both sides of one side and the other side (see FIG. 16D). You may.

≪Multilayer board≫
A multilayer substrate in which a plurality of laminated plates as shown in the first to third embodiments are laminated may be adopted. An etching delay layer 20 and / or a redox layer 40 may be provided for each of the conductor layers 30.

FIG. 18 shows a mode in which a plurality of laminated plates shown in FIG. 2 (a) are laminated, but the present invention is not limited to this, and FIGS. 1, 2 (b), 15A, 15B (a), and FIG. A mode in which a plurality of laminated plates shown in any of FIGS. 15B (b), 16 (a), 16 (b), 16 (c) and 16 (d) are laminated may be adopted. 1, FIG. 2 (a), FIG. 2 (b), FIG. 15A, FIG. 15B (a), FIG. 15B (b), FIG. 16 (a), FIG. 16 (b), FIG. 16 (c) and FIG. A multilayer substrate in which a plurality of laminates having any two or more aspects of (d) are laminated may be adopted. A mode in which the configuration of the laminated plate located on the outermost surface (re-upper surface) and the configuration of the other laminated plate (laminated plate located inside) are different may be adopted.

The description of each embodiment and the disclosure of the drawings described above are merely examples for explaining the invention described in the claims, and the description of the above-described embodiments or the disclosure of the drawings is included in the claims. The described invention is not limited.

An electronic component 210 such as a semiconductor element, a capacitor, or a resistor is placed on the laminated plate 100 in the above-described embodiment, and the electronic component is sealed with a sealing resin 220 to provide an electronic device 200 (FIG. 17). reference). Such electronic devices may be incorporated into any mounting device such as automobiles, airplanes, ships, helicopters, personal computers, home appliances and the like.

10 Insulation layer 20 Etching delay layer 30 Conductor layer 100 Laminated plate

Claims

Insulation layer and
The conductor layer provided in the insulating layer and
Etching delay layers provided on one surface, the other surface, or both sides of the one surface and the other surface of the conductor layer,
With
A laminated board in which the conductor layer and the etching delay layer are not patterned.
The laminated plate according to claim 1, wherein the etching delay layer is provided on substantially the entire surface of one surface of the conductor layer.
The laminated plate according to claim 1 or 2, wherein an oxide layer is provided between the insulating layer and the conductor layer.
The conductor layer is a layer containing copper as a main component.
Any of claims 1 to 3, wherein the etching delay layer is a layer containing an alloy containing nickel, titanium, zinc, silver, tin, iron, gold, aluminum, stainless steel, tungsten, platinum, chromium, lead or cobalt as a main component. The laminated board according to item 1.
The laminated plate according to any one of claims 1 to 4, wherein the thickness of the etching delay layer is 1/2 to 1/1000 of the thickness of the conductor layer.
The laminated plate according to claim 5, wherein the thickness of the etching delay layer is 1/2 to 1/10 of the thickness of the conductor layer.
The laminated plate according to any one of claims 1 to 6, wherein the etching delay layer is provided on both sides of the conductor layer.
The laminated plate according to any one of claims 1 to 7, wherein the conductor layer has a thickness of 100 μm or more.
The laminated plate according to any one of claims 1 to 8, wherein an oxide layer is provided on both one side and the other side of the conductor layer.
The laminated plate according to any one of claims 1 to 9, wherein the insulating layer is in a semi-cured state.
A step of preparing a laminated plate having an insulating layer, a conductor layer provided on the insulating layer, and etching delay layers provided on one surface or both one side and the other side of the conductor layer.
A step of patterning the conductor layer and the etching delay layer by etching the substrate to be processed, and
A method for manufacturing a patterning substrate comprising.
The laminated board according to any one of claims 1 to 10 and
Electronic components provided on the laminated board and
Electronic device equipped with.
A mounting device including the electronic device according to claim 12.