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WO2021072859A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021072859A1
WO2021072859A1 PCT/CN2019/117566 CN2019117566W WO2021072859A1 WO 2021072859 A1 WO2021072859 A1 WO 2021072859A1 CN 2019117566 W CN2019117566 W CN 2019117566W WO 2021072859 A1 WO2021072859 A1 WO 2021072859A1
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WIPO (PCT)
Prior art keywords
layer
opening
pixel electrode
forming
film transistor
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Application number
PCT/CN2019/117566
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English (en)
French (fr)
Inventor
肖军城
艾飞
罗成志
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武汉华星光电技术有限公司
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Publication of WO2021072859A1 publication Critical patent/WO2021072859A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display device.
  • TFT-LCD In recent years, in TFT-LCD, the development of projects for power saving, high definition, and improvement of color reproducibility is being promoted. Among them, improving the penetration performance, improving the brightness of TFT-LCD, and reducing power loss are the difficulties that all panel manufacturers in the world are conquering.
  • the transmittance of a TFT-LCD panel refers to the ratio of the light intensity before and after the backlight passes through the TFT-LCD panel. Under normal circumstances, the light transmittance of TFT-LCD is only 3-10%, which means that more than 90% of the light cannot be used.
  • TFT-LCD array substrate in addition to the metal traces, there are also multilayer films composed of silicon oxide, silicon nitride, indium tin oxide, and materials used for the flat layer that have a greater impact on the transmittance. structure.
  • the refractive index and extinction coefficient of each film will affect the overall transmittance of the multilayer film. Therefore, the transmittance of the multilayer film can be improved by adjusting the refractive index, extinction coefficient, film structure and other parameters of each film.
  • the bottom buffer layer of the film structure of the array substrate commonly used in the industry is composed of silicon nitride and silicon oxide
  • the inter-insulating layer is composed of silicon nitride and silicon oxide
  • the passivation layer 13' (PV) is composed of silicon nitride.
  • the refractive index of silicon nitride is greater than that of silicon oxide. Therefore, light will be reflected when passing through the interface between silicon nitride and silicon oxide, resulting in a decrease in transmittance.
  • silicon oxide can be used instead of silicon nitride.
  • the silicon nitride of the passivation layer 13' PV
  • a part of the silicon nitride is exposed in the opening 3'to contact the air, that is, the silicon nitride at the opening 3'is in contact with the air;
  • the silicon nitride is in contact with the pixel electrode 14' made of indium tin oxide material on the top surface thereof.
  • the transmittance of silicon oxide in contact with the air is greatly improved due to the small difference in refractive index between silicon oxide and air, but it is The transmittance at the contact point of the pixel electrode 14' decreases due to the large refractive index difference between the silicon oxide and the pixel electrode. The final result is that the overall transmittance of the array substrate is not significantly improved.
  • the present invention provides an array substrate, a preparation method thereof, and a display device, so as to improve the light transmittance of the entire array substrate.
  • the present invention provides an array substrate including a thin film transistor structure layer; and a common electrode layer provided on the thin film transistor structure layer; a first opening is provided on the common electrode layer A passivation layer, covering the common electrode layer and filling the first opening; a pixel electrode layer, covering the passivation layer and passing through the passivation layer and the first opening Connected to the thin film transistor structure layer; an opening extending from the pixel electrode layer to the surface of the common electrode layer; a first filling layer covering the common electrode layer and the pixel electrode layer and filling them The opening; the light transmittance of the passivation layer is less than the light transmittance of the first filling layer.
  • the thin film transistor structure layer includes a substrate; an active layer provided on the substrate; a gate insulating layer covering the substrate and covering the active layer; a gate layer , Arranged on the gate insulating layer; an interlayer dielectric layer, covering the gate insulating layer and covering the gate layer; a second opening, extending from the interlayer dielectric layer to the The surface of the source layer; the source and drain are arranged on the interlayer dielectric layer and are respectively connected to the active layer through a second opening; the planarization layer is arranged on the interlayer dielectric layer and Covering the source and the drain; the pixel electrode layer is connected to the drain.
  • the source electrode and the drain electrode cover the wall of the second opening;
  • the thin film transistor structure layer further includes a filling layer, which is filled in the second opening And cover the surface of the source electrode and the drain electrode;
  • the material of the filling layer is silicon oxide or silicon nitride.
  • the thin film transistor structure layer further includes a metal light-shielding layer, which is provided on a side of the substrate away from the active layer and corresponding to the region where the active layer is located.
  • the material used for the substrate is silicon oxide and/or silicon nitride; the material used for the interlayer dielectric layer is silicon oxide and/or silicon nitride; the pixel electrode layer and the common
  • the materials used for the electrode layer are all indium tin oxide materials.
  • the material used for the passivation layer is silicon nitride material, and all the materials of the first filling layer are silicon oxide materials
  • the present invention also provides a preparation method for preparing the array substrate, characterized in that it comprises the following steps: preparing the thin film transistor structure layer; forming the common electrode layer on the thin film transistor structure layer; Forming the first opening that penetrates the common electrode layer; forming the passivation layer in the first opening and the surface of the common electrode layer; forming the passivation layer, the first Opening and extending to the third opening in the thin film transistor structure layer; forming the pixel electrode layer in the third opening and on the passivation layer; coating photoresist material on the pixel electrode A photoresist layer is formed on the layer, and the photoresist layer is exposed and developed to form a pixel electrode pattern; according to the formed pixel electrode pattern, the pixel electrode layer is wet-etched to form a pixel electrode and a pixel electrode between the pixel electrodes.
  • a gap in the first gap, dry etching the passivation layer to form a second gap, the first gap and the second gap form the opening; remove the photoresist layer; deposit a filling material The opening and the surfaces of the common electrode layer and the pixel electrode layer form the first filling layer.
  • the step of preparing the thin film transistor structure layer includes providing a substrate; forming an active layer on the substrate; forming a gate insulating layer on the substrate and covering the active layer. Layer; forming a gate layer on the gate insulating layer; forming an interlayer dielectric layer on the gate insulating layer and covering the gate layer; forming an interlayer dielectric layer extending from the interlayer dielectric layer to the active A second opening on the surface of the layer; forming source and drain electrodes on the interlayer dielectric layer and the active layer on the wall of the second opening and the bottom of the second opening On; depositing silicon oxide or silicon nitride material in the second opening to form a filling layer; forming a planarization layer on the interlayer dielectric layer and covering the source, the drain and the filling layer In the step of forming the third opening, the third opening extends to the surface of the drain.
  • a side of the substrate away from the active layer and corresponding to the area where the active layer is provided has a metal light-shielding layer.
  • the present invention also provides a display device, including the array substrate.
  • the silicon nitride in the passivation layer in contact with the air is replaced with silicon oxide to reduce interface reflection and improve the transmittance at the contact with the air; and when in contact with the pixel electrode layer
  • the first filling layer is added to the upper part of the pixel electrode layer to reduce the interface reflection between the pixel electrode layer and the air, which greatly improves the light transmittance of the entire array substrate.
  • the preparation method of the array substrate is simple, easy to operate, and can effectively achieve the purpose of improving the overall transmittance of the array substrate.
  • FIG. 1 is a structural diagram of an array substrate in the prior art, which mainly reflects the positional relationship of the passivation layer, the opening and the pixel electrode, and a part of the passivation layer is exposed in the opening to contact the air, and part is arranged under the pixel electrode to contact the pixel electrode.
  • FIG. 2 is a structural diagram of an array substrate after forming a second opening according to an embodiment of the present invention.
  • FIG. 3 is a structural diagram of an array substrate after a planarization layer is formed according to an embodiment of the present invention.
  • FIG. 4 is a structural diagram of the array substrate after forming the first opening according to the embodiment of the present invention.
  • FIG. 5 is a structural diagram of an array substrate after forming a third opening according to an embodiment of the present invention.
  • FIG. 6 is a structural diagram of an array substrate for exposing and developing a photoresist layer to form pixel electrode patterns according to an embodiment of the present invention.
  • FIG. 7 is a structural diagram of the array substrate after forming the first notch according to the embodiment of the present invention.
  • FIG. 8 is a structural diagram of an array substrate after forming a second notch, that is, after forming an opening according to an embodiment of the present invention.
  • FIG. 9 is a structural diagram of an array substrate after forming a first filling layer according to an embodiment of the present invention.
  • FIG. 10 is a structure diagram of the device when a mask is used to shield the array substrate and the deposited silicon oxide material is in the opening and on the common electrode layer according to an embodiment of the present invention.
  • A is the curve of the transmittance of the array substrate where the passivation layer is in contact with air and the thickness of the first filling layer there.
  • B is the curve of the transmittance of the array substrate where the passivation layer is in contact with the pixel electrode layer and the thickness of the first filling layer there.
  • the array substrate 1 of the present invention includes a thin film transistor structure layer 11, a common electrode layer 12, a passivation layer 13, a pixel electrode layer 14, and a first filling layer 15.
  • the thin film transistor structure layer 11 includes a substrate 111, an active layer 112, a gate insulating layer 113, a gate layer 114, an interlayer dielectric layer 115, a source 116 and a drain 117, A planarization layer 119 and a filling layer 118.
  • the active layer 112 is disposed on the substrate 111;
  • the gate insulating layer 113 covers the substrate 111 and covers the active layer 112;
  • the gate layer 114 is disposed on the substrate 111.
  • the interlayer dielectric layer 115 covers the gate insulating layer 113 and covers the gate layer 114; the second opening 22 extends from the interlayer dielectric layer 115 To the surface of the active layer 112; the source electrode 116 and the drain electrode 117 are disposed on the interlayer dielectric layer 115 and are connected to the active layer 112 through a second opening 22; The chemical layer 119 is disposed on the interlayer dielectric layer 115 and covers the source electrode 116 and the drain electrode 117.
  • the thin film transistor structure layer 11 further includes a metal light-shielding layer 110, and the metal light-shielding layer 110 is disposed on a side of the substrate 111 away from the active layer 112 and corresponding to the area where the active layer 112 is located.
  • the material used for the substrate 111 is silicon oxide and/or silicon nitride; the material used for the interlayer dielectric layer 115 is silicon oxide and/or silicon nitride.
  • the common electrode layer 12 is disposed on the thin film transistor structure layer 11, and the common electrode layer 12 has a first opening 21 therein, and the first opening 21 corresponds to the drain electrode. 117.
  • the materials used for the common electrode layer 12 are all indium tin oxide materials.
  • the passivation layer 13 covers the common electrode layer 12 and fills the first opening 21, and the material of the passivation layer 13 is silicon nitride.
  • the pixel electrode layer 14 covers the passivation layer 13 and is connected to the thin film transistor structure layer 11 through the passivation layer 13 and the first opening 21. ⁇ 117 ⁇ Drain 117.
  • the pixel electrode layer 14 has an opening 3. As shown in FIGS. 7 to 8, the opening 3 extends from the pixel electrode layer 14 to the surface of the common electrode layer 12.
  • the material used for the pixel electrode layer 14 is indium tin oxide material.
  • the thickness of the pixel electrode layer 14 is 10 nm-100 nm.
  • the first filling layer 15 covers the common electrode layer 12, the pixel electrode layer 14 and fills the opening 3, and the material of the first filling layer 15 is silicon oxide material.
  • the light transmittance of the passivation layer 13 is lower than the light transmittance of the first filling layer 15.
  • the present invention also provides a preparation method for preparing the array substrate 1, including the following steps.
  • the thin film transistor structure layer 11 is prepared; specifically, as shown in FIG. 2, in the step of preparing the thin film transistor structure layer 11, a substrate 111 is provided.
  • the thickness of the substrate 111 is A side away from the active layer 112 and corresponding to the area where the active layer 112 is located has a metal light-shielding layer 110; an active layer 112 is formed on the substrate 111; a gate insulating layer 113 is formed on the substrate 111 And cover the active layer 112; form a gate layer 114 on the gate insulating layer 113; form an interlayer dielectric layer 115 on the gate insulating layer 113 and cover the gate layer 114; see figure 3, forming a second opening 22 extending from the interlayer dielectric layer 115 to the surface of the active layer 112; forming a source 116 and a drain 117 on the interlayer dielectric layer 115 and the On the wall of the second opening 22 and on the active layer 112 at the bottom of the second opening 22; as shown
  • a silicon oxide or silicon nitride material is deposited on the second opening
  • a filling layer 118 is formed in 22;
  • a planarization layer 119 is formed on the interlayer dielectric layer 115 and covers the source electrode 116, the drain electrode 117 and the filling layer 118.
  • the common electrode layer 12 is formed on the thin film transistor structure layer 11. Specifically, an indium tin oxide material is deposited on the planarization layer 119 to form the common electrode layer 12.
  • the first opening 21 penetrating the common electrode layer 12 is formed.
  • silicon nitride is deposited in the first opening 21 and the surface of the common electrode layer 12 to form the passivation layer 13.
  • a third opening 23 penetrating through the passivation layer 13, the first opening 21 and extending into the thin film transistor structure layer 11 is formed; in the step of forming the third opening 23, The third opening 23 extends to the surface of the drain 117.
  • the pixel electrode layer 14 is formed in the third opening 23 and on the passivation layer 13.
  • a photoresist material is coated on the pixel electrode layer 14 to form a photoresist layer 4, and the photoresist layer 4 is exposed and developed to form a pixel electrode pattern.
  • the pixel electrode layer 14 is wet-etched to form the pixel electrode and the first gap 31 between the pixel electrode; as shown in FIG. 8, in the In the first notch 31, the passivation layer 13 is dry-etched to form a second notch 32, and the first notch 31 and the second notch 32 form the opening 3.
  • the photoresist layer 4 is stripped and removed.
  • a silicon oxide material is deposited in the opening 3 and the surfaces of the common electrode layer 12 and the pixel electrode layer 14 to form the first filling layer 15.
  • the mask 5 is used to cover the lower edge non-display area of each array substrate 1 on the glass substrate 6, and then the first filling layer 15 is prepared by the chemical vapor deposition method. 1nm-2000 nm.
  • the function of the mask plate 5 is to prevent the first filling layer 15 from covering the terminal area so that it cannot be connected to an IC, a flexible circuit board, and the like.
  • A is the curve of the transmittance of the array substrate where the passivation layer is in contact with the air and the thickness of the first filling layer there
  • B is the curve where the passivation layer is in contact with the pixel electrode layer.
  • the curve of the transmittance of the array substrate and the thickness of the first filling layer It can be seen from FIG. 11 that when the thickness of the first filling layer is 1 nm-2000 nm, the light transmittance of the entire array substrate is 80% or more.
  • the present invention also provides a display device 10 including the array substrate 1 described above.
  • the main point of the design of the present invention is that the array substrate 1 and other components of the display device 10, such as the color filter substrate, the packaging structure, etc., will not be repeated one by one.

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  • General Physics & Mathematics (AREA)
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  • Engineering & Computer Science (AREA)
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Abstract

本发明公开了一种阵列基板及其制备方法、显示装置，阵列基板包括薄膜晶体管结构层；以及公共电极层设于薄膜晶体管结构层上；第一开孔设于公共电极层上；钝化层覆于公共电极层上且填充于第一开孔；像素电极层覆于钝化层上并穿过钝化层和第一开孔连接至薄膜晶体管结构层；开口从像素电极层延伸至公共电极层的表面；第一填充层覆于公共电极层、像素电极层上并填充于开口；所述钝化层的光的透过率小于所述第一填充层的光的透过率。

Description

阵列基板及其制备方法、显示装置 技术领域
本发明涉及显示技术领域，具体为一种阵列基板及其制备方法、显示装置。
 背景技术
近年来，在TFT-LCD中，正在推进用于节省电力化、高清晰化及提高色再现性的项目开发。其中提高穿透性能、提升TFT-LCD的亮度、减少电力损耗，是世界各家面板厂都在攻克的难关。TFT-LCD面板的穿透性是指背光源透过TFT-LCD面板前后的光强之比。通常情况下TFT-LCD的光的透过率只有3-10%，也就是说超过90%的光是无法得到利用的。对于TFT-LCD的阵列基板（TFT）来说，除开金属走线外，对穿透率影响较大的还有由氧化硅、氮化硅、氧化铟锡、平坦层所用材料构成的多层膜结构。每层膜的折射率和消光系数都会对多层膜的整体穿透率产生影响。因此，可以通过调节每层膜的折射率、消光系数、膜层结构等参数来提高多层膜的透过率。
目前业界常用的阵列基板的膜层结构的底层缓冲层由氮化硅和氧化硅构成，间绝缘层由氮化硅和氧化硅构成，钝化层13’（PV）由氮化硅构成。通常来说，氮化硅的折射率会大于氧化硅的折射率，因此，光在穿过氮化硅和氧化硅界面时会有反射，造成透过率降低。为了提高透过率，可用氧化硅代替氮化硅。如图1所示，对于钝化层13’（PV）的氮化硅来说，一部分氮化硅裸露在开口3’中与空气接触，即开口3’处的氮化硅与空气接触；一部分氮化硅与其顶面的氧化铟锡材料制成的像素电极14’接触。如果直接用氧化硅来代替钝化层13’（PV）的氮化硅，与空气接触处的氧化硅的透过率，由于氧化硅与空气的折射率差值小而得到大幅提高，但与像素电极14’接触处的透过率由于氧化硅与像素电极的折射率差值大而降低。最终结果是阵列基板整体的透过率提高并不明显。
 技术问题
为解决上述技术问题：本发明提供一种阵列基板及其制备方法、显示装置，以提高阵列基板整体的光的透过率。
 技术解决方案
解决上述问题的技术方案是：本发明提供一种阵列基板，包括薄膜晶体管结构层；以及公共电极层，设于所述薄膜晶体管结构层上；第一开孔，设于所述公共电极层上；钝化层，覆于所述公共电极层上且填充于所述第一开孔；像素电极层，覆于所述钝化层上并穿过所述钝化层和所述第一开孔连接至所述薄膜晶体管结构层；开口，从所述像素电极层延伸至所述公共电极层的表面；第一填充层，覆于所述公共电极层、所述像素电极层上并填充于所述开口；所述钝化层的光的透过率小于所述第一填充层的光的透过率。
在本发明一实施例中，所述薄膜晶体管结构层包括基底；有源层，设于所述基底上；栅极绝缘层，覆于所述基底上并覆盖所述有源层；栅极层，设于所述栅极绝缘层上；层间介质层，覆于所述栅极绝缘层上并覆盖所述栅极层；第二开孔，从所述层间介质层延伸至所述有源层的表面；源极和漏极，设于所述层间介质层上并分别通过一第二开孔连接至所述有源层；平坦化层，设于所述层间介质层上并覆盖所述源极和所述漏极；所述像素电极层连接至所述漏极。
在本发明一实施例中，所述源极和所述漏极覆于所述第二开孔的孔壁上；所述薄膜晶体管结构层还包括填充层，填充于所述第二开孔中且覆于所述源极和所述漏极的表面；所述填充层所用材料为氧化硅或氮化硅材料。
在本发明一实施例中，所述薄膜晶体管结构层还包括金属遮光层，设于所述基底远离所述有源层的一面且对应于所述有源层所在区域。
在本发明一实施例中，所述基底所用材料为氧化硅和/或氮化硅；所述层间介质层所用材料为氧化硅和/或氮化硅；所述像素电极层和所述公共电极层所用材料均为氧化铟锡材料。
在本发明一实施例中，所述钝化层所用材料为氮化硅材料，所述第一填充层所有材料为氧化硅材料
本发明还提供了一种制备方法，用以制备所述的阵列基板，其特征在于，包括以下步骤：制备所述薄膜晶体管结构层；形成所述公共电极层于所述薄膜晶体管结构层上；形成贯穿所述公共电极层的所述第一开孔；形成所述钝化层于所述第一开孔中和所述公共电极层的表面；形成贯穿所述钝化层、所述第一开孔并延伸至所述薄膜晶体管结构层内的第三开孔；形成所述像素电极层于所述第三开孔中和所述钝化层上；涂布光阻材料于所述像素电极层上形成光阻层，并曝光显影所述光阻层形成像素电极图案；根据形成的所述像素电极图案，湿法刻蚀所述像素电极层形成像素电极以及所述像素电极之间的第一缺口；在所述第一缺口中，干法刻蚀所述钝化层形成第二缺口，所述第一缺口和第二缺口形成所述开口；去除所述光阻层；沉积填充材料于所述开口中和所述公共电极层、所述像素电极层的表面形成所述第一填充层。
在本发明一实施例中，在制备所述薄膜晶体管结构层步骤中，包括提供一基底；形成有源层于所述基底上；形成栅极绝缘层于所述基底上并覆盖所述有源层；形成栅极层于所述栅极绝缘层上；形成层间介质层于所述栅极绝缘层上并覆盖所述栅极层；形成从所述层间介质层延伸至所述有源层的表面的第二开孔；形成源极和漏极于所述层间介质层上以及所述第二开孔的孔壁上和所述第二开孔的孔底的所述有源层上；沉积氧化硅或氮化硅材料于所述第二开孔中形成填充层；形成平坦化层于所述层间介质层上并覆盖所述源极、所述漏极和所述填充层；在形成第三开孔步骤中，所述第三开孔延伸至所述漏极的表面。
在本发明一实施例中，在提供一基底步骤中，所述基底的远离所述有源层的一面且对应于所述有源层所在区域具有金属遮光层。
本发明还提供了一种显示装置，包括所述的阵列基板。
 有益效果
本发明的阵列基板、显示装置，将与空气接触处的钝化层中的氮化硅用氧化硅代替，减小界面反射从而提高与空气接触处的透过率；并在与像素电极层接触处的上部增加第一填充层，减小像素电极层处与空气的界面反射，大幅度地提高了阵列基板整体的光的透过率。阵列基板的制备方法简单，便于操作，能够有效实现提高阵列基板整体透过率的目的。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
下面结合附图和实施例对本发明作进一步解释。
图1是现有技术中的阵列基板的结构图，主要体现钝化层、开口以及像素电极的位置关系以及钝化层一部分裸露于开口与空气接触，一部分设置在像素电极下方与像素电极接触。
图2是本发明实施例的形成第二开孔后的阵列基板的结构图。
图3是本发明实施例的形成平坦化层后的阵列基板的结构图。
图4是本发明实施例的形成第一开孔后的阵列基板的结构图。
图5是本发明实施例的形成第三开孔后的阵列基板的结构图。
图6是本发明实施例的曝光显影光阻层形成像素电极图案的阵列基板的结构图。
图7是本发明实施例的形成第一缺口后的阵列基板的结构图。
图8是本发明实施例的形成第二缺口，即形成开口后的阵列基板的结构图。
图9是本发明实施例的形成第一填充层后的阵列基板的结构图。
图10是本发明实施例的采用掩膜板遮挡阵列基板，沉积的氧化硅材料于开口中和公共电极层上时的装置结构图。
图11为本发明实施例的第一填充层厚度与其透过率的曲线图，其中A为钝化层与空气接触处的阵列基板的透过率与该处的第一填充层厚度的曲线，B为钝化层与像素电极层接触处的阵列基板的透过率与该处的第一填充层厚度的曲线。
附图标记：
1阵列基板；                 10显示装置；
11薄膜晶体管结构层；        12公共电极层；
13、13’钝化层；             14、14’像素电极层；
15第一填充层；              110金属遮光层；
111基底；                   112有源层；
113栅极绝缘层；             114栅极层；
115层间介质层；             116源极；
117漏极；                   118填充层；
119平坦化层；               21第一开孔；
22第二开孔；                23第三开孔；
31第一缺口；                32第二缺口；
3、3’开口；                4光阻层；
5掩膜板；                   6玻璃基板。
 本发明的实施方式
以下实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「顶」、「底」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
如图9所示，在一实施例中，本发明的阵列基板1包括薄膜晶体管结构层11、公共电极层12、钝化层13、像素电极层14、第一填充层15。
如图2至图3所示，所述薄膜晶体管结构层11包括基底111、有源层112、栅极绝缘层113、栅极层114、层间介质层115、源极116和漏极117、平坦化层119以及填充层118。具体地讲，所述有源层112设于所述基底111上；所述栅极绝缘层113覆于所述基底111上并覆盖所述有源层112；所述栅极层114设于所述栅极绝缘层113上；所述层间介质层115覆于所述栅极绝缘层113上并覆盖所述栅极层114；所述第二开孔22从所述层间介质层115延伸至所述有源层112的表面；所述源极116和漏极117设于所述层间介质层115上并分别通过一第二开孔22连接至所述有源层112；所述平坦化层119设于所述层间介质层115上并覆盖所述源极116和所述漏极117。
所述薄膜晶体管结构层11还包括金属遮光层110，所述金属遮光层110设于所述基底111远离所述有源层112的一面且对应于所述有源层112所在区域。所述基底111所用材料为氧化硅和/或氮化硅；所述层间介质层115所用材料为氧化硅和/或氮化硅。
如图4所示，所述公共电极层12设于所述薄膜晶体管结构层11上，所述公共电极层12中具有一第一开孔21，所述第一开孔21对应所述漏极117。所述公共电极层12所用材料均为氧化铟锡材料。
如图5所示，所述钝化层13覆于所述公共电极层12上且填充于所述第一开孔21，所述钝化层13所用材料为氮化硅。
如图6所示，所述像素电极层14覆于所述钝化层13上并穿过所述钝化层13和所述第一开孔21连接至所述薄膜晶体管结构层11的所述漏极117。所述像素电极层14具有开口3，参见图7至图8所示，所述开口3从所述像素电极层14延伸至所述公共电极层12的表面。所述像素电极层14所用材料均为氧化铟锡材料。所述像素电极层14的厚度为10nm-100nm。
如图9所示，所述第一填充层15覆于所述公共电极层12、所述像素电极层14上并填充于所述开口3，第一填充层15所用材料为氧化硅材料，所述钝化层13的光的透过率小于所述第一填充层15的光的透过率。
本发明还提供了一种制备方法，用以制备所述的阵列基板1，包括以下步骤。
制备所述薄膜晶体管结构层11；具体的讲，如图2所示，在制备所述薄膜晶体管结构层11步骤中，包括提供一基底111，在提供一基底111步骤中，所述基底111的远离所述有源层112的一面且对应于所述有源层112所在区域具有金属遮光层110；形成有源层112于所述基底111上；形成栅极绝缘层113于所述基底111上并覆盖所述有源层112；形成栅极层114于所述栅极绝缘层113上；形成层间介质层115于所述栅极绝缘层113上并覆盖所述栅极层114；参见图3所示，形成从所述层间介质层115延伸至所述有源层112的表面的第二开孔22；形成源极116和漏极117于所述层间介质层115上以及所述第二开孔22的孔壁上和所述第二开孔22的孔底的所述有源层112上；参见图4所示，沉积氧化硅或氮化硅材料于所述第二开孔22中形成填充层118；形成平坦化层119于所述层间介质层115上并覆盖所述源极116、所述漏极117和所述填充层118。
参见图4所示，形成所述公共电极层12于所述薄膜晶体管结构层11上。具体地讲，沉积氧化铟锡材料于所述平坦化层119上形成所述公共电极层12。
参见图4所示，形成贯穿所述公共电极层12的所述第一开孔21。
参见图5所示，沉积氮化硅于所述第一开孔21中和所述公共电极层12的表面形成所述钝化层13。
参见图5所示，形成贯穿所述钝化层13、所述第一开孔21并延伸至所述薄膜晶体管结构层11内的第三开孔23；在形成第三开孔23步骤中，所述第三开孔23延伸至所述漏极117的表面。
参见图6所示，形成所述像素电极层14于所述第三开孔23中和所述钝化层13上。
参见图6所示，涂布光阻材料于所述像素电极层14上形成光阻层4，并曝光显影所述光阻层4形成像素电极图案。
参见图7所示，根据形成的所述像素电极图案，湿法刻蚀所述像素电极层14形成像素电极以及所述像素电极之间的第一缺口31；参见图8所示，在所述第一缺口31中，干法刻蚀所述钝化层13形成第二缺口32，所述第一缺口31和第二缺口32形成所述开口3。
参见图9所示，剥离去除所述光阻层4。沉积氧化硅材料于所述开口3中和所述公共电极层12、所述像素电极层14的表面形成所述第一填充层15。具体地讲，参见图10所示，利用所述掩膜板5将玻璃基板6上每个阵列基板1的下边缘非显示区遮住，然后利用化学气相沉积法制备第一填充层15，厚度为1nm-2000 nm。 所述掩膜板5的作用是防止第一填充层15将端子区遮盖而无法与IC、柔性电路板等连接。
如图11所示，图11中，A为钝化层与空气接触处的阵列基板的透过率与该处的第一填充层厚度的曲线，B为钝化层与像素电极层接触处的阵列基板的透过率与该处的第一填充层厚度的曲线。由图11可知，第一填充层厚度在1nm-2000nm时，阵列基板的整体的光的透过率在80％以上。
参见图9所示，本发明还提供了一种显示装置10，包括所述的阵列基板1。本发明的设计要点在于所述阵列基板1，对于显示装置10的其他器件，如彩膜基板、封装结构等就不再一一赘述。
以上仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种阵列基板，其包括
    薄膜晶体管结构层；以及
    公共电极层，设于所述薄膜晶体管结构层上；
    第一开孔，设于所述公共电极层上；
    钝化层，覆于所述公共电极层上且填充于所述第一开孔；
    像素电极层，覆于所述钝化层上并穿过所述钝化层和所述第一开孔连接至所述薄膜晶体管结构层；
    开口，从所述像素电极层延伸至所述公共电极层的表面；
    第一填充层，覆于所述公共电极层、所述像素电极层上并填充于所述开口，所述钝化层的光的透过率小于所述第一填充层的光的透过率。
  2. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管结构层包括
    基底；
    有源层，设于所述基底上；
    栅极绝缘层，覆于所述基底上并覆盖所述有源层；
    栅极层，设于所述栅极绝缘层上；
    层间介质层，覆于所述栅极绝缘层上并覆盖所述栅极层；
    第二开孔，从所述层间介质层延伸至所述有源层的表面；
    源极和漏极，设于所述层间介质层上并分别通过一第二开孔连接至所述有源层；
    平坦化层，设于所述层间介质层上并覆盖所述源极和所述漏极；
    所述像素电极层连接至所述漏极。
  3. 根据权利要求2所述的阵列基板，其中，所述源极和所述漏极覆于所述第二开孔的孔壁上；
    所述薄膜晶体管结构层还包括填充层，填充于所述第二开孔中且覆于所述源极和所述漏极的表面；所述填充层所用材料为氧化硅或氮化硅材料。
  4. 根据权利要求2所述的阵列基板，其中，所述薄膜晶体管结构层还包括金属遮光层，设于所述基底远离所述有源层的一面且对应于所述有源层所在区域。
  5. 根据权利要求2所述的阵列基板，其中，所述基底所用材料为氧化硅和/或氮化硅；所述层间介质层所用材料为氧化硅和/或氮化硅；所述像素电极层和所述公共电极层所用材料均为氧化铟锡材料。
  6. 根据权利要求1所述的阵列基板，其中，所述钝化层所用材料为氮化硅材料，所述第一填充层所有材料为氧化硅材料。
  7. 一种制备方法，用以制备如权利要求1所述的阵列基板，其包括以下步骤：
    制备所述薄膜晶体管结构层；
    形成所述公共电极层于所述薄膜晶体管结构层上；
    形成贯穿所述公共电极层的所述第一开孔；
    形成所述钝化层于所述第一开孔中和所述公共电极层的表面；
    形成贯穿所述钝化层、所述第一开孔并延伸至所述薄膜晶体管结构层内的第三开孔；
    形成所述像素电极层于所述第三开孔中和所述钝化层上；
    涂布光阻材料于所述像素电极层上形成光阻层，并曝光显影所述光阻层形成像素电极图案；
    根据形成的所述像素电极图案，湿法刻蚀所述像素电极层形成像素电极以及所述像素电极之间的第一缺口；
    在所述第一缺口中，干法刻蚀所述钝化层形成第二缺口，所述第一缺口和第二缺口形成所述开口；
    去除所述光阻层；
    沉积填充材料于所述开口中和所述公共电极层、所述像素电极层的表面形成所述第一填充层。
  8. 根据权利要求7所述的制备方法，其中，在制备所述薄膜晶体管结构层步骤中，包括
    提供一基底；
    形成有源层于所述基底上；
    形成栅极绝缘层于所述基底上并覆盖所述有源层；
    形成栅极层于所述栅极绝缘层上；
    形成层间介质层于所述栅极绝缘层上并覆盖所述栅极层；
    形成从所述层间介质层延伸至所述有源层的表面的第二开孔；
    形成源极和漏极于所述层间介质层上以及所述第二开孔的孔壁上和所述第二开孔的孔底的所述有源层上；
    沉积氧化硅或氮化硅材料于所述第二开孔中形成填充层；
    形成平坦化层于所述层间介质层上并覆盖所述源极、所述漏极和所述填充层；
    在形成第三开孔步骤中，所述第三开孔延伸至所述漏极的表面。
  9. 根据权利要求7所述的制备方法，其中，在提供一基底步骤中，所述基底的远离所述有源层的一面且对应于所述有源层所在区域具有金属遮光层。
  10. 一种显示装置，其包括如权利要求1所述的阵列基板。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114023762B (zh) * 2021-10-18 2023-06-27 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN114203775B (zh) * 2021-11-24 2023-05-09 深圳市华星光电半导体显示技术有限公司 Oled显示面板和oled显示装置
CN119815921A (zh) * 2022-02-28 2025-04-11 武汉华星光电技术有限公司 阵列基板及其制备方法、显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130052798A (ko) * 2011-11-14 2013-05-23 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
JP2013205435A (ja) * 2012-03-27 2013-10-07 Jsr Corp アレイ基板、液晶表示素子、感放射線性樹脂組成物およびアレイ基板の製造方法
CN107175815A (zh) * 2017-07-13 2017-09-19 上海天马微电子有限公司 一种透射式液晶面板与3d打印装置
CN107942591A (zh) * 2017-11-20 2018-04-20 深圳市华星光电技术有限公司 一种阵列基板及液晶显示面板
CN108227288A (zh) * 2018-01-26 2018-06-29 惠州市华星光电技术有限公司 一种va显示面板及显示装置
CN109445214A (zh) * 2018-12-13 2019-03-08 昆山龙腾光电有限公司 阵列基板及制作方法和液晶显示面板

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6686977B2 (en) * 2001-07-24 2004-02-03 Three-Five Systems, Inc. Liquid crystal on silicon device
JP4095518B2 (ja) * 2002-10-31 2008-06-04 セイコーエプソン株式会社 電気光学装置及び電子機器
JP2004170554A (ja) * 2002-11-18 2004-06-17 Victor Co Of Japan Ltd 反射型液晶表示装置
KR101877448B1 (ko) * 2011-06-30 2018-07-12 엘지디스플레이 주식회사 프린지 필드 스위칭 모드 액정표시장치용 어레이 기판 및 이의 제조 방법
CN102723308B (zh) * 2012-06-08 2014-09-24 京东方科技集团股份有限公司 一种阵列基板及其制作方法和显示装置
TWI516836B (zh) * 2013-03-07 2016-01-11 群創光電股份有限公司 液晶顯示面板及包含其之液晶顯示裝置
CN205121103U (zh) * 2015-10-28 2016-03-30 武汉华星光电技术有限公司 一种内嵌式自电容触控基板及面板
CN105607365A (zh) * 2015-12-31 2016-05-25 深圳市华星光电技术有限公司 一种coa基板及其制作方法
CN105895581B (zh) * 2016-06-22 2019-01-01 武汉华星光电技术有限公司 Tft基板的制作方法
CN106842728A (zh) * 2017-04-06 2017-06-13 深圳市华星光电技术有限公司 阵列基板及该阵列基板的制作方法
TWI655768B (zh) * 2018-04-24 2019-04-01 友達光電股份有限公司 陣列基板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130052798A (ko) * 2011-11-14 2013-05-23 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
JP2013205435A (ja) * 2012-03-27 2013-10-07 Jsr Corp アレイ基板、液晶表示素子、感放射線性樹脂組成物およびアレイ基板の製造方法
CN107175815A (zh) * 2017-07-13 2017-09-19 上海天马微电子有限公司 一种透射式液晶面板与3d打印装置
CN107942591A (zh) * 2017-11-20 2018-04-20 深圳市华星光电技术有限公司 一种阵列基板及液晶显示面板
CN108227288A (zh) * 2018-01-26 2018-06-29 惠州市华星光电技术有限公司 一种va显示面板及显示装置
CN109445214A (zh) * 2018-12-13 2019-03-08 昆山龙腾光电有限公司 阵列基板及制作方法和液晶显示面板

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