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WO2020191872A1 - 像素补偿电路及显示装置 - Google Patents

像素补偿电路及显示装置 Download PDF

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Publication number
WO2020191872A1
WO2020191872A1 PCT/CN2019/086321 CN2019086321W WO2020191872A1 WO 2020191872 A1 WO2020191872 A1 WO 2020191872A1 CN 2019086321 W CN2019086321 W CN 2019086321W WO 2020191872 A1 WO2020191872 A1 WO 2020191872A1
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WO
WIPO (PCT)
Prior art keywords
switch tube
control
compensation circuit
terminal
control signal
Prior art date
Application number
PCT/CN2019/086321
Other languages
English (en)
French (fr)
Inventor
张锋
Original Assignee
武汉华星光电半导体显示技术有限公司
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Publication of WO2020191872A1 publication Critical patent/WO2020191872A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel compensation circuit and a display device.
  • OLED display technology As a new type of display technology, Light Emitting Diode (OLED) display technology has many advantages that other display technologies cannot match, such as wide viewing angle, wide color gamut, high contrast, low power consumption, and foldable/flexible advantages.
  • the new generation of display technology has strong competitiveness.
  • OLED display technology is divided into passive OLED (Passive Matrix OLED, PMOLED) display technology and active OLED (Active Matrix OLED, AMOLED) display technology according to its driving mode.
  • PMOLED Passive Matrix OLED
  • AMOLED Active Matrix OLED
  • AMOLED display technology Technology is a display technology applied to TVs and mobile devices. With its low power consumption and large size, it has broad application prospects in power-sensitive portable electronic devices.
  • AMOLED display technology is the current flexible display technology.
  • the basic pixel drive circuit of AMOLED is a 2T1C circuit that includes a switch thin film transistor Switch Thin Film Transistor (STFT, T1), a driver TFT (DTFT, T2) and a storage capacitor Cst.
  • the driving current of OLED is controlled by DTFT.
  • the DTFT is restricted by factors such as the uniformity of the manufacturing process and the attenuation over time, its threshold voltage Vth is prone to drift, which causes the OLED drive current to change easily, which makes the OLED display image uneven and affects the image quality.
  • the existing 6T1C pixel compensation circuit which is widely recognized and applied in the industry, is composed of 6 TFTs and 1 storage capacitor. Although the pixel compensation circuit eliminates the Vth drift of DTFT, the AMOLED picture is not displayed. However, the voltage drop drift of the power supply voltage VDD will seriously affect the current of the OLED.
  • the present disclosure provides a pixel compensation circuit and a display device, which solves the problem that the OLED drive current of the pixel compensation circuit and the display device is easily affected by the drift of the threshold voltage Vth of the driving thin film transistor and the voltage drop drift of the power supply voltage VDD.
  • OLED display image is not uniform, technical problems affecting image quality.
  • the embodiments of the present disclosure provide a pixel compensation circuit, including:
  • a drive switch tube the drive switch tube includes a first end, a second end and a control end, and the first end of the drive switch tube is connected to a first power signal;
  • a first switch tube the first switch tube includes a first end, a second end and a control end, the first end of the first switch tube is connected to the control end of the drive switch tube, the The second end of the first switch tube is connected to the second end of the drive switch tube, and the control end of the first switch tube is connected to a first scan signal;
  • the second switch tube includes a first terminal, a second terminal, and a control terminal.
  • the first terminal of the second switch tube is connected to the reset voltage, and the control terminal of the second switch tube is connected to the first terminal.
  • a third switch tube the third switch tube includes a first end, a second end, and a control end, the first end of the third switch tube is connected to a data signal, and the control end of the third switch tube Connected to the first scan signal;
  • a fourth switch tube the fourth switch tube includes a first end, a second end, and a control end, the first end of the fourth switch tube is grounded, and the second end of the fourth switch tube is connected The second end of the third switch tube and the control end of the fourth switch tube are connected to a first control signal;
  • the fifth switch tube includes a first end, a second end, and a control end.
  • the first end of the fifth switch tube is connected to the second end of the driving switch tube and the The second end of the first switch tube, and the control end of the fifth switch tube are connected to a second control signal;
  • a storage capacitor the storage capacitor has a first terminal and a second terminal, and the first terminal of the storage capacitor is connected to the second terminal of the third switch tube and the first terminal of the fourth switch tube. Two ends, the second end of the storage capacitor is connected to the control end of the drive switch, the first end of the first switch, and the second end of the second switch ;as well as
  • a light-emitting element is an organic light-emitting diode, the light-emitting element has an anode end and a cathode end, the anode end of the light-emitting element is connected to the second end of the fifth switch tube, the light-emitting element
  • the cathode terminal is connected to a second power signal, and the voltage of the first power signal is greater than the voltage of the second power signal.
  • the driving switch tube, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, and the fifth switch tube All are thin film transistors, wherein the first end of the thin film transistor is the source, the second end is the drain, and the control end is the gate.
  • the driving switch tube, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, and the fifth switch tube All are P-type thin film transistors or all are N-type thin film transistors.
  • the driving process of the pixel compensation circuit includes a reset phase, a compensation phase, and a light-emitting phase, where:
  • the reset stage using the first scan signal, the second scan signal, the first control signal, and the second control signal to turn on the second switch tube and the fourth switch tube and turn off Turning off the driving switch tube, the first switch tube, the third switch tube, and the fifth switch tube;
  • the compensation stage using the first scan signal, the second scan signal, the first control signal, and the second control signal to turn on the first switch tube and the third switch tube and turn off Turning off the driving switch tube, the second switch tube, the fourth switch tube, and the fifth switch tube;
  • the light-emitting stage using the first scan signal, the second scan signal, the first control signal, and the second control signal to turn on the drive switch tube, the fourth switch tube, and the The fifth switch tube turns off the first switch tube, the second switch tube, and the third switch tube.
  • the pixel compensation circuit when the driving switch tube and the first switch tube to the fifth switch tube are both P-type thin film transistors, when the second scan signal and the When the first control signal output is both low level, and the first scan signal and the second control signal output are both high level, the pixel compensation circuit is in the reset phase; when the first scan signal When the output is low and the second scan signal, the first control signal, and the second control signal output are all high, the pixel compensation circuit is in the compensation stage; when the first When the control signal and the second control signal output are both low level, and the first scan signal and the second scan signal output are both high level, the pixel compensation circuit is in the light-emitting stage.
  • the pixel compensation circuit when the driving switch tube and the first switch tube to the fifth switch tube are both P-type thin film transistors, when the second scan signal and the When the first control signal output is both high level, and the first scan signal and the second control signal output are both low level, the pixel compensation circuit is in the reset phase; when the first scan signal When the output is high and the second scan signal, the first control signal, and the second control signal output are all low, the pixel compensation circuit is in the compensation stage; when the first control signal When both the output of the second control signal and the second control signal are high, and the output of the first scan signal and the second scan signal are both low, the pixel compensation circuit is in the light-emitting stage.
  • the first power signal is at a high level
  • the second power signal is at a low level
  • the embodiments of the present disclosure provide a pixel compensation circuit, including:
  • a drive switch tube the drive switch tube includes a first end, a second end and a control end, and the first end of the drive switch tube is connected to a first power signal;
  • a first switch tube the first switch tube includes a first end, a second end and a control end, the first end of the first switch tube is connected to the control end of the drive switch tube, the The second end of the first switch tube is connected to the second end of the drive switch tube, and the control end of the first switch tube is connected to a first scan signal;
  • the second switch tube includes a first terminal, a second terminal, and a control terminal.
  • the first terminal of the second switch tube is connected to the reset voltage, and the control terminal of the second switch tube is connected to the first terminal.
  • a third switch tube the third switch tube includes a first end, a second end, and a control end, the first end of the third switch tube is connected to a data signal, and the control end of the third switch tube Connected to the first scan signal;
  • a fourth switch tube the fourth switch tube includes a first end, a second end, and a control end, the first end of the fourth switch tube is grounded, and the second end of the fourth switch tube is connected The second end of the third switch tube and the control end of the fourth switch tube are connected to a first control signal;
  • the fifth switch tube includes a first end, a second end, and a control end.
  • the first end of the fifth switch tube is connected to the second end of the driving switch tube and the The second end of the first switch tube, and the control end of the fifth switch tube are connected to a second control signal;
  • a storage capacitor the storage capacitor has a first terminal and a second terminal, and the first terminal of the storage capacitor is connected to the second terminal of the third switch tube and the first terminal of the fourth switch tube. Two ends, the second end of the storage capacitor is connected to the control end of the drive switch, the first end of the first switch, and the second end of the second switch ;as well as
  • the light emitting element has an anode terminal and a cathode terminal, the anode terminal of the light emitting element is connected to the second end of the fifth switch tube, and the cathode terminal of the light emitting element is connected to a second power source signal.
  • the driving switch tube, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, and the fifth switch tube are all thin film transistors, wherein the first end of the thin film transistor is the source, the second end is the drain, and the control end is the gate.
  • the driving switch tube, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, and the fifth switch tube are all P-type thin film transistors or all N-type thin film transistors.
  • the driving process of the pixel compensation circuit includes a reset phase, a compensation phase, and a light-emitting phase, where:
  • the reset stage using the first scan signal, the second scan signal, the first control signal, and the second control signal to turn on the second switch tube and the fourth switch tube and turn off Turning off the driving switch tube, the first switch tube, the third switch tube, and the fifth switch tube;
  • the compensation stage using the first scan signal, the second scan signal, the first control signal, and the second control signal to turn on the first switch tube and the third switch tube and turn off Turning off the driving switch tube, the second switch tube, the fourth switch tube, and the fifth switch tube;
  • the light-emitting stage using the first scan signal, the second scan signal, the first control signal, and the second control signal to turn on the drive switch tube, the fourth switch tube, and the The fifth switch tube turns off the first switch tube, the second switch tube, and the third switch tube.
  • the pixel compensation circuit when the driving switch tube and the first switch tube to the fifth switch tube are both P-type thin film transistors, when the second scan signal and When the first control signal output is both low level, and the first scan signal and the second control signal output are both high level, the pixel compensation circuit is in the reset phase; when the first When the output of the scan signal is at a low level, and the second scan signal, the first control signal, and the second control signal output are all at a high level, the pixel compensation circuit is in the compensation stage; When the first control signal and the second control signal output are both low level, and the first scan signal and the second scan signal output are both high level, the pixel compensation circuit is in the light-emitting stage.
  • the pixel compensation circuit when the driving switch tube and the first switch tube to the fifth switch tube are both P-type thin film transistors, when the second scan signal and When the first control signal output is high, and the first scan signal and the second control signal output are both low, the pixel compensation circuit is in the reset phase; when the first When the scan signal output is at a high level, and the second scan signal, the first control signal, and the second control signal output are all at a low level, the pixel compensation circuit is in the compensation stage; when the first When the control signal and the second control signal output are both high level, and the first scan signal and the second scan signal output are both low level, the pixel compensation circuit is in the light-emitting stage.
  • the voltage of the first power signal is greater than the voltage of the second power signal.
  • the first power signal is at a high level
  • the second power signal is at a low level
  • the light-emitting element is an organic light-emitting diode.
  • the embodiments of the present disclosure provide a display device including the pixel compensation circuit described above.
  • the pixel compensation circuit and the display device provided by the present disclosure can reduce or eliminate the influence of the drift of the threshold voltage Vth of the driving thin film transistor on the OLED driving current through the pixel compensation circuit. Reduce or eliminate the influence of the voltage drop drift of the power supply voltage VDD on the OLED drive current, and simultaneously realize the compensation for the voltage drop drift between the threshold voltage Vth of the driving thin film transistor and the power supply voltage VDD, which is beneficial to improve the uniformity of the light-emitting brightness of the light-emitting element .
  • FIG. 1 is a schematic structural diagram of a prior art OLED pixel driving circuit
  • FIG. 2 is a schematic structural diagram of a pixel compensation circuit provided by an embodiment of the disclosure.
  • FIG. 3 is a timing diagram of a pixel compensation circuit provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic structural diagram of a pixel compensation circuit in a reset phase provided by an embodiment of the disclosure
  • FIG. 5 is a schematic diagram of a compensation stage structure of a pixel compensation circuit provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a structure of a pixel compensation circuit in a light-emitting stage provided by an embodiment of the disclosure.
  • the disclosed embodiments are directed to the prior art pixel compensation circuit and display device.
  • the OLED driving current is easily affected by the drift of the driving thin film transistor threshold voltage Vth and the voltage drop drift of the power supply voltage VDD, resulting in uneven OLED display images. , Technical issues affecting image quality. This embodiment can solve this defect.
  • the pixel compensation circuit includes a driving switch tube T, a first switching tube T1, a second switching tube T2, a third switching tube T3, a fourth switching tube T4, and a fifth switching tube.
  • T5 storage capacitor Cst and light-emitting element
  • the driving switch tube T includes a first terminal, a second terminal and a control terminal, and the first terminal of the driving switch tube T is connected to the first power signal VDD;
  • the first switch tube T1 includes a first end, a second end, and a control end, the first end of the first switch tube T1 and the control end of the drive switch tube T Connected, the second end of the first switch tube T1 is connected to the second end of the drive switch tube T, and the control end of the first switch tube T1 is connected to the first scan signal Scan(n );
  • the second switch tube T2 includes a first terminal, a second terminal and a control terminal, the first terminal of the second switch tube T2 is connected to the reset voltage Vi, and the second switch tube T2
  • the control terminal is connected to the second scan signal Scan(n-1), wherein the reset voltage Vi has a lower potential, and the drive switch tube T and the second switch tube T2 are compared with node B;
  • the third switch tube T3, the third switch tube T3 includes a first terminal, a second terminal, and a control terminal, the first terminal of the third switch tube T3 is connected to the data signal Vdata, and the third switch tube T3 The control terminal is connected to the first scan signal Scan(n);
  • the fourth switch tube T4, the fourth switch tube T4 includes a first terminal, a second terminal and a control terminal, the first terminal of the fourth switch tube T4 is grounded, and the second terminal of the fourth switch tube T4 Terminal is connected to the second terminal of the third switch tube T3, the control terminal of the fourth switch tube T4 is connected to the first control signal EM1, wherein the fourth switch tube T4 and the third switch tube T3 intersects at node A;
  • the fifth switch tube T5, the fifth switch tube T5 includes a first terminal, a second terminal and a control terminal, the first terminal of the fifth switch tube T5 is connected to the second terminal of the drive switch tube T Terminal and the second terminal of the first switch tube T1, and the control terminal of the fifth switch tube T5 is connected to a second control signal EM2;
  • a storage capacitor Cst the storage capacitor Cst has a first end and a second end, the first end of the storage capacitor Cst is connected to the second end of the third switch tube T3 and the fourth switch tube
  • the second terminal of T4 the second terminal of the storage capacitor Cst is connected to the control terminal of the drive switch tube T, the first terminal of the first switch tube T1, and the second terminal
  • the second end of the switch tube T2 specifically, the first end of the storage capacitor Cst is the node A, and the second end of the storage capacitor Cst is the node B;
  • the light-emitting element may be an Organic Light-Emitting Diode (OLED), the light-emitting element has an anode end and a cathode end, and the anode end of the light-emitting element is connected to the fifth switch tube T5 The second terminal and the cathode terminal of the light-emitting element are connected to a second power signal VSS.
  • OLED Organic Light-Emitting Diode
  • the voltage provided by the first power signal VDD is greater than the voltage provided by the second power signal VSS.
  • the first power signal VDD is a high-level signal
  • the second power signal VSS is a low-level signal. Flat signal.
  • the switch tube T5 is a thin film transistor, wherein the first end of the thin film transistor is a source (Source, S), the second end is a drain (Drain, D), and the control end is a gate (Gate, G).
  • the switch tubes T5 are all P-type thin film transistors, and this embodiment takes the P-type thin film transistor as an example for description. It should be understood that the driving switching tube T, the first switching tube T1, the second switching tube T2, the third switching tube T3, the fourth switching tube T4, and the fifth switching tube T5 can also be an N-type thin film transistor. When the N-type thin film transistor is selected, it corresponds to the direction of the OLED current in the pixel compensation circuit and the first scan signal Scan(n) and the second scan signal Scan (N-1). The high and low levels of the first control signal EM1 and the first control signal EM2 vary with the use of thin film transistors of different conductivity types as the switching elements of the pixel compensation circuit. Here, Do not repeat them one by one.
  • FIG. 3 is a timing diagram of the pixel compensation circuit provided by the embodiment of the disclosure. Since the P-type thin film transistor is selected in this embodiment, when the gate signal input by the switch tube is low, the corresponding switch tube is turned on; When the gate signal input by the switching tube is high, the corresponding switching tube is turned off.
  • the driving process of the pixel compensation circuit includes a reset phase, a compensation phase, and a light-emitting phase, where:
  • the pixel compensation circuit is in the reset stage.
  • the output of the second scan signal Scan(n-1) and the first control signal EM1 are both low, and the first scan signal
  • the output of Scan(n) and the second control signal EM2 are both high, that is, the second scan signal Scan(n-1) and the first control signal EM1 are turned on, and the first scan signal Scan( n) Turn off with the second control signal EM2.
  • FIG. 4 shows the equivalent circuit structure of the reset phase.
  • the second switching tube T2 and the fourth switching tube T4 are in a conducting state, the driving switching tube T, the first switching tube T1, the third switching tube T3, and the fifth switching tube T5
  • the voltage at the first end of the storage capacitor Cst namely node A
  • the voltage at the second end of the storage capacitor Cst namely node B
  • the reset Voltage Vi is reset to the reset Voltage Vi.
  • the voltage of the first terminal of the driving switch tube T is the voltage of the data signal Vdata
  • the output of the first scan signal Scan(n) is low, and the second scan signal Scan(n-1), the first control signal EM1 and the second control signal
  • the output of the signal EM2 is high, that is, the first scan signal Scan(n) is turned on, the second scan signal Scan(n-1), the first control signal EM1 and the second control signal EM2 shut down.
  • Figure 5 shows the equivalent circuit structure diagram of the compensation stage.
  • the driving switching tube T, the first switching tube T1, and the third switching tube T3 are in a conducting state, the driving switching tube T, the second switching tube T2, the fourth switching tube T4, and the The fifth switch tube T5 is in the off state.
  • the voltage at the first end of the storage capacitor Cst that is, the node A, is written into the voltage provided by the data signal Vdata.
  • the control terminal and the second terminal are short-connected through the first switch tube T1, so the drive switch tube T and the first switch tube T1 form a diode connect structure 10, and the The diode connection structure 20, the first power signal VDD is written by the first terminal of the driving switch tube, and the control terminal (gate ) Perform charging until the control terminal (gate) potential of the drive switch T is VDD+Vth, that is, the potential of the node B is VDD+Vth.
  • the emission (Emission) stage The emission (Emission) stage:
  • the outputs of the first control signal EM1 and the second control signal EM2 are both low, and the first scan signal Scan(n) and the second scan signal Scan(n) -1)
  • the outputs are both high, that is, the first control signal EM1 and the second control signal EM2 are turned on, and the first scan signal Scan(n) and the second scan signal Scan(n-1) )shut down.
  • Figure 6 shows the equivalent circuit structure diagram of the light-emitting stage.
  • the driving switch tube T, the fourth switch tube T4, and the fifth switch tube T5 are in a conducting state, the first switch tube T1, the second switch tube T2, and the third switch tube T3 In the off state, the voltage at the first terminal of the storage capacitor Cst, that is, the node A, is 0V.
  • the light-emitting current IOLED of the OLED is only related to the data signal Data, and has nothing to do with the threshold voltage Vth of the driving switch tube T and the first power supply voltage VDD, thereby solving the problem of the driving thin film transistor T The problem of uneven light-emitting brightness caused by the drift of the threshold voltage Vth and the drift of the voltage drop of the first power supply voltage VDD.
  • the embodiments of the present disclosure also provide an embodiment of a display device.
  • the display device may be an AMOLED display device, and the AMOLED display device includes the pixel compensation circuit described in the foregoing embodiment.
  • the display device provided by the embodiments of the present disclosure adopts the pixel compensation circuit provided by the above-mentioned embodiments of the present disclosure to prevent the light-emitting element in each pixel from changing the light-emitting brightness in one frame of the picture, and to avoid the driving film in each pixel
  • the drift of the threshold voltage Vth of the transistor and the drift of the voltage drop of the power supply voltage VDD cause the uneven brightness of the light-emitting elements in each pixel, thereby improving the display effect and display uniformity.
  • the pixel compensation circuit and the display device provided by the embodiments of the present disclosure, through the pixel compensation circuit, can reduce or eliminate the influence of the drift of the threshold voltage Vth of the driving thin film transistor on the OLED driving current, and can also reduce Or eliminate the influence of the voltage drop drift of the power supply voltage VDD on the OLED driving current, and simultaneously realize the compensation for the voltage drop drift between the threshold voltage Vth of the driving thin film transistor and the power supply voltage VDD, which is beneficial to improve the uniformity of the light-emitting brightness of the light-emitting element.

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Abstract

一种像素补偿电路及显示装置，像素补偿电路包括驱动开关管(T)、第一至第五开关管(T1-T5)、存储电容(Cst)以及发光元件(OLED)，降低或消除驱动薄膜晶体管的阈值电压(Vth)的漂移以及电源电压(VDD)的压降漂移对OLED驱动电流的影响，同时实现对驱动薄膜晶体管的阈值电压(Vth)与电源电压(VDD)的压降漂移的补偿，提高了发光元件(OLED)的发光亮度的均匀性。

Description

像素补偿电路及显示装置 技术领域
本揭示涉及显示技术领域，尤其涉及一种像素补偿电路及显示装置。
 背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示技术作为新型显示技术，具有其它一些显示技术所无法比拟的诸多优势，如宽视角、广色域、高对比度、低功耗和可折叠/柔性等优点，因而其在新世代显示技术中具有强有力的竞争力，OLED显示技术根据其驱动方式分为无源OLED(Passive Matrix OLED，PMOLED)显示技术和有源OLED(Active Matrix OLED，AMOLED)显示技术，其中AMOLED显示技术是一种应用于电视和移动设备的显示技术，以其低功耗、大尺寸的特点在对功耗敏感的便携电子设备中有着广阔的应用前景，同时AMOLED显示技术是当前柔性显示技术的重点发展方向之一。
如图1所示，AMOLED的基本像素驱动电路是2T1C电路即包括一个开关薄膜晶体管Switch Thin Film Transistor (STFT, T1)，一个驱动薄膜晶体管Driver TFT (DTFT，T2)和一个存储电容Cst。OLED的驱动电流由DTFT控制，IOLED为驱动晶体管M1对应于栅源电压 Vgs的电流，其大小为：IOLED=k(Vgs-Vth)2，其中k为DTFT的电流放大系数，由DTFT自身属性决定，Vth为DTFT的阈值电压。因DTFT受制程工艺的均一性和随使用时间的衰减等因素制约，使得其阈值电压Vth易发生漂移，导致OLED驱动电流易发生变化，从而使得OLED显示图像不均匀，影响画质。
现有的目前被业界广为认可和应用的为一种6T1C像素补偿电路，该电路由6个TFT和1个存储电容构成，该像素补偿电路虽然消除了DTFT的Vth漂移所引起AMOLED画面显示不均的问题，然而，电源电压VDD的压降漂移则会严重影响OLED的电流。
因此，需要提供一种新的像素补偿电路及显示装置，来解决上述技术问题。
 技术问题
本揭示提供一种像素补偿电路及显示装置，解决了像素补偿电路及显示装置，其 OLED驱动电流易受到驱动薄膜晶体管阈值电压Vth的漂移及电源电压VDD的压降漂移的影响而发生变化，导致 OLED显示图像不均匀，影响画质的技术问题。
 技术解决方案
为解决上述问题，本揭示提供的技术方案如下：
本揭示实施例提供一种像素补偿电路，包括：
驱动开关管，所述驱动开关管包括第一端、第二端与控制端，所述驱动开关管的所述第一端连接第一电源信号；
第一开关管，所述第一开关管包括第一端、第二端与控制端，所述第一开关管的所述第一端与所述驱动开关管的所述控制端连接，所述第一开关管的所述第二端与所述驱动开关管的所述第二端连接，所述第一开关管的所述控制端连接第一扫描信号；
第二开关管，所述第二开关管包括第一端、第二端与控制端，所述第二开关管的所述第一端连接复位电压，所述第二开关管的控制端连接第二扫描信号；
第三开关管，所述第三开关管包括第一端、第二端与控制端，所述第三开关管的所述第一端连接数据信号，所述第三开关管的所述控制端连接所述第一扫描信号；
第四开关管，所述第四开关管包括第一端、第二端与控制端，所述第四开关管的所述第一端接地，所述第四开关管的所述第二端连接所述第三开关管的所述第二端，所述第四开关管的所述控制端连接第一控制信号；
第五开关管，所述第五开关管包括第一端、第二端与控制端，所述第五开关管的所述第一端连接所述驱动开关管的所述第二端以及所述第一开关管的所述第二端，所述第五开关管的所述控制端连接第二控制信号；
存储电容，所述存储电容具有第一端与第二端，所述存储电容的所述第一端连接所述第三开关管的所述第二端以及所述第四开关管的所述第二端，所述存储电容的所述第二端连接所述驱动开关管的所述控制端、所述第一开关管的所述第一端以及所述第二开关管的所述第二端；以及
发光元件，所述发光元件为有机发光二极管，所述发光元件具有阳极端与阴极端，所述发光元件的所述阳极端连接所述第五开关管的所述第二端，所述发光元件的所述阴极端连接第二电源信号，所述第一电源信号的电压大于所述第二电源信号的电压。
在本揭示提供的像素补偿电路中，所述驱动开关管、所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管以及所述第五开关管均为薄膜晶体管，其中所述薄膜晶体管的第一端为源极，第二端为漏极以及控制端为栅极。
在本揭示提供的像素补偿电路中，所述驱动开关管、所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管以及所述第五开关管均为P型薄膜晶体管或均为N型薄膜晶体管。
在本揭示提供的像素补偿电路中，所述像素补偿电路的驱动过程包括复位阶段、补偿阶段以及发光阶段，其中：
所述复位阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述第二开关管与所述第四开关管并关断所述驱动开关管、所述第一开关管、所述第三开关管以及所述第五开关管；
所述补偿阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述第一开关管以及所述第三开关管并关断所述驱动开关管、所述第二开关管、所述第四开关管以及所述第五开关管；
所述发光阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述驱动开关管、所述第四开关管以及所述第五开关管并关断所述第一开关管、所述第二开关管以及所述第三开关管。
在本揭示提供的像素补偿电路中，在所述驱动开关管与所述第一开关管至所述第五开关管均为P型薄膜晶体管的情况下，当所述第二扫描信号与所述第一控制信号输出均为低电平，且所述第一扫描信号与所述第二控制信号输出均为高电平时，所述像素补偿电路处于所述复位阶段；当所述第一扫描信号输出为低电平，且所述第二扫描信号、所述第一控制信号与所述第二控制信号输出均为高电平时，所述像素补偿电路处于所述补偿阶段；当所述第一控制信号与所述第二控制信号输出均为低电平，且所述第一扫描信号与所述第二扫描信号输出均为高电平时，所述像素补偿电路处于所述发光阶段。
在本揭示提供的像素补偿电路中，在所述驱动开关管与所述第一开关管至所述第五开关管均为P型薄膜晶体管的情况下，当所述第二扫描信号与所述第一控制信号输出均为高电平，且所述第一扫描信号与所述第二控制信号输出均为低电平时，所述像素补偿电路处于所述复位阶段；当所述第一扫描信号输出为高电平，且所述第二扫描信号、第一控制信号与所述第二控制信号输出均为低电平时，所述像素补偿电路处于所述补偿阶段；当所述第一控制信号与所述第二控制信号输出均为高电平，且所述第一扫描信号与所述第二扫描信号输出均为低电平时，所述像素补偿电路处于所述发光阶段。
在本揭示提供的像素补偿电路中，所述第一电源信号为高电平，所述第二电源信号为低电平。
本揭示实施例提供一种像素补偿电路，包括：
驱动开关管，所述驱动开关管包括第一端、第二端与控制端，所述驱动开关管的所述第一端连接第一电源信号；
第一开关管，所述第一开关管包括第一端、第二端与控制端，所述第一开关管的所述第一端与所述驱动开关管的所述控制端连接，所述第一开关管的所述第二端与所述驱动开关管的所述第二端连接，所述第一开关管的所述控制端连接第一扫描信号；
第二开关管，所述第二开关管包括第一端、第二端与控制端，所述第二开关管的所述第一端连接复位电压，所述第二开关管的控制端连接第二扫描信号；
第三开关管，所述第三开关管包括第一端、第二端与控制端，所述第三开关管的所述第一端连接数据信号，所述第三开关管的所述控制端连接所述第一扫描信号；
第四开关管，所述第四开关管包括第一端、第二端与控制端，所述第四开关管的所述第一端接地，所述第四开关管的所述第二端连接所述第三开关管的所述第二端，所述第四开关管的所述控制端连接第一控制信号；
第五开关管，所述第五开关管包括第一端、第二端与控制端，所述第五开关管的所述第一端连接所述驱动开关管的所述第二端以及所述第一开关管的所述第二端，所述第五开关管的所述控制端连接第二控制信号；
存储电容，所述存储电容具有第一端与第二端，所述存储电容的所述第一端连接所述第三开关管的所述第二端以及所述第四开关管的所述第二端，所述存储电容的所述第二端连接所述驱动开关管的所述控制端、所述第一开关管的所述第一端以及所述第二开关管的所述第二端；以及
发光元件，所述发光元件具有阳极端与阴极端，所述发光元件的所述阳极端连接所述第五开关管的所述第二端，所述发光元件的所述阴极端连接第二电源信号。
在本揭示实施例提供的像素补偿电路中，所述驱动开关管、所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管以及所述第五开关管均为薄膜晶体管，其中所述薄膜晶体管的第一端为源极，第二端为漏极以及控制端为栅极。
在本揭示实施例提供的像素补偿电路中，所述驱动开关管、所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管以及所述第五开关管均为P型薄膜晶体管或均为N型薄膜晶体管。
在本揭示实施例提供的像素补偿电路中，所述像素补偿电路的驱动过程包括复位阶段、补偿阶段以及发光阶段，其中：
所述复位阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述第二开关管与所述第四开关管并关断所述驱动开关管、所述第一开关管、所述第三开关管以及所述第五开关管；
所述补偿阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述第一开关管以及所述第三开关管并关断所述驱动开关管、所述第二开关管、所述第四开关管以及所述第五开关管；
所述发光阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述驱动开关管、所述第四开关管以及所述第五开关管并关断所述第一开关管、所述第二开关管以及所述第三开关管。
在本揭示实施例提供的像素补偿电路中，在所述驱动开关管与所述第一开关管至所述第五开关管均为P型薄膜晶体管的情况下，当所述第二扫描信号与所述第一控制信号输出均为低电平，且所述第一扫描信号与所述第二控制信号输出均为高电平时，所述像素补偿电路处于所述复位阶段；当所述第一扫描信号输出为低电平，且所述第二扫描信号、所述第一控制信号与所述第二控制信号输出均为高电平时，所述像素补偿电路处于所述补偿阶段；当所述第一控制信号与所述第二控制信号输出均为低电平，且所述第一扫描信号与所述第二扫描信号输出均为高电平时，所述像素补偿电路处于所述发光阶段。
在本揭示实施例提供的像素补偿电路中，在所述驱动开关管与所述第一开关管至所述第五开关管均为P型薄膜晶体管的情况下，当所述第二扫描信号与所述第一控制信号输出均为高电平，且所述第一扫描信号与所述第二控制信号输出均为低电平时，所述像素补偿电路处于所述复位阶段；当所述第一扫描信号输出为高电平，且所述第二扫描信号、第一控制信号与所述第二控制信号输出均为低电平时，所述像素补偿电路处于所述补偿阶段；当所述第一控制信号与所述第二控制信号输出均为高电平，且所述第一扫描信号与所述第二扫描信号输出均为低电平时，所述像素补偿电路处于所述发光阶段。
在本揭示实施例提供的像素补偿电路中，所述第一电源信号的电压大于所述第二电源信号的电压。
在本揭示实施例提供的像素补偿电路中，所述第一电源信号为高电平，所述第二电源信号为低电平。
在本揭示实施例提供的像素补偿电路中，所述发光元件为有机发光二极管。
本揭示实施例提供一种显示装置，包含上述像素补偿电路。
 有益效果
本揭示的有益效果为：本揭示提供的像素补偿电路及显示装置，通过所述像素补偿电路，既可以实现降低或消除驱动薄膜晶体管的阈值电压Vth的漂移对OLED驱动电流的影响，同时也可以降低或消除电源电压VDD的压降漂移对OLED驱动电流的影响，可同时实现对驱动薄膜晶体管的阈值电压Vth与电源电压VDD的压降漂移的补偿，有利于提高发光元件的发光亮度的均匀性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术的OLED像素驱动电路的结构示意图；
图2为本揭示实施例提供的一种像素补偿电路的结构示意图；
图3为本揭示实施例提供的一种像素补偿电路的时序示意图；
图4为本揭示实施例提供的一种像素补偿电路的复位阶段结构示意图；
图5为本揭示实施例提供的一种像素补偿电路的补偿阶段结构示意图；
图6为本揭示实施例提供的一种像素补偿电路的发光阶段结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
本揭示实施例针对现有技术的像素补偿电路及显示装置，其 OLED驱动电流易受到驱动薄膜晶体管阈值电压Vth的漂移及电源电压VDD的压降漂移的影响而发生变化，导致 OLED显示图像不均匀，影响画质的技术问题。本实施例能够解决该缺陷。
实施例一
如图2所示，本揭示实施例提供的像素补偿电路，包括驱动开关管T、第一开关管T1、第二开关管T2、第三开关管T3、第四开关管T4、第五开关管T5、存储电容Cst以及发光元件，具体电路连接关系如下：
驱动开关管T，所述驱动开关管T包括第一端、第二端与控制端，所述驱动开关管T的第一端连接第一电源信号VDD；
第一开关管T1，所述第一开关管T1包括第一端、第二端与控制端，所述第一开关管T1的所述第一端与所述驱动开关管T的所述控制端连接，所述第一开关管T1的所述第二端与所述驱动开关管T的所述第二端连接，所述第一开关管T1的所述控制端连接第一扫描信号Scan（n）；
第二开关管T2，所述第二开关管T2包括第一端、第二端与控制端，所述第二开关管T2的所述第一端连接复位电压Vi，所述第二开关管T2的所述控制端连接第二扫描信号Scan（n-1），其中所述复位电压Vi的电位较低，所述驱动开关管T与所述第二开关管T2相较于节点B；
第三开关管T3，所述第三开关管T3包括第一端、第二端与控制端，所述第三开关管T3的所述第一端连接数据信号Vdata，所述第三开关管T3的所述控制端连接所述第一扫描信号Scan（n）；
第四开关管T4，所述第四开关管T4包括第一端、第二端与控制端，所述第四开关管T4的所述第一端接地，所述第四开关管T4的第二端连接所述第三开关管T3的所述第二端，所述第四开关管T4的所述控制端连接第一控制信号EM1，其中所述第四开关管T4与所述第三开关管T3相交于节点A；
第五开关管T5，所述第五开关管T5包括第一端、第二端与控制端，所述第五开关管T5的所述第一端连接所述驱动开关管T的所述第二端以及所述第一开关管T1的所述第二端，所述第五开关管T5的所述控制端连接第二控制信号EM2；
存储电容Cst，所述存储电容Cst具有第一端与第二端，所述存储电容Cst的所述第一端连接所述第三开关管T3的所述第二端以及所述第四开关管T4的所述第二端，所述存储电容Cst的所述第二端连接所述驱动开关管T的所述控制端、所述第一开关管T1的所述第一端以及所述第二开关管T2的所述第二端，具体地，所述存储电容Cst的所述第一端即为所述节点A，所述存储电容Cst的所述第二端即为所述节点B；
发光元件，所述发光元件可为有机发光二极管（Organic Light-Emitting Diode，OLED），所述发光元件具有阳极端与阴极端，所述发光元件的所述阳极端连接所述第五开关管T5的所述第二端，所述发光元件的所述阴极端连接第二电源信号VSS。
其中，所述第一电源信号VDD提供的电压大于所述第二电源信号VSS提供的电压，具体地，所述第一电源信号VDD为高电平信号，所述第二电源信号VSS为低电平信号。
在本揭示实施例中，所述驱动开关管T、所述第一开关管T1、所述第二开关管T2、所述第三开关管T3、所述第四开关管T4以及所述第五开关管T5均为薄膜晶体管，其中所述薄膜晶体管的第一端为源极（Source，S），第二端为漏极（Drain，D）以及控制端为栅极（Gate，G）。
在本揭示实施例中，所述驱动开关管T、所述第一开关管T1、所述第二开关管T2、所述第三开关管T3、所述第四开关管T4以及所述第五开关管T5均为P型薄膜晶体管，本实施例以P型薄膜晶体管为例进行说明。应理解的是，所述驱动开关管T、所述第一开关管T1、所述第二开关管T2、所述第三开关管T3、所述第四开关管T4以及所述第五开关管T5也可为为N型薄膜晶体管，当选用N型薄膜晶体管时，对应所述像素补偿电路中的所述OLED电流流向及所述第一扫描信号Scan（n）、所述第二扫描信号Scan（n-1）、所述第一控制信号EM1及所述第一控制信号EM2的高低电平随之采用不同导电类型的薄膜晶体管作为所述像素补偿电路的开关元件的不同而改变，在此不再一一赘述。
如图3所示为本揭示实施例提供的像素补偿电路的时序示意图，由于本实施例中选用P型薄膜晶体管，当开关管输入的栅极信号为低电平时，对应开关管导通；当开关管输入的栅极信号为高电平时，对应开关管关断。所述像素补偿电路的驱动过程包括复位阶段、补偿阶段以及发光阶段，其中：
所述复位（Reset）阶段：
在t1时间段，所述像素补偿电路处于复位阶段，此时所述第二扫描信号Scan（n-1）与所述第一控制信号EM1输出均为低电平，且所述第一扫描信号Scan（n）与所述第二控制信号EM2输出均为高电平时，即所述第二扫描信号Scan（n-1）与所述第一控制信号EM1打开，所述第一扫描信号Scan（n）与所述第二控制信号EM2关闭。
如图4所示为复位阶段的等效电路结构图。所述第二开关管T2与所述第四开关管T4处于导通状态，所述驱动开关管T、所述第一开关管T1、所述第三开关管T3以及所述第五开关管T5处于关断状态，此时所述存储电容Cst的所述第一端，即节点A的电压复位至0V，所述存储电容Cst的所述第二端，即节点B的电压复位至所述复位电压Vi。具体地，所述驱动开关管T的所述第一端的电压为所述数据信号Vdata电压，则所述驱动开关管T的所述控制端与所述第一端之间的电压差为Vgs=Vi-Vdata，需保证Vgs=Vi-Vdata<Vth，即Vi< Vdata+ Vth时，所述驱动开关管T处于关断状态，其中，Vth为所述驱动开关管T的阈值电压。
所述补偿（Compensate）阶段：
在t2时间段，此时所述第一扫描信号Scan（n）输出为低电平，且所述第二扫描信号Scan（n-1）、所述第一控制信号EM1与所述第二控制信号EM2输出均为高电平时，即所述第一扫描信号Scan（n）打开，所述第二扫描信号Scan（n-1）、所述第一控制信号EM1与所述第二控制信号EM2关闭。
如图5所示为补偿阶段的等效电路结构图。所述驱动开关管T、所述第一开关管T1以及所述第三开关管T3处于导通状态，所述驱动开关管T、所述第二开关管T2、所述第四开关管T4以及所述第五开关管T5处于关断状态，此时所述存储电容Cst的所述第一端，即节点A的电压写入所述数据信号Vdata提供的电压，由于所述驱动开关管T的所述控制端与所述第二端通过所述第一开关管T1短接，因此所述驱动开关管T与所述第一开关管T1形成一个二极管连接（Diode connect）结构10，通过所述二极管连接结构20，所述第一电源信号VDD由所述驱动开关管的所述第一端写入，经过所述二极管连接结构20，将所述驱动开关管T的所述控制端（栅极）进行充电至所述驱动开关管T的所述控制端（栅极）电位为VDD+Vth，即所述节点B的电位为VDD+Vth。
所述发光（Emission）阶段：
在t3时间段，此时所述第一控制信号EM1与所述第二控制信号EM2输出均为低电平，且所述第一扫描信号Scan（n）与所述第二扫描信号Scan（n-1）输出均为高电平时，即所述第一控制信号EM1与所述第二控制信号EM2打开，所述第一扫描信号Scan（n）与所述第二扫描信号Scan（n-1）关闭。
如图6所示为发光阶段的等效电路结构图。所述驱动开关管T、所述第四开关管T4以及所述第五开关管T5处于导通状态，所述第一开关管T1、所述第二开关管T2以及所述第三开关管T3处于关断状态，此时所述存储电容Cst的所述第一端，即节点A的电压为0V，由于所述存储电容Cst的耦合作用，所述驱动开关管T的所述控制端（栅极）电位为VDD+Vth，即所述节点B的电位为VDD+Vth-Vdata，因此，OLED的发光电流IOLED为IOLED =k[(VDD+Vth-Vdata- VDD)- Vth]2 =k·Vdata 2，其中k为系数。
由上式可知，OLED的发光电流IOLED仅与所述数据信号Data有关，与所述驱动开关管T的阈值电压Vth与所述第一电源电压VDD无关，从而解决了由于所述驱动薄膜晶体管T的阈值电压Vth的漂移及所述第一电源电压VDD的压降漂移所造成的发光亮度不均的问题。
实施例二
本揭示实施例还提供一种显示装置的实施例。在本实施例中，所述显示装置可为AMOLED显示装置，AMOLED显示装置包括上述实施例所述的像素补偿电路。
本揭示实施例提供的显示装置，采用本揭示上述实施例提供的像素补偿电路，可以避免每个像素内的发光元件在一帧画面中的发光亮度发生变化，以及，避免各像素内的驱动薄膜晶体管的阈值电压Vth的漂移以及电源电压VDD的压降漂移造成的各像素内发光元件发光亮度的不均匀，从而提高显示效果和显示均匀性。
有益效果为：本揭示实施例提供的像素补偿电路及显示装置，通过所述像素补偿电路，既可以实现降低或消除驱动薄膜晶体管的阈值电压Vth的漂移对OLED驱动电流的影响，同时也可以降低或消除电源电压VDD的压降漂移对OLED驱动电流的影响，可同时实现对驱动薄膜晶体管的阈值电压Vth与电源电压VDD的压降漂移的补偿，有利于提高发光元件的发光亮度的均匀性。
综上所述，虽然本揭示已以优选实施例揭露如上，但上述优选实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种像素补偿电路，包括：
    驱动开关管，所述驱动开关管包括第一端、第二端与控制端，所述驱动开关管的所述第一端连接第一电源信号；
    第一开关管，所述第一开关管包括第一端、第二端与控制端，所述第一开关管的所述第一端与所述驱动开关管的所述控制端连接，所述第一开关管的所述第二端与所述驱动开关管的所述第二端连接，所述第一开关管的所述控制端连接第一扫描信号；
    第二开关管，所述第二开关管包括第一端、第二端与控制端，所述第二开关管的所述第一端连接复位电压，所述第二开关管的控制端连接第二扫描信号；
    第三开关管，所述第三开关管包括第一端、第二端与控制端，所述第三开关管的所述第一端连接数据信号，所述第三开关管的所述控制端连接所述第一扫描信号；
    第四开关管，所述第四开关管包括第一端、第二端与控制端，所述第四开关管的所述第一端接地，所述第四开关管的所述第二端连接所述第三开关管的所述第二端，所述第四开关管的所述控制端连接第一控制信号；
    第五开关管，所述第五开关管包括第一端、第二端与控制端，所述第五开关管的所述第一端连接所述驱动开关管的所述第二端以及所述第一开关管的所述第二端，所述第五开关管的所述控制端连接第二控制信号；
    存储电容，所述存储电容具有第一端与第二端，所述存储电容的所述第一端连接所述第三开关管的所述第二端以及所述第四开关管的所述第二端，所述存储电容的所述第二端连接所述驱动开关管的所述控制端、所述第一开关管的所述第一端以及所述第二开关管的所述第二端；以及
    发光元件，所述发光元件为有机发光二极管，所述发光元件具有阳极端与阴极端，所述发光元件的所述阳极端连接所述第五开关管的所述第二端，所述发光元件的所述阴极端连接第二电源信号，所述第一电源信号的电压大于所述第二电源信号的电压。
  2. 根据权利要求1所述的像素补偿电路，其中所述驱动开关管、所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管以及所述第五开关管均为薄膜晶体管，其中所述薄膜晶体管的第一端为源极，第二端为漏极以及控制端为栅极。
  3. 根据权利要求2所述的像素补偿电路，其中所述驱动开关管、所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管以及所述第五开关管均为P型薄膜晶体管或均为N型薄膜晶体管。
  4. 根据权利要求1所述的像素补偿电路，其中所述像素补偿电路的驱动过程包括复位阶段、补偿阶段以及发光阶段，其中：
    所述复位阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述第二开关管与所述第四开关管并关断所述驱动开关管、所述第一开关管、所述第三开关管以及所述第五开关管；
    所述补偿阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述第一开关管以及所述第三开关管并关断所述驱动开关管、所述第二开关管、所述第四开关管以及所述第五开关管；
    所述发光阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述驱动开关管、所述第四开关管以及所述第五开关管并关断所述第一开关管、所述第二开关管以及所述第三开关管。
  5. 根据权利要求4所述的像素补偿电路，其中在所述驱动开关管与所述第一开关管至所述第五开关管均为P型薄膜晶体管的情况下，当所述第二扫描信号与所述第一控制信号输出均为低电平，且所述第一扫描信号与所述第二控制信号输出均为高电平时，所述像素补偿电路处于所述复位阶段；当所述第一扫描信号输出为低电平，且所述第二扫描信号、所述第一控制信号与所述第二控制信号输出均为高电平时，所述像素补偿电路处于所述补偿阶段；当所述第一控制信号与所述第二控制信号输出均为低电平，且所述第一扫描信号与所述第二扫描信号输出均为高电平时，所述像素补偿电路处于所述发光阶段。
  6. 根据权利要求4所述的像素补偿电路，其中在所述驱动开关管与所述第一开关管至所述第五开关管均为P型薄膜晶体管的情况下，当所述第二扫描信号与所述第一控制信号输出均为高电平，且所述第一扫描信号与所述第二控制信号输出均为低电平时，所述像素补偿电路处于所述复位阶段；当所述第一扫描信号输出为高电平，且所述第二扫描信号、第一控制信号与所述第二控制信号输出均为低电平时，所述像素补偿电路处于所述补偿阶段；当所述第一控制信号与所述第二控制信号输出均为高电平，且所述第一扫描信号与所述第二扫描信号输出均为低电平时，所述像素补偿电路处于所述发光阶段。
  7. 根据权利要求1所述的像素补偿电路，其中所述第一电源信号为高电平，所述第二电源信号为低电平。
  8. 一种像素补偿电路，包括：
    驱动开关管，所述驱动开关管包括第一端、第二端与控制端，所述驱动开关管的所述第一端连接第一电源信号；
    第一开关管，所述第一开关管包括第一端、第二端与控制端，所述第一开关管的所述第一端与所述驱动开关管的所述控制端连接，所述第一开关管的所述第二端与所述驱动开关管的所述第二端连接，所述第一开关管的所述控制端连接第一扫描信号；
    第二开关管，所述第二开关管包括第一端、第二端与控制端，所述第二开关管的所述第一端连接复位电压，所述第二开关管的控制端连接第二扫描信号；
    第三开关管，所述第三开关管包括第一端、第二端与控制端，所述第三开关管的所述第一端连接数据信号，所述第三开关管的所述控制端连接所述第一扫描信号；
    第四开关管，所述第四开关管包括第一端、第二端与控制端，所述第四开关管的所述第一端接地，所述第四开关管的所述第二端连接所述第三开关管的所述第二端，所述第四开关管的所述控制端连接第一控制信号；
    第五开关管，所述第五开关管包括第一端、第二端与控制端，所述第五开关管的所述第一端连接所述驱动开关管的所述第二端以及所述第一开关管的所述第二端，所述第五开关管的所述控制端连接第二控制信号；
    存储电容，所述存储电容具有第一端与第二端，所述存储电容的所述第一端连接所述第三开关管的所述第二端以及所述第四开关管的所述第二端，所述存储电容的所述第二端连接所述驱动开关管的所述控制端、所述第一开关管的所述第一端以及所述第二开关管的所述第二端；以及
    发光元件，所述发光元件具有阳极端与阴极端，所述发光元件的所述阳极端连接所述第五开关管的所述第二端，所述发光元件的所述阴极端连接第二电源信号。
  9. 根据权利要求8所述的像素补偿电路，其中所述驱动开关管、所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管以及所述第五开关管均为薄膜晶体管，其中所述薄膜晶体管的第一端为源极，第二端为漏极以及控制端为栅极。
  10. 根据权利要求9所述的像素补偿电路，其中所述驱动开关管、所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管以及所述第五开关管均为P型薄膜晶体管或均为N型薄膜晶体管。
  11. 根据权利要求8所述的像素补偿电路，其中所述像素补偿电路的驱动过程包括复位阶段、补偿阶段以及发光阶段，其中：
    所述复位阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述第二开关管与所述第四开关管并关断所述驱动开关管、所述第一开关管、所述第三开关管以及所述第五开关管；
    所述补偿阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述第一开关管以及所述第三开关管并关断所述驱动开关管、所述第二开关管、所述第四开关管以及所述第五开关管；
    所述发光阶段：利用所述第一扫描信号、所述第二扫描信号、所述第一控制信号及所述第二控制信号导通所述驱动开关管、所述第四开关管以及所述第五开关管并关断所述第一开关管、所述第二开关管以及所述第三开关管。
  12. 根据权利要求11所述的像素补偿电路，其中在所述驱动开关管与所述第一开关管至所述第五开关管均为P型薄膜晶体管的情况下，当所述第二扫描信号与所述第一控制信号输出均为低电平，且所述第一扫描信号与所述第二控制信号输出均为高电平时，所述像素补偿电路处于所述复位阶段；当所述第一扫描信号输出为低电平，且所述第二扫描信号、所述第一控制信号与所述第二控制信号输出均为高电平时，所述像素补偿电路处于所述补偿阶段；当所述第一控制信号与所述第二控制信号输出均为低电平，且所述第一扫描信号与所述第二扫描信号输出均为高电平时，所述像素补偿电路处于所述发光阶段。
  13. 根据权利要求11所述的像素补偿电路，其中在所述驱动开关管与所述第一开关管至所述第五开关管均为P型薄膜晶体管的情况下，当所述第二扫描信号与所述第一控制信号输出均为高电平，且所述第一扫描信号与所述第二控制信号输出均为低电平时，所述像素补偿电路处于所述复位阶段；当所述第一扫描信号输出为高电平，且所述第二扫描信号、第一控制信号与所述第二控制信号输出均为低电平时，所述像素补偿电路处于所述补偿阶段；当所述第一控制信号与所述第二控制信号输出均为高电平，且所述第一扫描信号与所述第二扫描信号输出均为低电平时，所述像素补偿电路处于所述发光阶段。
  14. 根据权利要求8所述的像素补偿电路，其中所述第一电源信号的电压大于所述第二电源信号的电压。
  15. 根据权利要求14所述的像素补偿电路，其中所述第一电源信号为高电平，所述第二电源信号为低电平。
  16. 根据权利要求8所述的像素补偿电路，其中所述发光元件为有机发光二极管。
  17. 一种显示装置，其特征在于，包括权利要求8所述的像素补偿电路。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12094410B2 (en) * 2022-01-28 2024-09-17 Mianyang HKC Optoelectronics Technology Co., Ltd. Driving voltage compensation circuit, driving circuit, pixel driving circuit and display device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110738964A (zh) * 2019-10-29 2020-01-31 京东方科技集团股份有限公司 像素电路及显示装置
CN110890056A (zh) * 2019-11-25 2020-03-17 南京中电熊猫平板显示科技有限公司 一种自发光显示装置以及像素内补偿电路

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100141644A1 (en) * 2008-12-05 2010-06-10 Lee Baek-Woon Display device and method of driving the same
US20110134100A1 (en) * 2009-12-08 2011-06-09 Bo-Yong Chung Pixel circuit and organic electro-luminescent display apparatus
CN103943060A (zh) * 2013-06-28 2014-07-23 上海天马微电子有限公司 有机发光显示器及其像素电路、像素电路的驱动方法
CN104157240A (zh) * 2014-07-22 2014-11-19 京东方科技集团股份有限公司 像素驱动电路、驱动方法、阵列基板及显示装置
CN104464630A (zh) * 2014-12-23 2015-03-25 昆山国显光电有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器
US9215777B2 (en) * 2012-12-13 2015-12-15 Samsung Display Co., Ltd. Pixel and organic light emitting display device using the same
CN105185305A (zh) * 2015-09-10 2015-12-23 京东方科技集团股份有限公司 一种像素电路、其驱动方法及相关装置
CN105989791A (zh) * 2015-01-27 2016-10-05 上海和辉光电有限公司 Oled像素补偿电路和oled像素驱动方法
CN106847179A (zh) * 2017-04-12 2017-06-13 武汉华星光电技术有限公司 一种像素补偿电路及显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5177999B2 (ja) * 2006-12-05 2013-04-10 株式会社半導体エネルギー研究所 液晶表示装置
KR101458373B1 (ko) * 2008-10-24 2014-11-06 엘지디스플레이 주식회사 유기전계 발광 디스플레이 장치
CN202855271U (zh) * 2012-11-13 2013-04-03 京东方科技集团股份有限公司 像素电路及显示装置
CN103971640B (zh) * 2014-05-07 2016-08-24 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法和显示装置
CN104036725B (zh) * 2014-05-29 2017-10-03 京东方科技集团股份有限公司 像素电路及其驱动方法、有机发光显示面板及显示装置
CN103996377B (zh) * 2014-05-30 2016-07-06 京东方科技集团股份有限公司 像素电路和显示装置
CN105206221B (zh) * 2014-06-13 2018-06-22 京东方科技集团股份有限公司 像素驱动电路、驱动方法、阵列基板及显示装置
CN104751779A (zh) * 2014-11-25 2015-07-01 上海和辉光电有限公司 显示装置、oled像素驱动电路及其驱动方法
CN104575389A (zh) * 2015-01-29 2015-04-29 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板及显示装置
CN104658484B (zh) * 2015-03-18 2018-01-16 上海和辉光电有限公司 显示装置、像素驱动电路及其驱动方法
CN207115974U (zh) * 2017-08-29 2018-03-16 京东方科技集团股份有限公司 一种像素电路及显示装置
CN109166522B (zh) * 2018-09-28 2022-10-18 昆山国显光电有限公司 像素电路、其驱动方法及显示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100141644A1 (en) * 2008-12-05 2010-06-10 Lee Baek-Woon Display device and method of driving the same
US20110134100A1 (en) * 2009-12-08 2011-06-09 Bo-Yong Chung Pixel circuit and organic electro-luminescent display apparatus
US9215777B2 (en) * 2012-12-13 2015-12-15 Samsung Display Co., Ltd. Pixel and organic light emitting display device using the same
CN103943060A (zh) * 2013-06-28 2014-07-23 上海天马微电子有限公司 有机发光显示器及其像素电路、像素电路的驱动方法
CN104157240A (zh) * 2014-07-22 2014-11-19 京东方科技集团股份有限公司 像素驱动电路、驱动方法、阵列基板及显示装置
CN104464630A (zh) * 2014-12-23 2015-03-25 昆山国显光电有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器
CN105989791A (zh) * 2015-01-27 2016-10-05 上海和辉光电有限公司 Oled像素补偿电路和oled像素驱动方法
CN105185305A (zh) * 2015-09-10 2015-12-23 京东方科技集团股份有限公司 一种像素电路、其驱动方法及相关装置
CN106847179A (zh) * 2017-04-12 2017-06-13 武汉华星光电技术有限公司 一种像素补偿电路及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12094410B2 (en) * 2022-01-28 2024-09-17 Mianyang HKC Optoelectronics Technology Co., Ltd. Driving voltage compensation circuit, driving circuit, pixel driving circuit and display device

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