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WO2020140810A1 - 阵列基板母板及显示面板母板 - Google Patents

阵列基板母板及显示面板母板 Download PDF

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Publication number
WO2020140810A1
WO2020140810A1 PCT/CN2019/128299 CN2019128299W WO2020140810A1 WO 2020140810 A1 WO2020140810 A1 WO 2020140810A1 CN 2019128299 W CN2019128299 W CN 2019128299W WO 2020140810 A1 WO2020140810 A1 WO 2020140810A1
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WO
WIPO (PCT)
Prior art keywords
array substrate
connection line
array
electrically connected
electrical test
Prior art date
Application number
PCT/CN2019/128299
Other languages
English (en)
French (fr)
Inventor
贾丹
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/957,343 priority Critical patent/US11360361B2/en
Publication of WO2020140810A1 publication Critical patent/WO2020140810A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate motherboard and a display panel motherboard.
  • the static electricity accumulation problem often occurs in the manufacturing process of the display panel mother board.
  • the manufacturing process of the display panel mother board needs to involve microscope sampling and other operations.
  • There are many operations such as taking out, putting in and transporting by the staff, and the instantaneous static electricity of the human body can reach tens of thousands of volts, so it will be generated in this process Static electricity accumulation problem.
  • the slimming process or cutting eg Stick Cut, strip cutting; Group Cut, cell cutting; Cell Cut, individual cutting
  • there are also operations such as manual transportation and screen splitting by personnel, so here
  • the problem of static electricity accumulation can also occur during the process.
  • ESD Electro-Static discharge
  • the protection circuit may be burned or a short circuit (Short) problem may occur, which may result in ET (Electrical Test).
  • AD Abnormal Display failure occurs when lighting, which affects the quality of the display panel.
  • an embodiment of the present disclosure provides an array substrate mother board, which includes: a plurality of array substrates and connecting wires.
  • Each array substrate of the plurality of array substrates includes an electrical test area, and the electrical test area includes a first conductive terminal; the connection line is electrically connected to the first conductive terminal of the electrical test area of the plurality of array substrates To electrically connect the plurality of array substrates together.
  • connection line is disposed between the plurality of array substrates, and the connection line extends in a row direction or a column direction in which the plurality of array substrates are arranged.
  • each row of array substrates in the plurality of array substrates is electrically connected together by one connection line; and/or each row of array substrates in the plurality of array substrates is connected by one of the connection lines The wires are electrically connected together.
  • connection line includes a first connection line and a second connection line;
  • the array substrate motherboard is divided into a plurality of display units, and each display unit of the plurality of display units includes at least two The array substrate;
  • each of the display units includes a set of electrical test areas, the set of electrical test areas includes second conductive terminals; and in each of the display units, the first of each of the array substrate electrical test areas
  • the conductive terminal is electrically connected to the second conductive terminal of the group electrical test area of the display unit through the first connection line; in the plurality of display units, the second conductive terminal of the group electrical test area of each display unit passes The second connection wires are electrically connected together.
  • each of the display units includes m rows and n columns of the array substrates; wherein, m and n are positive integers; m is smaller than the array substrates arranged in the array substrate mother board The number of rows, n is less than the number of columns in which the array substrates are arranged in the array substrate mother board.
  • each of the display units includes a plurality of rows and columns of the array substrates; in each of the display units, the first conductive terminal and the first A connection line is electrically connected; the first conductive terminal of the electrical test area of each array substrate in the same column is electrically connected to a first connection line.
  • the second conductive terminal of the group electrical test area of each display unit located in the same row is electrically connected to a second connection line; and/or, located in the same column
  • the second conductive terminal of the group electrical test area of each display unit is electrically connected to a second connection line.
  • the display unit includes at least one column of the array substrate.
  • one set of the second connection line is disposed between two adjacent rows of the array substrate, and the second connection line is electrically tested with each of the display units The second conductive terminals of the zone are all electrically connected.
  • one second connection line is provided between every two adjacent rows of the array substrate; or, one second connection line is provided between any two adjacent rows of the array substrate.
  • connection line includes a plurality of sub-connection lines, and one end of each of the plurality of sub-connection lines is electrically connected to at least one of the first conductive terminals.
  • connection line is the same layer and the same material as any conductive layer on the plurality of array substrates.
  • connection line and the gate electrode layer or the source-drain electrode layer of the plurality of array substrates are in the same layer and the same material.
  • a display panel motherboard which includes the array substrate motherboard described in any of the above embodiments.
  • FIG. 1a is a schematic structural diagram of an array substrate motherboard according to some embodiments of the present disclosure
  • FIG. 1b is a schematic structural diagram of another array substrate motherboard according to some embodiments of the present disclosure.
  • FIG. 1c is a schematic structural diagram of still another array substrate motherboard according to some embodiments of the present disclosure.
  • FIG. 2a is a schematic structural diagram of still another array substrate motherboard according to some embodiments of the present disclosure.
  • FIG. 2b is a schematic structural diagram of still another array substrate motherboard according to some embodiments of the present disclosure.
  • FIG. 2c is a schematic structural view of yet another array substrate motherboard provided according to some embodiments of the present disclosure.
  • FIG. 3a is a schematic structural diagram of yet another array substrate motherboard according to some embodiments of the present disclosure.
  • FIG. 3b is a schematic structural diagram of still another array substrate motherboard according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a motherboard of a display panel according to some embodiments of the present disclosure.
  • first and second are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more.
  • Coupled and “connected” and their derivatives may be used.
  • some embodiments may be described using the terms “connected” and “connected in series” to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components do not directly contact each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C” and includes the following combinations of A, B, and C: A only, B only, C only, A, and B Combination, A and C combination, B and C combination, and A, B and C combination.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • orientation or positional relationship indicated by “up/up”, “down/down”, “row/row direction”, and “column/column direction” are based on the orientation or positional relationship shown in the drawings, only for convenience
  • the simplified description of the technical solutions of the present disclosure is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as limiting the present disclosure.
  • An embodiment of the present disclosure provides an array substrate motherboard 1A, as shown in FIGS. 1a and 1b, including: a plurality of array substrates (Cells, also called Array substrates) 10; each array substrate 10 of the plurality of array substrates includes An electrical test area (Electrical Test Pad, ET Pad for short) 20, the electrical test area 20 includes a first conductive terminal 21 (Pin).
  • an electrical test area Electrical Test Pad, ET Pad for short
  • black dots are used to indicate the first conductive terminals 21 of the electrical test area 20.
  • the array substrate motherboard 1A further includes: a connecting wire 30; the connecting wire 30 is electrically connected to the first conductive terminals 21 of the electrical test area 20 of the plurality of array substrates 10 to connect the plurality of array substrates 10 electrically connected together.
  • the array substrate includes a box facing area and an electrical test area 20 on one side of the box facing area.
  • the box facing area is used to face the box facing substrate such as a color filter substrate.
  • the electrical test area 20 is used to set an integrated circuit (Integrated Circuit, referred to as IC ), conductive terminals for wiring on the array substrate 10 and the like.
  • IC integrated Circuit
  • the number of array substrates 10 included in the array substrate mother board 1A is not limited, and can be set accordingly according to the size of the array substrate mother board 1A and the size of the array substrate 10.
  • connection line 30 on the array substrate mother board 1A is not limited, as long as the plurality of array substrates 10 can be electrically connected together. Since the connection line 30 electrically connects the plurality of array substrates 10 together, the connection line 30 can form a loop.
  • connection line 30 is disposed between the plurality of array substrates 10, and the connection line 30 extends along the row direction or column direction where the plurality of array substrates 10 are arranged.
  • the plurality of array substrates 10 on the array substrate mother board 1A may be arranged in multiple rows and columns.
  • the connection line 30 is provided between the plurality of array substrates 10, and the connection line 30 extends along the row direction or the column direction in which the plurality of array substrates 10 are arranged.
  • connection line 30 is provided between two adjacent rows or two columns of array substrates 10, and the connection line 30 extends along the row direction or column direction in which the plurality of array substrates 10 are arranged.
  • the first conductive terminals 21 of different array substrates 10 can be electrically connected to the same connection line 30, so that the static first conductive terminals 21 of different array substrates 10 can be mutually connected by the same connection line 30.
  • the flow of charge between them is beneficial to the dispersion of static electricity.
  • connection line 30 is a single piece, that is, the connection line 30 includes one sub-connection line 3011.
  • each connection line 30 includes a plurality of sub-connection lines 3011, and one end of each sub-connection line 3011 is electrically connected to at least one first conductive terminal 21.
  • each sub-connection line 3011 has a plurality of connection ends 31, and each connection end 31 of the plurality of connection ends 31 is electrically connected to one first conductive terminal 21.
  • each connecting wire 30 can be electrically connected to the plurality of first conductive terminals 21, so that static electricity on the plurality of first conductive terminals 21 can be discharged.
  • the plurality of sub-connection lines 3011 in each connection line 30 may or may not contact each other, which is not limited.
  • each electrical test zone 20 includes a plurality of first conductive terminals 21, and one connection end 31 of a sub-connection line 3011 can be electrically connected to any first conductive terminal 21 in an electrical test zone 20; It may be electrically connected to two or more first conductive terminals 21 in one electrical test zone 20.
  • the first conductive terminal 21 with a greater risk of failure due to static electricity or the relatively important first conductive terminal 21 can be selected to be electrically connected to the connection line 30.
  • the connecting wire 30 is the same layer and the same material as any conductive layer on the plurality of array substrates 10.
  • the any conductive layer may be a patterned conductive layer.
  • the connection line 30 is disposed on the source-drain electrode layer, the connection line 30 is the same layer and the same material as the data line on the array substrate 10; for another example, the connection line 30 is disposed on the gate electrode layer, the connection line 30 and the gate on the array substrate 10
  • the wires have the same layer and the same material; for example, the connecting wire 30 and the electrode on the array substrate 10, such as ITO (Indium Tin Oxide) electrodes, have the same layer and the same material. In this way, the connection line 30 can be produced at the same time when the conductive pattern on the array substrate 10 is produced, thereby simplifying the manufacturing process of the array substrate mother board 1A.
  • connection line 30 may be fabricated separately, and not fabricated in the same layer as any conductive pattern on the array substrate 10.
  • the connection line 30 may be formed by applying photoresist, mask exposure, development, and etching processes.
  • the display panel motherboard After the production of the display panel motherboard is completed, it is necessary to perform the lighting operation at the time of ET on the display panel in the display panel motherboard to detect whether the circuits and wiring of each display panel are normal. Since the display panel mother board is cut into a plurality of display panels before the electrical test, the connecting wire 30 is cut during cutting, and thus does not affect the lighting operation of the display panel ET.
  • An embodiment of the present disclosure provides an array substrate mother board 1A. Since the array substrate mother board 1A includes a plurality of array substrates 10 and connecting wires 30, the connecting wires 30 electrically connect the plurality of array substrates 10 on the array substrate mother board 1A together Therefore, when static electricity is generated at a certain position of the array substrate 10, the static electricity can be led out through the connecting wire 30. During the circulation of static electricity, the static electricity accumulated at that position will be discharged and shared by different positions, thereby reducing the position The static electricity at the place improves the problem of large static electricity accumulation, avoids the damage of the product caused by electrostatic discharge, and improves the product yield.
  • the display panel motherboard can be cut into display panels one by one, and each display panel is separately ET illuminated, that is, the display panel is detected by the Cell ET method; also The display panel motherboard can be cut into multiple groups of display panels, and each group of display panels is individually illuminated by ET, that is, the display panel is detected by the Group ET method; of course, the display panel motherboard can also be cut into multiple rows, and each row of display panels
  • the ET lighting is performed separately, that is, the Stick ET method is used to detect the display panel.
  • connection line 30 when designing the connection line 30, the arrangement of the connection line 30 can be designed according to the cutting method of the display panel motherboard and the ET lighting method.
  • each row of the array substrates 10 in the plurality of array substrates 10 is electrically connected together by a connecting line 30.
  • adjacent row array substrates 10 may be electrically connected together by one connection line 30; adjacent row array substrates 10 may also be electrically connected together by multiple connection lines 30 as shown in FIGS. 1a and 1b.
  • each row of array substrates 10 is electrically connected by a connecting line 30, after the display panel motherboard is completed, when cutting, you can first cut the display panel motherboard into multiple rows of display panels along the row, and then Each row of display panels is cut into display panels one by one, that is, Stick Cut first, and then Cell Cut. At this time, each display panel can be separately illuminated by ET, that is, each display panel is detected by the Cell ET method.
  • each array substrate 10 in the plurality of array substrates 10 is electrically connected together by a connecting wire 30.
  • adjacent column array substrates 10 may be electrically connected together by one connection line 30; adjacent column array substrates 10 may also be electrically connected together by multiple connection lines 30.
  • each array of array substrates 10 is electrically connected by a connecting line 30, after the display panel motherboard is completed, when cutting, the display panel motherboard can be cut into multiple rows of display panels along the column, and then Each display panel is cut into display panels one by one, that is, Stick Cut first, and then Cell Cut. At this time, each display panel can be separately illuminated by ET, that is, each display panel is detected by the Cell ET method.
  • each row of array substrates 10 is electrically connected by a connecting line 30, every two columns of array substrates are electrically connected by a connecting line 30, if the middle position of the two columns of array substrates is Cutting (as shown by the dotted line in FIG. 1b ), because a row of array substrates are not connected together by the connecting line 30, the static electricity generated by any array substrate 10 in the array substrate of the row cannot be discharged through the connecting line 30.
  • each column of array substrates 10 is electrically connected by one connection line 30, and every two or more rows of array substrates are electrically connected by one connection line 30, there is the same problem as above when cutting.
  • each row of array substrates 10 is electrically connected together by one connection line 30, and each column of array substrates 10 is electrically connected together by one connection line 30.
  • each connection line 30 is electrically connected together by one connection line 30.
  • the connection line 30 includes a first connection line 301 and a second connection line 302;
  • the array substrate motherboard 1A is divided into a plurality of display units 01, each display unit 01 of the plurality of display units 01 includes at least two array substrates 10, each display unit 01 includes a group electrical test area 40, and the group electrical test area 40 includes a second conductive terminal 41, each display
  • the first conductive terminal 21 of the electrical test area 20 of each array substrate 10 in the unit 01 is electrically connected to the second conductive terminal 41 of the group electrical test area 40 of the display unit through the first connection line 301;
  • the second conductive terminals 41 of the group electrical test area 40 of each display unit 01 are electrically connected together through the second connection line 302.
  • the number of array substrates 10 included in each display unit 01 is not limited, and may include two array substrates 10; or may include more than two array substrates 10.
  • first conductive terminal 21 of the electrical test area 20 of each array substrate 10 and the second conductive terminal 41 of the group electrical test area 40 may be electrically connected by one first connection line 301 or a plurality of first connection lines 301 . 2a and 2b, for one display unit 01, the number of first connection lines 301 in FIG. 2b is greater than the number of first connection lines 301 in FIG. 2a, because each array substrate in one display unit 01 in FIG.
  • the first conductive terminal 21 of the electrical test area 20 of 10 is electrically connected to the second conductive terminal 41 of the electrical test area 40 through a plurality of first connection lines 301, so when a certain first connection line 301 is damaged, it can pass other
  • the first connection line 301 transmits signals, thereby improving the reliability of the electrical connection between the first conductive terminal 21 of the electrical test area 20 of each array substrate 10 and the second conductive terminal 41 of the group electrical test area 40.
  • the purpose of setting the group electrical test area 40 is to determine whether the multiple array substrates 10 in each display unit 01 have AD failure by performing ET lighting on the group electrical test area 40, because each display unit 01 is detected At this time, the plurality of array substrates 10 can be detected at the same time, so that the detection efficiency can be improved compared to the detection of the plurality of array substrates 10 separately.
  • the arrangement manner of the plurality of array substrates 10 in each display unit 01 is not limited, and two specific embodiments are provided below.
  • each display unit 01 includes m rows and n columns of array substrates 10; where m, n are positive integers, and m is less than the array substrate mother
  • the number of rows in which a plurality of array substrates 10 are arranged in the board is smaller than the number of rows in which the array substrates 10 in the array substrate mother board are arranged. That is to say, each display unit 01 includes some of the plurality of array substrates 10, which are arranged in m rows and n columns.
  • each display unit 01 includes four array substrates 10, which are arranged in two rows and two columns.
  • the array substrate 10 in each display unit 01 is arranged in the same manner. In other embodiments. The arrangement manner of the array substrate 10 in each display unit 01 is not completely the same. In order to facilitate cutting and design of the second connection line 302, so that the second connection line 302 is electrically connected to the second conductive terminals of the plurality of sets of electrical test areas 40, therefore, in some embodiments of the present disclosure, each display unit 01 The array substrate 10 is arranged in the same manner.
  • n and n are not limited.
  • m is 2, and n is 2; or, m is 3 and n is 2.
  • each display unit 01 includes multiple rows and columns of array substrates 10. As shown in FIG. 2b, in each display unit 01, the first conductive terminals 21 of the electrical test areas 20 of the array substrates 10 in the same row are electrically connected to a first connection line 301; and the array substrates in the same column The first conductive terminal 21 of the electrical test area 20 of 10 is electrically connected to a first connection line 301. In this way, as shown in FIG.
  • the first conductive terminals 21 of the included electrical test area 20 All are electrically connected to the second conductive terminal 41 of the electrical test zone 40 through a first connection line 301, so when a certain first connection line 301 is damaged, signals can be transmitted through other first connection lines 301, thereby improving the The reliability of the electrical connection between the first conductive terminal 21 of the electrical test area 20 of each array substrate 10 and the second conductive terminal 41 of the group electrical test area 40.
  • each display unit 01 includes m rows and n columns of array substrates 10
  • the arrangement of the second connection lines 302 is not limited, so as to be able to be electrically connected to the second conductive terminals 41 of each group of electrical test areas 40 as quasi.
  • the second conductive terminal 41 of the group electrical test area 40 in the same row of display units 01 is electrically connected to a second connection line 302.
  • the second conductive terminals 41 of the group electrical test area 40 in the adjacent row display unit 01 are electrically connected together by a second connection line 302; or as shown in FIG. 2a and As shown in FIG. 2b, the second conductive terminals 41 of the group electrical test area 40 in the adjacent row of display units 01 are electrically connected together by two or more second connection lines 302.
  • the second conductive terminal 41 of the group electrical test area 40 in the same column of display units 01 is electrically connected to a second connection line 302.
  • the second conductive terminals 41 of the group electrical test area 40 in the adjacent column display units 01 may be electrically connected together through one second connection line 302; or may be connected through two or more second connections The wires 302 are electrically connected together.
  • the second conductive terminal 41 of the group electrical testing area 40 in the same row of display units 01 is electrically connected to a second connecting line 302, the group electrical testing area 40 in the adjacent row of display units 01
  • the second conductive terminals 41 are electrically connected together by a second connection line 302, if cut along the middle position of the adjacent column of display units 01 (as shown by the dotted line in FIG. 2c), the group of display units 01 in some columns Since the electrical test area 40 is not connected together by the connection line 30, the static electricity generated by any one of the display units 01 in this column of display units 01 cannot be discharged through the second connection line 302.
  • the second conductive terminal 41 of the group electrical testing area 40 in the same column of the display unit 01 is electrically connected to a second connection line 302
  • the second conductive terminal 41 of the group electrical testing area 40 in the adjacent column of the display unit 01 The terminals 41 are electrically connected together by a second connecting wire 302, and there is the same problem as above when cutting.
  • the second conductive terminals 41 of the group electrical test area 40 in the same row of display units 01 are electrically connected to a second connection line 302 and are located in the group of the same column of display units 01
  • the second conductive terminal 41 of the electrical test area 40 is electrically connected to a second connection line 302.
  • the display panel motherboard can be cut into multiple display units 01 first, and then each display unit 01 is cut into display panels one by one, that is, Group Cut , And then proceed to Cell Cut. Since each display unit 01 has a group electrical test area 40, the group electrical test area 40 can be ET lighted to determine whether the plurality of array substrates 10 in the display unit 01 have AD defects, that is, each display is detected by the Group ET method panel.
  • the display panel motherboard is first cut into a plurality of display units 01.
  • the second connection line 302 electrically connected to the second conductive terminal 41 will be cut, and thus will not affect the ET lighting operation of each display unit 01.
  • each display unit 01 includes at least one column of array substrates 10 in the array substrate motherboard 1A.
  • each display unit 01 may include one array substrate 10 in the array substrate mother board 1A; it may also include two or more array substrates 10 in the array substrate mother board 1A.
  • each display unit 01 includes at least one row of array substrates 10 in the array substrate motherboard 1A
  • the second conductive terminals 41 of the group electrical test area 40 in the adjacent display unit 01 may pass a second
  • the connection wires 302 are connected together; as shown in FIG. 3a, the connection wires 302 may be connected together.
  • the static electricity may not be discharged quickly.
  • two array substrates 10 adjacent to each other are provided A second connection line 302 electrically connected to the second conductive terminal 41 of the group electrical test area 40 of each display unit 01.
  • a second connection line 302 is provided between every two adjacent rows of the array substrate 10.
  • a second connection line 302 is provided between any two groups of adjacent array substrates 10.
  • the number of the second connecting wires 302 can be maximized, and static electricity can be discharged more quickly.
  • each display unit 01 includes at least one row of array substrates 10 in the array substrate mother board 1A
  • the display panel mother board may be first cut into a plurality of display units 01, and then cut each display unit 01 into display panels one by one, that is, Stick Cut first, and then Cell Cut. Since each display unit 01 has a group electrical test area 40, the group electrical test area 40 can be ET lighted to determine whether the plurality of array substrates 10 in the display unit 01 have AD defects, that is, the Stick ET method is used to detect each display panel.
  • the display panel motherboard is first cut into a plurality of display units 01.
  • the second connection line 302 electrically connected to the two conductive terminals 41 will be cut, and thus will not affect the ET lighting of each display unit 01.
  • the setting method of the connecting wire 30 in the embodiment of the present disclosure includes but is not limited to the above-mentioned first way and second way.
  • an embodiment of the present disclosure provides a display panel motherboard 2A, including the above-mentioned array substrate motherboard 1A.
  • the type of the display panel motherboard 2A is not limited.
  • the display panel motherboard is a liquid crystal display (Liquid Crystal) (LCD); in other embodiments, the display panel motherboard is A self-luminous display panel, such as an organic electroluminescence display panel (Organic Light-Emitting Diode, OLED for short) or a quantum dot electroluminescence display panel (Quantum Dot Light-Emitting Display, QLED for short).
  • OLED Organic Light-Emitting Diode
  • QLED Quantum Dot Light-Emitting Display
  • the display panel motherboard 2A is a liquid crystal display panel
  • the display panel motherboard 2A includes an array substrate motherboard 1A and a counter substrate substrate motherboard 03 (eg, color filter substrate motherboard), and the array substrate motherboard 1A and The liquid crystal layer 02 between the mother substrate 03 of the cell substrate.
  • the display panel motherboard is a self-luminous display panel
  • the display panel motherboard includes an array substrate motherboard 1A and an encapsulation layer for encapsulating the array substrate motherboard 1A.
  • the connecting wires 30 connect the plurality of array substrates on the array substrate motherboard 1A 10 are electrically connected together, so when static electricity is generated at a certain position, the static electricity can be led out through the connection line 30.
  • the static electricity accumulated at that position will be discharged, and at the same time can be shared through different positions, thereby reducing The static electricity at this position improves the problem of large static electricity accumulation, avoids damage to the product caused by static electricity discharge, and improves the product yield.
  • the embodiments of the present disclosure can reduce the static electricity of the display panel motherboard 2A Accumulation can also reduce the risk of package reliability failure.

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Abstract

一种阵列基板母板（1A），包括多个阵列基板（10）和连接线（30）；多个阵列基板（10）中的每个阵列基板（10）包括电学测试区（20），电学测试区（20）包括第一导电端子（21）；连接线（30）与多个阵列基板（10）的电学测试区（20）的第一导电端子（21）电连接，以将多个阵列基板（10）电连接在一起。

Description

阵列基板母板及显示面板母板
本申请要求于2019年01月04日提交中国专利局、申请号为201910088142、发明名称为“一种阵列基板母板及显示面板母板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板母板及显示面板母板。
背景技术
目前，显示面板母板在制作过程中，常会产生静电积累问题。例如，显示面板母板的制作过程需涉及到显微镜抽检等作业，存在工作人员多次取出、放入以及搬送等操作，而人身体的瞬间静电可达到上万伏，因而在此过程中会产生静电积累问题。又例如，在减薄(slim)工艺或切割(例如Stick Cut，条形切割；Group Cut，单元切割；Cell Cut，个体切割)工艺中，同样存在人员手动搬送、分屏等操作，因而在此过程中也会产生静电积累问题。
由于静电积累过大后，ESD(Electro-Static discharge，静电释放)对显示面板的伤害极大例如会导致保护电路被烧伤或出现短路(Short)问题，从而会导致ET(Electrical Test，电学测试)点灯时出现AD(Abnormal Display，异常显示)不良，影响了显示面板的品质。
发明内容
一方面，本公开的实施例提供一种阵列基板母板，包括：多个阵列基板和连接线。所述多个阵列基板中的每个阵列基板包括电学测试区，所述电学测试区包括第一导电端子；所述连接线与所述多个阵列基板的电学测试区的第一导电端子电连接，以将所述多个阵列基板电连接在一起。
在一些实施例中，所述连接线设置于所述多个阵列基板之间，所述连接线沿所述多个阵列基板排列的行方向或列方向延伸。
在一些实施例中，所述多个阵列基板中的每行阵列基板通过一条所述连接线电连接在一起；和/或，所述多个阵列基板中的每列阵列基板通过一条所述连接线电连接在一起。
在一些实施例中，所述连接线包括第一连接线和第二连接线；所述阵列基板母板划分为多个显示单元，所述多个显示单元中的每个显示单元包括至少两个所述阵列基板；每个所述显示单元包括组电学测试区，所述组电学测试区包括第二导电端子；每个所述显示单元中，每个所述阵列基板的电学测试区的第一导电端子通过所述第一连接线与该显示单元 的组电学测试区的第二导电端子电连接；所述多个显示单元中，各所述显示单元的组电学测试区的第二导电端子通过所述第二连接线电连接在一起。
在一些实施例中，每个所述显示单元包括m行n列个所述阵列基板；其中，m，n为正整数；m小于所述阵列基板母板中所述多个阵列基板排列成的行数，n小于所述阵列基板母板中所述多个阵列基板排列成的列数。
在一些实施例中，每个所述显示单元包括多行多列个所述阵列基板；每个所述显示单元中，位于同一行的各阵列基板的电学测试区的第一导电端子与一条第一连接线电连接；位于同一列的各阵列基板的电学测试区的第一导电端子与一条第一连接线电连接。
在一些实施例中，所述多个显示单元中，位于同一行的各所述显示单元的组电学测试区的第二导电端子与一条第二连接线电连接；和/或，位于同一列的各所述显示单元的组电学测试区的第二导电端子与一条第二连接线电连接。
在一些实施例中，所述显示单元包括至少一列所述阵列基板。
在一些实施例中，所述多个阵列基板中，相邻两行所述阵列基板之间设置一条所述第二连接线，该条第二连接线与每个所述显示单元的组电学测试区的第二导电端子均电连接。
在一些实施例中，每相邻两行所述阵列基板之间设置一条所述第二连接线；或者，任意一组相邻两行所述阵列基板之间设置一条所述第二连接线。
在一些实施例中，所述连接线包括多条子连接线，所述多条子连接线中的每条子连接线的一端与至少一个所述第一导电端子电连接。
在一些实施例中，所述连接线与所述多个阵列基板上的任一导电层同层同材料。
在一些实施例中，所述连接线与所述多个阵列基板的栅电极层或源漏电极层同层同材料。
另一方面，提供一种显示面板母板，包括上述任一实施例所述的阵列基板母板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作 示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1a为根据本公开一些实施例提供的一种阵列基板母板的结构示意图；
图1b为根据本公开一些实施例提供的另一种阵列基板母板的结构示意图；
图1c为根据本公开一些实施例提供的再一种阵列基板母板的结构示意图；
图2a为根据本公开一些实施例提供的又一种阵列基板母板的结构示意图；
图2b为根据本公开一些实施例提供的又一种阵列基板母板的结构示意图；
图2c为根据本公开一些实施例提供的又一种阵列基板母板的结构示意图；
图3a为根据本公开一些实施例提供的又一种阵列基板母板的结构示意图；
图3b为根据本公开一些实施例提供的又一种阵列基板母板的结构示意图；
图4为根据本公开一些实施例提供的一种显示面板母板的结构示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术 语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”和“串接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
“上/上方”、“下/下方”、“行/行方向”以及“列/列方向”等指示的方位或位置关系的术语为基于附图所示的方位或位置关系，仅是为了便于说明本公开的技术方案的简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
例如，在某些情况下，涉及“行方向”的实施例可以在“列方向”的情况下实施等等，相反亦如此。将本公开所述方案进行90°旋转或镜像后亦属本公开要求保护的权利范畴。
本公开实施例提供一种阵列基板母板1A，如图1a和图1b所示，包括：多个阵列基板(Cell，也称Array基板)10；多个阵列基板中的每个阵列基板10包括电学测试区(Electrical test Pad，简称ET Pad)20，电学测试区20包括第一导电端子21(Pin)。本公开实施例附图中用黑点示意电学测试区20的第一导电端子21。
请继续参阅图1a和图1b，阵列基板母板1A还包括：连接线30；连接线30与多个阵列基板10的电学测试区20的第一导电端子21电连接，以将多个阵列基板10电连接在一起。
阵列基板包括对盒区域和位于对盒区域一侧的电学测试区20，对盒区域用于与对盒基板如彩膜基板对盒，电学测试区20用于设置集成电路(Integrated Circuit，简称IC)、阵列基板10上走线的导电端子等。
此外，对于阵列基板母板1A包括的阵列基板10的个数不进行限定，可以根据阵列基板母板1A的尺寸和阵列基板10的尺寸进行相应设置。
此处，对于连接线30在阵列基板母板1A上的设置方式不进行限定，以能将多个阵列基板10电连接在一起为准。由于连接线30将多个阵列基板10电连接在一起，因而连接线30可以形成回路。
在一些实施例中，如图1a和图1b所示，连接线30设置于多个阵列基板10之间，连接线30沿多个阵列基板10排列的行方向或列方向延伸。示例性地，如图1a和图1b所示，阵列基板母板1A上的多个阵列基板10可排列成多行和多列。连接线30设置于多个阵列基板10之间，连接线30沿多个阵列基板10排列的行方向或列方向延伸。也就是说，连接线30设置于相邻两行或相邻两列阵列基板10之间，并且连接线30沿多个阵列基板10排列的行方向或列方向延伸。通过这种设计，可以使不同的阵列基板10的第一导电端子21电连接至相同的连接线30，使得不同的阵列基板10的静第一导电端子21能够通过相同的连接线30实现相互之间的电荷流通，以有利于静电的分散。
对于连接线30，在一些实施例中，如图1a和图1b所示，连接线30为单独的一条，即连接线30包括一条子连接线3011。在另一些实施例中，如图1c所示，每条连接线30包括多条子连接线3011，每条子连接线3011的一端与至少一个第一导电端子21电连接。示例性的，如图1c所示，每条子连接线3011具有多个连接端31，多个连接端31中的每个连接端31与一个第一导电端子21电连接。这样一来，每条连接线30的一端就可以与多个第一导电端子21电连接，从而可以释放多个第一导电端子21上的静电。此外，每条连接线30中的多条子连接线3011可以相互接触，也可以不接触，对此不进行限定。
在此基础上，每个电学测试区20包括多个第一导电端子21，一条子连接线3011的一个连接端31可以与一个电学测试区20中的任一个第一导电端子21电连接；也可以与一个电学测试区20中的两个或两个以上第一导电端子21电连接。
基于上述，在选择与连接线30电连接的第一导电端子21时，可以选择静电导致失效风险较大的第一导电端子21或相对比较重要的第一 导电端子21与连接线30电连接。
在一些实施例中，连接线30与多个阵列基板10上的任一导电层同层同材料。示例性的，该任一导电层可以是具有图案的导电层。例如，连接线30设置于源漏电极层，连接线30与阵列基板10上的数据线同层同材料；再例如，连接线30设置于栅电极层，连接线30与阵列基板10上的栅线同层同材料；又例如，连接线30与阵列基板10上的电极，例如ITO(Indium Tin Oxides，氧化铟锡)电极，同层同材料。这样，在制作阵列基板10上的导电图案的同时可以制作连接线30，从而简化了阵列基板母板1A的制作工艺。
在另一些实施例中，连接线30可以单独制作，不与阵列基板10上的任一导电图案同层制作。此外，可以采用涂布光刻胶、掩膜曝光、显影以及刻蚀工艺形成连接线30。
需要说明的是，显示面板母板制作完成后，需要对显示面板母板中的显示面板进行ET时的点灯作业，以检测每个显示面板的电路、走线等是否正常。由于在电学测试前会将显示面板母板切割成多个显示面板，切割时连接线30会被切断，因而不会影响显示面板ET时的点灯作业。
本公开实施例提供一种阵列基板母板1A，由于阵列基板母板1A包括多个阵列基板10和连接线30，连接线30将阵列基板母板1A上的多个阵列基板10电连接在一起，因而当阵列基板10的某一位置产生静电时，可以通过连接线30将静电导出，静电在流通过程中，该位置处积累的静电会被释放，同时通过不同位置分担，从而减少了该位置处的静电，改善了静电积累较大的问题，避免静电释放导致产品损坏，提高了产品良率。
对显示面板母板中的多个显示面板进行ET点灯时，可以将显示面板母板切割成一个一个的显示面板，对每个显示面板分别进行ET点灯，即采用Cell ET方式检测显示面板；也可以将显示面板母板切割为多组显示面板，对每组显示面板分别进行ET点灯，即采用Group ET方式检测显示面板；当然还可以将显示面板母板切割为多排，对每排显示面板分别进行ET点灯，即采用Stick ET方式检测显示面板。
基于此，在设计连接线30时，可以根据显示面板母板的切割方式和ET点灯方式来设计连接线30的设置方式。
第一种方式：在一些实施例中，如图1a和图1b所示，多个阵列基板10中的每行阵列基板10通过一条连接线30电连接在一起。
在这种情况下，相邻行阵列基板10可以通过一条连接线30电连接在一起；相邻行阵列基板10也可以如图1a和图1b所示通过多条连接线30电连接在一起。
需要说明的是，当每行阵列基板10通过一条连接线30电连接在一起，显示面板母板制作完成后，在切割时，可以先沿行将显示面板母板切割成多排显示面板，再将每排显示面板切割成一个一个的显示面板，也即先进行Stick Cut，再进行Cell Cut。此时，可以对每个显示面板分别进行ET点灯，即采用Cell ET方式检测每个显示面板。
在另一些实施例中，如图1a所示，多个阵列基板10中的每列阵列基板10通过一条连接线30电连接在一起。
在这种情况下，相邻列阵列基板10可以通过一条连接线30电连接在一起；相邻列阵列基板10也可以通过多条连接线30电连接在一起。
需要说明的是，当每列阵列基板10通过一条连接线30电连接在一起，显示面板母板制作完成后，在切割时，可以先沿列将显示面板母板切割成多排显示面板，再将每排显示面板切割成一个一个的显示面板，也即先进行Stick Cut，再进行Cell Cut。此时，可以对每个显示面板分别进行ET点灯，即采用Cell ET方式检测每个显示面板。
考虑到，如图1b所示，若每行阵列基板10通过一条连接线30电连接在一起，每两列阵列基板通过一条连接线30电连接在一起，若沿该两列阵列基板的中间位置切割(如图1b中虚线所示)，则有一列阵列基板由于没有通过连接线30连接在一起，因而该列阵列基板中任一阵列基板10产生的静电便不能通过连接线30释放。同理，若每列阵列基板10通过一条连接线30电连接在一起，每两行或多行阵列基板通过一条连接线30电连接在一起，在切割时存在上述同样的问题。
基于上述，本公开实施例，如图1a所示，每行阵列基板10通过一条连接线30电连接在一起，且每列阵列基板10通过一条连接线30电连接在一起。这样一来，沿任意一行或任意一列切割显示面板母板，都可以使阵列基板母板1A上任一个阵列基板10产生的静电被释放掉。
第二种方式：如图2a、图2b、图2c、图3a和图3b所示，连接线30包括第一连接线301和第二连接线302；阵列基板母板1A划分为多个显示单元01，多个显示单元01中的每个显示单元01包括至少两个阵列基板10，每个显示单元01包括一个组电学测试区40，组电学测试区40包括第二导电端子41，每个显示单元01中每个阵列基板10的电学测试 区20的第一导电端子21通过第一连接线301与该显示单元的组电学测试区40的第二导电端子41电连接；多个显示单元01中，各显示单元01的组电学测试区40的第二导电端子41通过第二连接线302电连接在一起。
其中，对于每个显示单元01包括的阵列基板10的个数不进行限定，可以包括两个阵列基板10；也可以包括两个以上多个阵列基板10。
此处，可以通过一条第一连接线301或多条第一连接线301将每个阵列基板10的电学测试区20的第一导电端子21与组电学测试区40的第二导电端子41电连接。参考图2a和图2b，对于一个显示单元01，图2b中第一连接线301的条数多于图2a第一连接线301的条数，由于图2b中一个显示单元01中每个阵列基板10的电学测试区20的第一导电端子21通过多条第一连接线301与组电学测试区40的第二导电端子41电连接，因而当某一条第一连接线301损坏时，可以通过其它第一连接线301传输信号，从而提高了每个阵列基板10的电学测试区20的第一导电端子21与组电学测试区40的第二导电端子41电连接的可靠性。
需要说明的是，设置组电学测试区40的目的是通过对组电学测试区40进行ET点灯以判断每个显示单元01中多个阵列基板10是否有AD不良，由于对每个显示单元01检测时，可以同时对多个阵列基板10进行检测，因而相对于对多个阵列基板10分别检测，可以提高检测效率。
对于各个显示单元01中多个阵列基板10的排列方式不进行限定，以下提供两种具体的实施方式。
在本公开的一些实施例中，如图2b、图2b和图2c所示，每个显示单元01包括m行n列个阵列基板10；其中，m，n为正整数，m小于阵列基板母板中多个阵列基板10排列成的行数，n小于阵列基板母板中多个阵列基板10排列成的列数。也就是说，每个显示单元01包括多个阵列基板10中的一些阵列基板10，该些阵列基板10排布成m行和n列。例如，如图2b、图2b和图2c所示，每个显示单元01包括4个阵列基板10，该4个阵列基板10排布成2行和2列。
在一些实施例中，各个显示单元01中阵列基板10的排列方式相同。在另一些实施例中。各个显示单元01中阵列基板10的排列方式不完全相同。为了便于切割以及便于设计第二连接线302，以使第二连接线302与多个组电学测试区40的第二导电端子电连接，因而在本公开的一些实施例中，各个显示单元01中阵列基板10的排列方式相同。
此处，对于m，n不进行限定，示例的，m为2，n为2；或者，m 为3，n为2。
在一些实施例中，每个显示单元01包括多行和多列个阵列基板10。如图2b所示，每个显示单元01中，位于同一行的各阵列基板10的电学测试区20的第一导电端子21与一条第一连接线301电连接；且位于同一列的各阵列基板10的电学测试区20的第一导电端子21与一条第一连接线301电连接。这样，如图2b所示，由于每个显示单元01中每排阵列基板10(此处的“排”可以为行，也可以为列)，所包括的电学测试区20的第一导电端子21均通过一条第一连接线301与组电学测试区40的第二导电端子41电连接，因而当某一条第一连接线301损坏时，可以通过其它第一连接线301传输信号，从而提高了每个阵列基板10的电学测试区20的第一导电端子21与组电学测试区40的第二导电端子41电连接的可靠性。
在每个显示单元01包括m行n列个阵列基板10的情况下，对于第二连接线302的设置方式不进行限定，以能与各个组电学测试区40的第二导电端子41电连接为准。
在一些实施例中，如图2a、图2b和图2c所示，位于同一行显示单元01中的组电学测试区40的第二导电端子41与一条第二连接线302电连接。在这种情况下，可以如图2c所示，相邻行显示单元01中的组电学测试区40的第二导电端子41通过一条第二连接线302电连接在一起；也可以如图2a和图2b所示，相邻行显示单元01中的组电学测试区40的第二导电端子41通过两条或两条以上第二连接线302电连接在一起。
在另一些实施例中，如图2a、图2b和图2c所示，位于同一列显示单元01中的组电学测试区40的第二导电端子41与一条第二连接线302电连接。在这种情况下，相邻列显示单元01中的组电学测试区40的第二导电端子41可以通过一条第二连接线302电连接在一起；也可以通过两条或两条以上第二连接线302电连接在一起。
如图2c所示，若位于同一行显示单元01中的组电学测试区40的第二导电端子41与一条第二连接线302电连接，相邻行显示单元01中的组电学测试区40的第二导电端子41通过一条第二连接线302电连接在一起，若沿相邻列显示单元01的中间位置切割(如图2c中虚线所示)，则在一些列中的显示单元01的组电学测试区40由于没有通过连接线30连接在一起，因而这列显示单元01中任一个显示单元01产生的静电便不能通过第二连接线302释放。同理，若位于同一列显示单元01中的组电学测试区40的第二导电端子41与一条第二连接线302电连接，相邻 列显示单元01中的组电学测试区40的第二导电端子41通过一条第二连接线302电连接在一起，在切割时存在上述同样的问题。
基于此，本公开的一些实施例中，位于同一行显示单元01中的组电学测试区40的第二导电端子41与一条第二连接线302电连接，且位于同一列显示单元01中的组电学测试区40的第二导电端子41与一条第二连接线302电连接。
需要说明的是，在显示面板母板制作完成后，可以将显示面板母板先切割成多个显示单元01，再将每个显示单元01切割成一个一个的显示面板，也即先进行Group Cut，再进行Cell Cut。由于每个显示单元01具有一个组电学测试区40，因而可以对组电学测试区40进行ET点灯以判断显示单元01中多个阵列基板10是否有AD不良，即采用Group ET方式检测每个显示面板。
本领域技术人员应该明白，由于在对显示单元01中的组电学测试区40进行ET点灯前，会先将显示面板母板先切割成多个显示单元01，此时与各个组电学测试区40的第二导电端子41电连接的第二连接线302会被切断，因而不会影响各个显示单元01的ET点灯作业。
在本公开的一些实施例中，如图3a和图3b所示，每个显示单元01包括阵列基板母板1A中的至少一列阵列基板10。
此处，每个显示单元01可以包括阵列基板母板1A中的一列阵列基板10；也可以包括阵列基板母板1A中的两列或两列以上阵列基板10。
在每个显示单元01包括阵列基板母板1A中的至少一列阵列基板10的情况下，相邻显示单元01中组电学测试区40的第二导电端子41可以如图3b所示通过一条第二连接线302连接在一起；也可以如图3a所示通过多条第二连接线302连接在一起。
若设置的第二连接线302的数量较少，则静电有可能不能快速释放，基于此，在本公开的一些实施例中，多个阵列基板10中，相邻两行阵列基板10之间设置一条第二连接线302，该条第二连接线302与每个显示单元01的组电学测试区40的第二导电端子41电连接。
示例性地，如图3a所示，每相邻两行阵列基板10之间设置一条第二连接线302。
示例性地，如图3b所示，任意一组相邻两行阵列基板10之间设置一条第二连接线302。这种设置方式，可以使得设置的第二连接线302的数量最多，能更快地释放静电。
需要说明的是，在每个显示单元01包括阵列基板母板1A中的至少一列阵列基板10的情况下，在显示面板母板制作完成后，可以将显示面板母板先切割成多个显示单元01，再将每个显示单元01切割成一个一个的显示面板，也即先进行Stick Cut，再进行Cell Cut。由于每个显示单元01具有一个组电学测试区40，因而可以对组电学测试区40进行ET点灯以判断显示单元01中多个阵列基板10是否有AD不良，即采用Stick ET方式检测每个显示面板。
需要说明的是，由于在对显示单元01中的组电学测试区40进行ET点灯前，会先将显示面板母板先切割成多个显示单元01，此时与各个组电学测试区40的第二导电端子41电连接的第二连接线302会被切断，因而不会影响各个显示单元01的ET点灯。
本公开实施例中连接线30的设置方式包括但不限于上述第一种方式和第二种方式。
如图4所示，本公开实施例提供一种显示面板母板2A，包括上述的阵列基板母板1A。
此处，对于显示面板母板2A的类型不进行限定，在一些实施例中，显示面板母板为液晶显示面板(Liquid Crystal Display，简称LCD)；在另一些实施例中，显示面板母板为自发光显示面板，例如有机电致发光显示面板(Organic Light-Emitting Diode，简称OLED)或量子点电致发光显示面板(Quantum Dot Light-Emitting Display，简称QLED)。
在显示面板母板2A为液晶显示面板的情况下，显示面板母板2A包括阵列基板母板1A和对盒基板母板03(例如彩膜基板母板)，以及设置在阵列基板母板1A和对盒基板母板03之间的液晶层02。在显示面板母板为自发光显示面板的情况下，显示面板母板包括阵列基板母板1A和用于封装阵列基板母板1A的封装层。
本公开实施例提供的显示面板母板2A，由于显示面板母板2A中阵列基板母板1A包括多个阵列基板10和连接线30，连接线30将阵列基板母板1A上的多个阵列基板10电连接在一起，因而当某一位置产生静电时，可以通过连接线30将静电导出，静电在流通过程中，该位置处积累的静电会被释放，同时可通过不同位置分担，从而减少了该位置处的静电，改善了静电积累较大的问题，避免静电释放导致产品损坏，提高了产品良率。
在此基础上，在显示面板母板2A为自发光显示面板的情况下，静电 积累过大，可能会导致封装如Frit封装信赖性失效，本公开实施例由于可以降低显示面板母板2A的静电积累，因而还可以降低封装信赖性失效的风险。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种阵列基板母板，包括：
    多个阵列基板，所述多个阵列基板中的每个阵列基板包括电学测试区，所述电学测试区包括第一导电端子；
    连接线，所述连接线与所述多个阵列基板的电学测试区的第一导电端子电连接，以将所述多个阵列基板电连接在一起。
  2. 根据权利要求1所述的阵列基板母板，其中，所述连接线设置于所述多个阵列基板之间，所述连接线沿所述多个阵列基板排列的行方向或列方向延伸。
  3. 根据权利要求1或2所述的阵列基板母板，其中，所述多个阵列基板中的每行阵列基板通过一条所述连接线电连接在一起；
    和/或，所述多个阵列基板中的每列阵列基板通过一条所述连接线电连接在一起。
  4. 根据权利要求1～3中任一项所述的阵列基板母板，其中，所述连接线包括第一连接线和第二连接线；
    所述阵列基板母板划分为多个显示单元，所述多个显示单元中的每个显示单元包括至少两个所述阵列基板；每个所述显示单元包括组电学测试区，所述组电学测试区包括第二导电端子；
    每个所述显示单元中，每个所述阵列基板的电学测试区的第一导电端子通过所述第一连接线与该显示单元的组电学测试区的第二导电端子电连接；
    所述多个显示单元中，各所述显示单元的组电学测试区的第二导电端子通过所述第二连接线电连接在一起。
  5. 根据权利要求4所述的阵列基板母板，其中，每个所述显示单元包括m行n列个所述阵列基板；
    其中，m，n为正整数；m小于所述阵列基板母板中所述多个阵列基板排列成的行数，n小于所述阵列基板母板中所述多个阵列基板排列成的列数。
  6. 根据权利要求5所述的阵列基板母板，其中，每个所述显示单元包括多行多列个所述阵列基板；
    每个所述显示单元中，位于同一行的各阵列基板的电学测试区的第一导电端子与一条第一连接线电连接；位于同一列的各阵列基板的电学测试区的第一导电端子与一条第一连接线电连接。
  7. 根据权利要求5所述的阵列基板母板，其中，所述多个显示单元中，位于同一行的各所述显示单元的组电学测试区的第二导电端子与一条第二连接线电连接；
    和/或，位于同一列的各所述显示单元的组电学测试区的第二导电端子与一条第二连接线电连接。
  8. 根据权利要求4所述的阵列基板母板，其中，所述显示单元包括至少一列所述阵列基板。
  9. 根据权利要求8所述的阵列基板母板，其中，所述多个阵列基板中，相邻两行所述阵列基板之间设置一条所述第二连接线，该条第二连接线与每个所述显示单元的组电学测试区的第二导电端子均电连接。
  10. 根据权利要求9所述的阵列基板母板，其中，每相邻两行所述阵列基板之间设置一条所述第二连接线；或者，
    任意一组相邻两行所述阵列基板之间设置一条所述第二连接线。
  11. 根据权利要求1～10任一项所述的阵列基板母板，其中，所述连接线包括多条子连接线，所述多条子连接线中的每条子连接线的一端与至少一个所述第一导电端子电连接。
  12. 根据权利要求1～11中任一项所述的阵列基板母板，其中，所述连接线与所述多个阵列基板上的任一导电层同层同材料。
  13. 根据权利要求12所述的阵列基板母板，其中，所述连接线与所述多个阵列基板的栅电极层或源漏电极层同层同材料。
  14. 一种显示面板母板，包括权利要求1～13中任一项所述的阵列基板母板。
PCT/CN2019/128299 2019-01-04 2019-12-25 阵列基板母板及显示面板母板 WO2020140810A1 (zh)

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CN110187575B (zh) 2019-05-28 2020-12-18 昆山国显光电有限公司 阵列基板及阵列基板母板
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CN115633505A (zh) * 2022-10-31 2023-01-20 深圳市华星光电半导体显示技术有限公司 母板、电路板的制作方法以及电路板

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