WO2019179145A1

WO2019179145A1 - Package on package device and packaging method therefor

Info

Publication number: WO2019179145A1
Application number: PCT/CN2018/116159
Authority: WO
Inventors: 常明; 张晓东; 黄京; 刘国文
Original assignee: 华为技术有限公司
Priority date: 2018-03-21
Filing date: 2018-11-19
Publication date: 2019-09-26
Also published as: CN110299328A; CN110299328B

Abstract

A semiconductor device and a packaging method therefor, wherein in the device, the soldering conduction of a first substrate (21) and second substrate (22) is achieved by means of an interconnection structure (25) that is disposed above a first pad (222) of the second substrate (22) and that extends into vias (24) of the first substrate (21), and the vias (24) formed on the first substrate (21) may be achieved by means of a small pitch process such as an electroplating process; therefore, the interconnection structure (25) formed in the vias (24) and used for achieving the soldering of the first substrate (21) and second substrate (22) may achieve small pitch connection, which is capable of meeting requirements of smaller pitch process capabilities. Therefore, a smaller pitch electrical connection may be achieved by means of the interconnection structure (25) that is disposed above the first pad (222) of the second substrate (22) and that extends into the vias (24) of the first substrate (21), which is beneficial in increasing the packaging density of package on package devices.

Description

Stacked package device and packaging method thereof

The present application claims priority to Chinese Patent Application No. 201101233595.3, entitled "A Stacked Package Device and Its Packaging Method", filed on March 21, 2018, the entire contents of which are incorporated herein by reference. In the application.

Technical field

The present application relates to the field of semiconductor device manufacturing technologies, and in particular, to a stacked package device and a packaging method thereof.

Background technique

As the size of electronic devices is reduced, high integration density can be achieved by stacking a plurality of chips in one semiconductor package assembly or stacking a plurality of individual semiconductor package components. Recently, a package on package (POP) has been introduced for mobile electronic device applications and the like. The so-called POP is a stacked package in which a logical package component and a memory package component are stacked. With POP technology, different types of semiconductor chips can be included in one semiconductor device.

With the development of POP technology towards high-density input and output pins, the distance between pins is getting smaller and smaller, and the package thickness is getting thinner. How to further increase the package density of packaged devices and reduce the packaging cost has become the industry facing A big problem.

Summary of the invention

In view of this, the present application provides a stacked package device and a packaging method thereof to further increase the package density of the packaged package device and reduce the package cost.

In order to solve the above technical problem, the present application adopts the following technical solutions:

A first aspect of the present application provides a semiconductor device comprising:

a first substrate and a second substrate disposed on the first substrate;

The first substrate and the second substrate each include an opposite first surface and a second surface;

The first substrate is provided with a through hole penetrating the first surface and the second surface of the first substrate, and the first surface of the second substrate is provided with a first pad, the through hole and the first solder Pad relative setting;

The device further includes an interconnect structure for connecting the first substrate and the second substrate, the interconnect structure being fixed on the first pad and being squeezed and filled in the through hole.

The semiconductor device provided by the first aspect of the present application realizes the connection between the first substrate and the second substrate by an interconnection structure fixed on the first pad of the second substrate and being squeezed and filled in the through hole of the first substrate Turn on. The via hole for forming the first substrate may be realized by a small pitch process, such as an electroplating process, and therefore, an interconnect structure formed in the via hole for realizing the connection of the first substrate and the second substrate may be realized. Smaller pitch connections for smaller pitch process capability requirements. Therefore, the semiconductor device is fixed on the first pad of the second substrate, and the interconnect structure squeezed and filled in the through hole of the first substrate can realize a smaller pitch and a short distance between the first substrate and the second substrate. The electrical connection facilitates the packaging density of the stacked package device. In addition, the packaging process of the stacked package device is simple and low in cost, thereby contributing to reducing the packaging cost of the stacked package device.

In conjunction with the first aspect of the present application, in a first possible implementation, a metal layer is formed on a surface of the through hole, and the metal layer is electrically connected to an electronic device on the first substrate.

In conjunction with the first aspect of the present application and the first possible implementation manner thereof, in a second possible implementation, the device further includes a cavity structure disposed on the second surface of the first substrate, The cavity structure includes a cavity structure wall disposed on the second surface of the first substrate and a cavity space defined by the cavity structure wall;

A first chip is further disposed on the first surface of the second substrate, and the first chip is received by the cavity space.

In the second possible implementation manner, the cavity structure disposed on the second surface of the first substrate can play a certain supporting role for the first substrate, thereby enhancing the overall rigidity of the first substrate, and thus The substrate having no cavity structure is not provided, and the overall thickness of the first substrate can be relatively thinned, thereby achieving the effect of reducing the thickness of the device.

In conjunction with the first aspect of the present application and any of the foregoing possible implementation manners, in a third possible implementation manner, the interconnect structure has a filling height in the through hole of at least 30% of a through hole depth .

In this third possible implementation, the soldering stability between the first substrate and the second substrate can be improved.

In conjunction with the first aspect of the present application and any of the above possible implementations, in a fourth possible implementation, the interconnect structure is a rivet structure. This implementation can increase the bonding force between the first substrate and the second substrate, and enhance the stable reliability at both soldering positions.

In conjunction with the first aspect of the present application and any of the above possible implementations, in a fifth possible implementation, the interconnect structure is formed from a conductive bonding material capable of being cured.

In a sixth possible implementation manner of the first aspect of the present application, in a sixth possible implementation, the conductive bonding material is a conductive adhesive. This implementation simplifies the packaging process.

In conjunction with the first aspect of the present application and any of the foregoing possible implementations, in a seventh possible implementation, the first surface of the second substrate is further provided with a solder resist layer, the solder resist layer Located around the first pad. This implementation can prevent the cured shaped conductive bonding material from overflowing the first pad.

In a seventh possible implementation manner of the first aspect of the present application, in an eighth possible implementation manner, the solder resist layer is a solder resist layer defining structure or a non-solder resist layer defining structure.

In conjunction with the first aspect of the present application and any of the foregoing possible implementations, in a ninth possible implementation, the device further includes a second pad disposed on the second surface of the second substrate The second pad is for electrical connection with an external circuit.

In conjunction with the first aspect of the present application and any of the foregoing possible implementation manners, in the tenth possible implementation manner, the device further includes:

a third substrate disposed above the first surface of the first substrate; electrically connected between the third substrate and the first substrate;

a second chip disposed above the third substrate, the second chip being electrically connected to a surface of the third substrate.

A second aspect of the present application provides a method of packaging a semiconductor device, including:

Providing a first substrate and a second substrate, each of the first substrate and the second substrate includes an opposite first surface and a second surface, and a first pad is disposed on the first surface of the second substrate;

Forming a through hole penetrating the first surface and the second surface of the first substrate up and down at a position corresponding to the first pad;

Assembling the first substrate and the second substrate together, and positioning the through hole opposite to the first pad;

Forming an interconnect structure for connecting the first substrate and the second substrate over the first pad, the interconnect structure is fixed on the first pad, and is pressed and filled in the Said inside the hole.

The method provided by the second aspect of the present application can realize the connection of the first substrate and the second substrate by the interconnection structure fixed on the first pad of the second substrate and being squeezed and filled in the through hole of the first substrate. through. The via hole for forming the first substrate may be realized by a small pitch process, such as an electroplating process, and therefore, an interconnect structure formed in the via hole for realizing the connection of the first substrate and the second substrate may be realized. Smaller pitch connections for smaller pitch process capability requirements. Therefore, the method is fixed on the first pad of the second substrate, and the interconnect structure squeezed and filled in the through hole of the first substrate can realize smaller pitch and short distance of the first substrate and the second substrate. Sexual connection, which helps to increase the packaging density of stacked package devices. In addition, the packaging process of the stacked package device is simple and low in cost, thereby contributing to reducing the packaging cost of the stacked package device.

In conjunction with the second aspect of the present application, in a first possible implementation, after the forming the via hole, forming the interconnect structure, the method further includes:

A metal layer is formed on a surface of the via hole for electrically connecting to an electronic device on the first substrate.

In conjunction with the second aspect of the present application and any of the foregoing possible implementation manners, in the second possible implementation manner, before the forming the through hole, the method further includes:

Forming a cavity structure on the second surface of the first substrate, the cavity structure including a cavity structure wall disposed on the second surface of the first substrate and an empty space surrounded by the cavity structure wall a cavity space for accommodating a first chip disposed on the first surface of the second substrate;

Forming a through hole penetrating through the first surface and the second surface of the first substrate at a position corresponding to the first pad, specifically:

A through hole penetrating the first surface and the second surface of the first substrate and the cavity structure wall at a position corresponding to the first pad is formed at a position corresponding to the first pad.

In conjunction with the second aspect of the present application and any of the foregoing possible implementation manners, in the third possible implementation, before the assembling the first substrate and the second substrate together, the method further includes:

Coating the first bonding pad with a conductive bonding material capable of curing;

Forming an interconnection structure for connecting the first substrate and the second substrate over the first pad, specifically including:

While the first substrate and the second substrate are assembled, the curable molding conductive bonding material coated on the first bonding pad is caused to flow into the through hole;

The electrically conductive bonding material capable of being cured is cured to form an interconnect structure for connecting the first substrate and the second substrate.

With reference to the second aspect of the present application and any of the foregoing possible implementation manners, in the fourth possible implementation manner, the assembling the first substrate and the second substrate together include:

The first substrate and the second substrate are bonded together by a surface mount process.

With reference to the second aspect of the present application and any of the foregoing possible implementation manners, in a fifth possible implementation manner, the method further includes:

Forming a second pad on the second surface of the second substrate, the second pad being for electrically connecting to an external circuit.

With reference to the second aspect of the present application and any of the foregoing possible implementation manners, in the sixth possible implementation manner, before the assembling, the method further includes:

Forming a third substrate on the first surface of the first substrate; electrically connecting the third substrate and the first substrate;

A second chip is formed over the third substrate, the second chip being electrically connected to a surface of the third substrate.

Compared with the prior art, the present application has the following beneficial effects:

According to the above technical solution, in the stacked package device provided by the embodiment of the present application, the interconnect structure fixed on the first pad of the second substrate and squeezed into the through hole of the first substrate realizes the first The connection between the substrate and the second substrate is conducted. The via hole for forming the first substrate may be realized by a small pitch process, such as an electroplating process, and therefore, an interconnect structure formed in the via hole for realizing the connection of the first substrate and the second substrate may be realized. Smaller pitch connections for smaller pitch process capability requirements. Therefore, the interconnect structure provided by the embodiment of the present application by being fixed on the first pad of the second substrate and being squeezed and filled in the through hole of the first substrate enables a smaller pitch of the first substrate and the second substrate and Short-distance electrical connections help to increase the package density of stacked package devices.

In addition, in the embodiment of the present application, the packaging process of the stacked package device is simple and low in cost, thereby facilitating reduction of packaging cost of the stacked package device.

DRAWINGS

1 is a schematic cross-sectional view of a conventional stacked package device in the prior art;

2 is a schematic cross-sectional structural view of a stacked package device according to an embodiment of the present application;

3 is a schematic cross-sectional structural view of another stacked package device according to an embodiment of the present application;

4 is a schematic flow chart of a packaging method of a stacked package device according to an embodiment of the present application;

5A1 to FIG. 5E are schematic cross-sectional structural diagrams of a series of processes for packaging a stacked package device according to an embodiment of the present application;

FIG. 6 is a cross-sectional view showing a device formed by a packaging method of another stacked package device according to an embodiment of the present application.

detailed description

In the field of semiconductor device packaging, a cross-sectional structure of a stacked package device is shown in FIG. In FIG. 1, the stacked package device adopts a dual substrate bonding solder structure, in which the system level integrated chip 11 (SOC chip) is located between the upper substrate 12 and the lower substrate 13, so, in design In the structure of the device, a certain distance between the upper and

lower substrates

12 and 13 is ensured, and an electrical connection between the upper and

lower substrates

12 and 13 can be realized. In FIG. 1, in order to achieve electrical connection of the upper and

lower substrates

12 and 13, the upper and

lower substrates

12 and 13 are welded together using a copper core ball 14.

At present, the minimum pitch that can be achieved by the copper-core ball process is 270 μm, which results in a lower package density of the stacked package structure. With the development of electronic device technology, a smaller pitch process is required to achieve soldering of the upper and lower substrates to increase the package density of the stacked package devices.

Further, since the SOC chip 11 is placed between the upper and

lower substrates

12 and 13, and the SOC chip 11 is soldered on the lower substrate 13 by a flip chip process, when the upper and

lower substrates

12 and 13 are welded together, it is necessary to A certain gap space is left between the upper and

lower substrates

12 and 13 to accommodate the SOC chip 11. If the size of the gap space is constant, if the upper and

lower substrates

12 and 13 are welded together by using a small copper core ball, the solder joint is likely to occur, resulting in between the upper and

lower substrates

12 and 13. Poor soldering.

Therefore, the following defects exist in the stacked package device shown in FIG. 1:

First, the minimum pitch of the copper core ball process for realizing the upper and lower substrates is large, resulting in a low package density of the stacked package structure;

Secondly, the copper core ball is used to realize the connection between the upper and lower substrates. If the size of the copper core ball is improperly selected, the defects of poor soldering of the upper and lower substrates are prone to occur.

In order to solve the defects of the stacked package device shown in FIG. 1 , the embodiment of the present application provides a new stacked package device. In the stacked package device, soldering conduction of the first substrate and the second substrate is achieved by an interconnect structure fixed to the first pad of the second substrate and squeezed into the via hole of the first substrate. The via hole for forming the first substrate may be realized by a small pitch process, such as an electroplating process, and therefore, an interconnect structure formed in the via hole for realizing soldering of the first substrate and the second substrate may be realized Smaller pitch connections for smaller pitch process capability requirements. Therefore, the interconnect structure provided by the embodiment of the present application is fixed on the first pad of the second substrate and is pressed and filled in the through hole of the first substrate to achieve a smaller pitch between the first substrate and the second substrate. The electrical connection facilitates the packaging density of the stacked package device.

In addition, in the stacked package device provided by the embodiment of the present application, the interconnect structure for connecting the first substrate and the second substrate is directly formed on the first pad of the second substrate, and is pressed and filled into the first substrate. Within the via, therefore, the interconnect structure does not suffer from the presence of a solder joint defect in the copper core ball process. Therefore, compared with the prior art, the copper core ball process is used to realize the connection of the upper and lower substrates, the interconnect structure can increase the bonding force between the first substrate and the second substrate, and the solder joint stability reliability can be enhanced.

The structure of the stacked package device provided by the embodiment of the present application is described in detail below with reference to the accompanying drawings.

Referring to FIG. 2, the stacked package device provided by the embodiment of the present application includes the following structure:

a first substrate 21, a second substrate 22 and a cavity structure 23;

The first substrate 21 and the second substrate 22 each include an opposite first surface and a second surface. The first surface of the second substrate 22 is provided with a first chip 221 and a first pad 222; as an example, the first The chip 221 can be a system level integrated chip (SOC chip);

The cavity structure 23 includes a cavity structure wall 231 disposed on the second surface of the first substrate 21 and a cavity space 232 surrounded by the cavity structure wall 231;

The second substrate 22 is disposed below the cavity structure 23, and the first pad 222 is located below the cavity structure wall 231. Moreover, in order to be able to reduce the entire device size of the stacked package device, the first chip 221 can be accommodated by the cavity space 232. Thus, in the embodiment of the present application, the first chip 221 can be disposed opposite to the cavity space 232, and The space of the cavity space 232 can satisfy the requirement of accommodating the first chip 221.

The stacked package device further includes a through hole 24 penetrating through the first surface and the second surface of the first substrate 21 and the cavity structure wall 231, and the through hole 24 is disposed opposite to the first pad 222.

In addition, in order to achieve electrical connection between the first substrate 21 and the second substrate 22 and adhesion of the two substrates, the stacked package device further includes a first solder pad 222 and an extension filled into the through hole 24 . Interconnect structure 25.

In addition, a metal layer 26 may be formed on the surface of the through hole 24 for electrically connecting with the electronic device on the first substrate 21. As an example, the metal layer can be a copper metal layer formed using an electroplating process.

It should be noted that, in the embodiment of the present application, the number of the first pads 222 may be multiple, and correspondingly, the number of the through holes 24 formed above the first pads 222 may be plural. More specifically, there is a one-to-one correspondence between the through holes 24 and the first pads 222. Thus, one through hole 24 corresponds to a first pad 222. As such, a plurality of interconnect structures 25 may be included in the stacked package device provided by the embodiments of the present application. In the embodiment of the present application, the interconnect structure 25 can be formed in various ways.

As an example, the interconnect structure 25 can be formed from a conductive bonding material that is capable of being cured. As an example, the electrically conductive bonding material capable of being cured can be a conductive paste. As an example, the conductive paste may be at least one of a solder paste, a copper paste, and a silver paste. When the interconnect structure 25 is formed by using a conductive paste, the specific implementation may be as follows: In the embodiment of the present application, after the cavity structure 23 is formed on the second surface of the first substrate 21, a surface mount process may be employed. The first substrate 21 and the second substrate 22 are connected together. Before the two substrates are mounted, the first bonding pads 222 of the second substrate 22 are coated with a conductive paste, and then, when the two substrates are mounted, a certain pressure is applied, and the conductive adhesive is pressed into the through holes 24 by the pressure drop. The conductive paste extruded into the vias 24 is then cured into the interconnect structure 25 by reflow or baking.

When the embodiment of the present application adopts the above implementation manner to form the interconnect structure 25, the opening of the through hole 24 may be smaller than the size of the first pad 222. Therefore, the interconnect structure 25 may have a rivet structure with a large bottom area and a small top area. . More specifically, the elongated portion of the interconnect structure 25 in the rivet configuration is located within the through hole 24. The interconnect structure 25 in the rivet structure can increase the bonding force between the first substrate 21 and the second substrate 22, enhancing the stable reliability at both soldering positions. Moreover, in the embodiment of the present application, the height of the interconnect structure 25 extending into the through hole 24 is related to the amount of the conductive paste that is applied over the first pad 222. The more the amount of the conductive paste extends to the through hole. The higher the height within 24, the more stable and secure the soldering properties of interconnect structure 25. As an optional embodiment of the present application, in order to ensure the soldering stability between the first substrate 21 and the second substrate 22, the height of the interconnect structure 25 extending into the through hole 24 is at least 30% of the total depth of the through hole 24. As a more specific alternative embodiment, the height of the interconnect structure 25 extending into the vias 24 is the same as the total depth of the vias 24. As another specific embodiment, when the amount of the conductive paste is sufficiently large, the conductive paste may fill the entire through hole and overflow onto the first surface of the first substrate 21 under the action of the pressing force, and formed in this case. The interconnect structure 25 may extend onto the first surface of the first substrate 21, which may further improve soldering stability between the first substrate 21 and the second substrate 22.

It can be seen from the above that in the embodiment of the present application, the connection between the first substrate 21 and the second substrate 22 is realized by the above-mentioned interconnection structure 25 instead of the copper core ball 14 shown in FIG. There are no defects in the solder joints present in the copper core ball process. Therefore, the stacked package device in the embodiment of the present application can solve the defect of poor soldering existing in the two substrates in the existing stacked package device.

In addition, in the embodiment of the present application, the through hole 24 can be realized by a small pitch process, such as an electroplating process, and therefore, the interconnect structure formed in the through hole for realizing the soldering of the first substrate and the second substrate can be Achieve smaller pitch connections to meet the needs of smaller pitch process capabilities. Therefore, the interconnecting node provided on the first pad fixed to the second substrate and squeezed and filled in the through hole of the first substrate provided by the embodiment of the present application can realize a smaller pitch electrical connection, thereby facilitating the lifting. The package density of stacked package devices. As an example, the manufacturing process parameters of the via hole 24 are as follows: a pitch of 230 μm, a hole diameter of 100 μm, and a hole disk of 200 μm.

Further, the connection of the first substrate 21 and the second substrate 22 is realized by the interconnection structure 25 formed in the through hole 24, and there is no risk of string soldering.

In addition, in the embodiment of the present application, the cavity structure 23 disposed on the second surface of the first substrate 21 can play a certain supporting role for the first substrate 21, thereby enhancing the overall rigidity of the first substrate 21, and thus, the phase The overall thickness of the first substrate 21 can be relatively thinner than the substrate not provided with the cavity structure, thereby achieving the effect of reducing the thickness of the device. As an example, in the embodiment of the present application, the thickness of the first substrate 21 may be reduced by at least 60 μm compared to the substrate not provided with the cavity structure.

In addition, since the cavity structure 23 can enhance the overall rigidity of the first substrate 21, the processing of the packaging process of the stacked package device in the embodiment of the present application is convenient and easy, and the package yield is improved.

It should be noted that, as an extension of the embodiment of the present application, the cavity structure 23 in the stacked package device shown in FIG. 2 may not be included in the stacked package device provided by the embodiment of the present application. As such, in this embodiment, the effect of the cavity structure 23 is not correspondingly provided, but the embodiment is formed over the first pad 222 of the second substrate 22 and filled to the first substrate 21. The interconnect structure in the via hole 24 can achieve a smaller pitch and a short distance electrical connection of the first substrate 21 and the second substrate 22, thereby facilitating the packaging density of the stacked package device.

As a specific example of the present application, the first substrate 21 may be a copper clad laminate. More specifically, the copper clad laminate may be a double-sided copper clad laminate, and in order to fabricate a fine circuit layer, a certain surface may be separately disposed on the surface of the copper clad laminate. As an example, the ultra-thin copper foil may have a thickness of 3 μm.

As another specific embodiment of the present application, the second substrate 22 can be fabricated by a 3-layer ETS (Embbeded Trace Substrate) process.

As another specific embodiment of the present application, the first pad 222 may be a metal pad, a metal solder ball, or other structure for achieving electrical connection. In the embodiment of the present application, the first pad 222 is exemplified by a metal pad.

In order to prevent the conductive bonding material capable of being cured from overflowing the first bonding pad 222, as another embodiment of the embodiment of the present application, as shown in FIG. 2, a solder resist layer 223 is disposed on the first surface of the second substrate 22. The solder resist layer 223 is located around the first pad 222. More specifically, the solder resist layer may be a Solder-Mask Defined (SMD) structure or a Non-Solder-Mask Defined (NSMD) structure. Wherein, the solder mask opening of the SMD structure is smaller than the metal pad. The board designer defines the shape code, location, and nominal dimensions of the pads; the actual size of the pad openings is controlled by the solder mask creator. The solder mask is typically an imageable liquid photoresist.

The metal pad of the NSMD structure is smaller than the solder mask opening. On the NSMD pads of the surface wiring board, a portion of the printed circuit leads will be wetted by the solder.

As a further embodiment of the present application, a second pad 224 for electrically connecting to an external circuit may be disposed on the second surface of the second substrate 22. The specific structure of the second pad 224 may be a metal pad. , metal solder balls or other electrical connection structures.

As another embodiment of the present application, as shown in FIG. 3, the stacked package device provided in this embodiment may further include:

a third substrate 31 disposed above the first surface of the first substrate 21;

a second chip 32 disposed on the third substrate 31. The second chip 32 is electrically connected to the surface of the third substrate 31. The third substrate 31 and the first substrate 21 are electrically connected by the third pad 33. connection.

As an example, the second chip 32 may be a memory chip. The third pad 33 can be a metal solder ball, a metal pad or other electrical connection structure.

Further, in order to protect internal components of the stacked package device, the stacked package device structure shown in FIG. 3 may further include a molding body 34 that wraps the second chip 32 and the third substrate 31.

The above is a specific structure of the stacked package device provided by the embodiment of the present application. Based on the specific structure of the stacked package device, the embodiment of the present application further provides a specific implementation manner of the package method of the stacked package device.

Referring to FIG. 4 to FIG. 5D , the method for packaging a stacked package device provided by the embodiment of the present application includes the following steps:

S401: providing a first substrate 21 and a second substrate 22, each of the first substrate 21 and the second substrate 22 includes an opposite first surface and a second surface, and the first surface of the second substrate 22 is provided with a first chip 221 and First pad 222.

As shown in FIG. 5A1, the first substrate 21 is internally provided with a blind hole 211, and the second surface is provided with a line 212. The blind vias 211 can achieve electrical connection of the first surface and the second surface of the first substrate 21.

In the embodiment of the present application, the first substrate 21 may be a double-sided copper-clad board, and in order to make a fine line on the surface of the first substrate 21, the two surfaces of the first substrate 21 may be provided with a certain thickness of ultra-thin. Copper foil.

In the embodiment of the present application, a schematic cross-sectional view of the second substrate 22 is as shown in FIG. 5A2, which may include opposing first and second surfaces, and a first chip 221 is disposed on the first surface of the second substrate 22. And a first pad 222. In addition, a solder resist layer 223 may be disposed on the first surface of the second substrate 22 , and the solder resist layer 223 is located around the first pad 222 .

The second substrate 22 can be fabricated using a 3-layer ETS process. In the embodiment of the present application, after the 3-layer ETS process is completed, the first chip 221 and the first pad 222 are formed on the first surface of the second substrate 22.

As an example, in the embodiment of the present application, the first chip 221 may be formed on the first surface of the second substrate 22 by a flip chip process. The specific process can be as follows:

The wafer formed with the plurality of first chips is ground and thinned, and cut into a single first chip, and the first chip is bonded on the first surface of the second substrate 22 by using a die bonder, and then The underfill of a chip is filled with an under fill, thereby forming a first chip 221 on the first surface of the second substrate 22.

In the embodiment of the present application, the first chip 221 may be a SOC chip. Additionally, the first pad 222 can be a metal pad, a metal solder ball, or other electrical connection structure.

S402: forming a cavity structure 23 on the second surface of the first substrate 21, the cavity structure 23 including a cavity structure wall 231 disposed on the second surface of the first substrate 21 and an empty space surrounded by the cavity structure wall 231 Cavity space 232.

As an example, a photosensitive dielectric material may be coated on the second surface of the first substrate 21, and then the cavity structure 23 may be formed on the second surface of the first substrate 21 by a photolithography etching process.

Further, as another example, a copper clad laminate or a semi-cured resin sheet (PrePreg, PPG) may be formed on the second surface of the first substrate 21, and then formed by mechanically milling a copper clad or a semi-cured resin sheet. Cavity structure 23.

A schematic diagram of the corresponding cross-sectional structure performed in this step is shown in FIG. 5B.

S403: forming a through hole 24 penetrating the first surface and the second surface of the first substrate 21 and the cavity structure wall 231 up and down at a position corresponding to the first pad 222.

It should be noted that, in the embodiment of the present application, the position corresponding to the first pad 222 is a position that is opposite to the first pad 222 when the first substrate and the second substrate are placed in parallel with each other.

This step may specifically be a mechanical drilling process or a plated through hole process in which the first surface and the second surface of the first substrate 21 and the through hole of the cavity structure wall 231 are formed at positions corresponding to the first pad 222. twenty four.

It should be noted that, in the embodiment of the present application, a metal layer 26 may be formed on the surface of the via hole 24 to achieve electrical connection with the electronic device on the first substrate 21.

A schematic diagram of the corresponding cross-sectional structure performed in this step is shown in FIG. 5C.

S404: coating the conductive paste 51 on the first pad 222.

In this step, the conductive paste 51 may be coated on the first pad 222 that needs to be soldered to the first substrate by a dispensing process.

In this step, the conductive paste may be at least one of a solder paste, a copper paste, and a silver paste. In order to secure the soldering stability between the first substrate 21 and the second substrate 22, the amount of the conductive paste 51 to be coated is as large as possible.

A schematic diagram of the corresponding cross-sectional structure performed in this step is shown in FIG. 5D.

S405: The first substrate 21 and the second substrate 22 formed with the cavity structure 23 are assembled together, and the first chip 221 is received by the cavity space 232, and the through hole 24 is disposed opposite to the first pad 222, and At the same time of assembly, a certain pressure is applied to press the conductive paste 51 coated on the first pad 222 into the through hole 24.

As an example, this step may employ a surface mount process to mount the first substrate 21 and the second substrate 22 formed with the cavity structure 23 together.

While the first substrate 21 and the second substrate are bonded together, a certain pressure is applied to cause the conductive paste 51 coated on the first pad 222 to be squeezed into the through hole 24.

A schematic diagram of the corresponding cross-sectional structure performed in this step is shown in FIG. 5E.

S406: curing the conductive paste 51 such that the conductive paste 51 forms an interconnect structure 25 extending into the through hole 24 above the first pad 333.

The conductive paste 51 is cured by a reflow or baking process such that the conductive paste 51 forms an interconnect structure 25 extending into the via hole 24 over the first pad 333. The interconnect structure 25 is used to achieve electrical connection between the first substrate 21 and the second substrate 22 and adhesion of the two substrates.

As an optional embodiment of the present application, in order to ensure the soldering stability between the first substrate 21 and the second substrate 22, the height of the interconnect structure 25 extending into the through hole 24 is at least 30% of the total depth of the through hole 24. .

It should be noted that, in the embodiment of the present application, S402 to S403 are processes on the first substrate 21, and S404 is a process on the second substrate 22, because the first substrate 21 and the second substrate 22 are not assembled yet. Therefore, the embodiment of the present application does not limit the execution order of S402 to S403 and S404. Specifically, as shown in FIG. 4, S402 to S403 may be executed first, and then S404 may be executed. S404 may be executed first, and then S402 to S403 may be executed, or may be performed simultaneously.

The above is a specific implementation manner of the packaging method of the stacked package device provided by the embodiment of the present application. In this specific implementation, a conductive paste is used as a material for forming an interconnect structure as an example. In fact, in the embodiment of the present application, the material forming the interconnect structure is not limited to the conductive paste, and it may also be other conductive bonding materials capable of curing. Accordingly, when other interconnective structures capable of curing molding are used to form the interconnect structure, the corresponding manner in which the interconnect structure is formed may also vary accordingly.

For example, as an extended embodiment of the embodiment of the present application, the conductive paste may not be coated on the first pad before the two substrates are assembled, but after the two are assembled, the conductive paste capable of curing can be introduced into the through hole 24. The junction material is then passed through a corresponding process such that the curable shaped electrically conductive bonding material forms an interconnect structure over the first pad and extending into the vias 24.

In addition, as another extended embodiment of the embodiment of the present application, when the conductive adhesive is used as the conductive adhesive material capable of curing, the conductive paste may not be coated on the first bonding pad before the two substrates are assembled, but After the two are assembled, the conductive paste is introduced into the through hole 24, and then the conductive paste is cured by corresponding reflow or baking, so that the conductive paste forms an interconnection above the first pad and extending into the through hole 24. structure.

In addition, as an optional embodiment of the present application, on the basis of the foregoing embodiment, before S405, the following steps are further included:

Forming a third substrate 31 on the first surface of the first substrate 21;

A second chip 32 is formed above the third substrate 31, and the second chip 32 is electrically connected to a surface of the third substrate 31, and the third substrate 31 and the first substrate 21 pass between The third pad 33 is electrically connected.

In addition, in order to protect internal components of the stacked package device, the above packaging method may further include:

The second chip 32 and the third substrate 31 are molded with a molding compound to form a molding body 34 that encloses the second chip 32 and the third substrate 31.

The structure of the stacked package device finally formed by the specific implementation is shown in FIG. 6, and the corresponding structural diagram is shown in FIG. 3.

The above is a specific embodiment of the present application.

Claims

A semiconductor device characterized by comprising:

a first substrate and a second substrate disposed on the first substrate;

The first substrate and the second substrate each include an opposite first surface and a second surface;

The first substrate is provided with a through hole penetrating the first surface and the second surface of the first substrate, and the first surface of the second substrate is provided with a first pad, the through hole and the first solder Pad relative setting;

The device further includes an interconnect structure for connecting the first substrate and the second substrate, the interconnect structure being fixed on the first pad and being squeezed and filled in the through hole.
The device according to claim 1, wherein a metal layer is formed on a surface of the via hole, and the metal layer is electrically connected to an electronic device on the first substrate.
The device according to claim 1 or 2, wherein the device further comprises a cavity structure disposed on the second surface of the first substrate, the cavity structure comprising a first substrate disposed on the first substrate a cavity structure wall on the two surfaces and a cavity space surrounded by the cavity structure wall;

A first chip is further disposed on the first surface of the second substrate, and the first chip is received by the cavity space.
A device according to any one of claims 1 to 3, wherein the interconnection structure has a filling height in the through hole of at least 30% of the depth of the through hole.
A device according to any one of claims 1 to 4, wherein the interconnect structure is a rivet structure.
A device according to any one of claims 1 to 5, wherein the interconnect structure is formed of a conductive bonding material capable of being cured.
The device according to any one of claims 6 to 4, wherein the conductive bonding material is a conductive paste.
The device according to any one of claims 1 to 7, wherein a solder resist layer is further disposed on the first surface of the second substrate, and the solder resist layer is located around the first pad.
The device according to claim 8, wherein the solder resist layer is a solder resist layer defining structure or a non-solder resist layer defining structure.
The device according to any one of claims 1 to 9, wherein the device further comprises a second pad disposed on the second surface of the second substrate, the second pad being used for The external circuit is electrically connected.
The device according to any one of claims 1 to 10, wherein the device further comprises:

a third substrate disposed above the first surface of the first substrate; electrically connected between the third substrate and the first substrate;

a second chip disposed above the third substrate, the second chip being electrically connected to a surface of the third substrate.
A method of packaging a semiconductor device, comprising:

Providing a first substrate and a second substrate, each of the first substrate and the second substrate includes an opposite first surface and a second surface, and a first pad is disposed on the first surface of the second substrate;

Forming a through hole penetrating the first surface and the second surface of the first substrate up and down at a position corresponding to the first pad;

Assembling the first substrate and the second substrate together, and positioning the through hole opposite to the first pad;

Forming an interconnect structure for connecting the first substrate and the second substrate over the first pad, the interconnect structure is fixed on the first pad, and is pressed and filled in the Said inside the hole.
The method according to claim 12, further comprising: after forming the via hole, forming the interconnect structure, further comprising:

A metal layer is formed on a surface of the via hole for electrically connecting to an electronic device on the first substrate.
The method according to claim 12 or 13, wherein before forming the through hole, the method further comprises:

Forming a cavity structure on the second surface of the first substrate, the cavity structure including a cavity structure wall disposed on the second surface of the first substrate and an empty space surrounded by the cavity structure wall a cavity space for accommodating a first chip disposed on the first surface of the second substrate;

Forming a through hole penetrating through the first surface and the second surface of the first substrate at a position corresponding to the first pad, specifically:

A through hole penetrating the first surface and the second surface of the first substrate and the cavity structure wall at a position corresponding to the first pad is formed at a position corresponding to the first pad.
The method according to any one of claims 12 to 14, wherein before the assembling the first substrate and the second substrate together, the method further comprises:

Coating the first bonding pad with a conductive bonding material capable of curing;

Forming an interconnection structure for connecting the first substrate and the second substrate over the first pad, specifically including:

While the first substrate and the second substrate are assembled, the curable molding conductive bonding material coated on the first bonding pad is caused to flow into the through hole;

The electrically conductive bonding material capable of being cured is cured to form an interconnect structure for connecting the first substrate and the second substrate.
The method according to any one of claims 12 to 15, wherein the assembling the first substrate and the second substrate together comprises:

The first substrate and the second substrate are bonded together by a surface mount process.
The method according to any one of claims 12 to 16, wherein the method further comprises:

Forming a second pad on the second surface of the second substrate, the second pad being for electrically connecting to an external circuit.
The method according to any one of claims 12-17, further comprising: before assembling, further comprising:

Forming a third substrate on the first surface of the first substrate; electrically connecting the third substrate and the first substrate;

A second chip is formed over the third substrate, the second chip being electrically connected to a surface of the third substrate.