CN110299328A - A kind of stack packaged device and its packaging method - Google Patents
A kind of stack packaged device and its packaging method Download PDFInfo
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- CN110299328A CN110299328A CN201810233595.3A CN201810233595A CN110299328A CN 110299328 A CN110299328 A CN 110299328A CN 201810233595 A CN201810233595 A CN 201810233595A CN 110299328 A CN110299328 A CN 110299328A
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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- H01L2924/151—Die mounting substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract
本申请公开了一种半导体器件及其封装方法。在该器件中，通过设置于第二基板的第一焊垫上方的、且延伸至第一基板的通孔内的互连结构实现第一基板和第二基板的焊接导通。用于形成该第一基板上的通孔可以通过较小间距工艺实现，例如电镀工艺，因此，形成于该通孔内的、用于实现第一基板和第二基板焊接的互连结构可以实现较小间距连接，能够满足更小间距工艺能力需求。因此，本申请实施例提供的通过形成于第二基板的第一焊垫上方且延伸至第一基板的通孔内的互连结构能够实现更小间距的电性连接，从而有利于提升堆叠封装器件的封装密度。
The application discloses a semiconductor device and a packaging method thereof. In the device, soldering conduction between the first substrate and the second substrate is realized through an interconnection structure disposed above the first pad of the second substrate and extending into the through hole of the first substrate. The through holes used to form the first substrate can be realized by a small-pitch process, such as an electroplating process. Therefore, the interconnection structure formed in the through holes and used to realize the welding of the first substrate and the second substrate can be realized. Smaller-pitch connections can meet the requirements of smaller-pitch process capabilities. Therefore, the interconnection structure provided by the embodiment of the present application formed above the first pad of the second substrate and extending into the through hole of the first substrate can realize electrical connection with a smaller pitch, thereby facilitating the improvement of stacked packaging. The packing density of the device.
Description
Technical field
This application involves semiconductor device processing technology field more particularly to a kind of stack packaged device and its encapsulation sides
Method.
Background technique
It, can be by stacking multiple chips or heap in a semiconductor package as the size of electronic equipment reduces
Multiple individual semiconductor packages are folded to realize high density of integration.Recently, drawn for mobile electronic device application etc.
Into stacked package technology (Package on Package, POP).So-called POP is by logic package assembling and memory package
The stacked package of stack of components setting.It can include different types of semiconductor in a semiconductor devices using POP technology
Chip.
As POP technology is towards the development in high density input and output pin direction, the distance between pin is also smaller and smaller, envelope
Dress thickness is more and more thinner, how further to promote the packaging density of stack packaged device, reduction packaging cost is faced as industry
A great problem.
Summary of the invention
In view of this, being stacked and being sealed with further promotion this application provides a kind of stack packaged device and its packaging method
It fills the packaging density of device and reduces packaging cost.
In order to solve the above-mentioned technical problem, the application adopts the technical scheme that
The first aspect of the application provides a kind of semiconductor devices, comprising:
First substrate and the second substrate being set on the first substrate；
The first substrate and the second substrate include opposite first surface and second surface；
The through-hole through first substrate first surface and second surface, the second substrate are provided on the first substrate
First surface on be provided with the first weld pad, the through-hole is oppositely arranged with first weld pad；
The device further includes the interconnection structure for connecting the first substrate and the second substrate, the mutual connection
Structure is fixed on first weld pad, and is extruded and is filled in the through-hole.
The semiconductor devices that the first aspect of the application provides, by being fixed on the first weld pad of the second substrate, and by
Extrusion packing realizes the connection conducting of first substrate and the second substrate in the interconnection structure in the through-hole of first substrate.It is used to form
Through-hole on the first substrate can be realized by smaller spacing technique, such as therefore electroplating technology is formed in the through-hole
, the connection of smaller spacing may be implemented for realizing the interconnection structure that first substrate is connected with the second substrate, can satisfy smaller
Spacing technological ability demand.Therefore, the semiconductor devices is by being fixed on the first weld pad of the second substrate, and is extruded filling
It can be realized first substrate and the smaller spacing of the second substrate and short-range electricity in the interconnection structure in the through-hole of first substrate
Property connection, thus be conducive to promoted stack packaged device packaging density.In addition, the packaging technology process of the stack packaged device
Simply, low in cost, thus advantageously reduce the packaging cost of stack packaged device.
In conjunction with the application's in a first aspect, in the first possible implementation, being formed on the surface of the through-hole
Electronic device on metal layer, the metal layer and the first substrate is electrically connected.
In conjunction in the first aspect of the application and its first possible implementation, in second of possible implementation
In, the device further includes the cavity structure being set on the first substrate second surface, and the cavity structure includes setting
In the cavity structure wall on the first substrate second surface and the void space surrounded by the cavity structure wall；
The first chip is additionally provided on the first surface of the second substrate, first chip is by the void space institute
It accommodates.
In this second possible implementation, being set to cavity structure on first substrate second surface can be the
One substrate plays certain supporting role, to enhance the integral rigidity of first substrate, therefore, compared to being not provided with cavity knot
The integral thickness of the substrate of structure, first substrate can be thinned relatively, to achieve the effect that reduce thickness of detector.
In conjunction in the first aspect of the application and its any of the above-described possible implementation, in the third possible realization side
In formula, packed height of the interconnection structure in the through-hole is at least the 30% of via depth.
In the third possible implementation, the welding stability between first substrate and the second substrate can be improved.
In conjunction in the first aspect of the application and its any of the above-described possible implementation, the 4th kind of possible realization side
In formula, the interconnection structure is rivet arrangement.The implementation can increase the binding force between first substrate and the second substrate, increase
Reliability at both strong welding position.
In conjunction in the first aspect of the application and its any of the above-described possible implementation, the 5th kind of possible realization side
In formula, the interconnection structure is formed by the conductive bonding material for capableing of curing molding.
In the 5th kind of possible implementation in conjunction with the first aspect of the application, in the 6th kind of possible implementation
In, the conductive bonding material is conducting resinl.The implementation can simplify packaging technology.
In conjunction in the first aspect of the application and its any of the above-described possible implementation, the 7th kind of possible realization side
In formula, solder mask is additionally provided on the first surface of the second substrate, the solder mask is located at around first weld pad.
The implementation can prevent the conductive bonding material of curing molding from overflowing the first weld pad.
In the 7th kind of possible implementation in conjunction with the first aspect of the application, in the 8th kind of possible implementation
In, the solder mask is solder mask limiting structure or non-solder mask limiting structure.
In conjunction in the first aspect of the application and its any of the above-described possible implementation, the 9th kind of possible realization side
In formula, the device further includes the second weld pad being arranged on the second surface of the second substrate, and second weld pad is used for
It is electrically connected with external circuit.
In conjunction in the first aspect of the application and its any of the above-described possible implementation, the tenth kind of possible realization side
In formula, the device further include:
The third substrate being set to above the first surface of the first substrate；The third substrate and the first substrate
Between be electrically connected；
The second chip being set to above the third substrate, second chip are electrically connected on third substrate surface.
The second aspect of the application provides a kind of packaging method of semiconductor devices, comprising:
First substrate and the second substrate are provided, the first substrate and the second substrate include opposite first surface
And second surface, the first weld pad is provided on the first surface of the second substrate；
The first surface and second for running through the first substrate up and down is formed in position corresponding with first weld pad
The through-hole on surface；
First substrate and the second substrate are fitted together, and are oppositely arranged the through-hole with first weld pad；
The interconnection structure for connecting the first substrate and the second substrate is formed in the top of first weld pad,
The interconnection structure is fixed on first weld pad, and is extruded and is filled in the through-hole.
It can be by being fixed on the first weld pad of the second substrate by the method that the application second aspect provides, and be squeezed
The interconnection structure being filled in the through-hole of first substrate is pressed to realize the connection conducting of first substrate and the second substrate.It is used to form this
Through-hole on first substrate can be realized by smaller spacing technique, such as electroplating technology, therefore, be formed in it is in the through-hole,
Smaller spacing connection may be implemented for realizing the interconnection structure that first substrate is connected with the second substrate, can satisfy smaller spacing
Technological ability demand.Therefore, this method is by being fixed on the first weld pad of the second substrate, and is extruded and is filled in first substrate
Through-hole in interconnection structure can be realized first substrate and the smaller spacing of the second substrate and short-range electric connection, thus
Be conducive to be promoted the packaging density of stack packaged device.In addition, the packaging technology process of the stack packaged device is simple, it is at low cost
It is honest and clean, thus advantageously reduce the packaging cost of stack packaged device.
In conjunction with the second aspect of the application, in the first possible implementation, after forming the through-hole, formed
Before the interconnection structure, further includes:
Metal layer is formed on the surface of the through-hole, the metal layer is used for and the electronic device on the first substrate
It is electrically connected.
In conjunction in the second aspect of the application and its any of the above-described possible implementation, second of possible realization side
In formula, before forming the through-hole, further includes:
Cavity structure is formed on the second surface of the first substrate, the cavity structure includes being set to described first
Cavity structure wall on second substrate surface and the void space surrounded by the cavity structure wall；The void space is used for
Accommodate the first chip being set on the second substrate first surface；
It is described position corresponding with first weld pad formed up and down through the first substrate first surface and
The through-hole of second surface, specifically:
The first surface and second for running through the first substrate up and down is formed in position corresponding with first weld pad
The through-hole of surface and the cavity structure wall.
In this second possible implementation, being set to cavity structure on first substrate second surface can be the
One substrate plays certain supporting role, to enhance the integral rigidity of first substrate, therefore, compared to being not provided with cavity knot
The integral thickness of the substrate of structure, first substrate can be thinned relatively, to achieve the effect that reduce thickness of detector.
In conjunction in the second aspect of the application and its any of the above-described possible implementation, in the third possible realization side
In formula, it is described first substrate and the second substrate are fitted together before, further includes:
The conductive bonding material of curing molding is capable of in coating on first weld pad；
The top in first weld pad forms the interconnection for connecting the first substrate and the second substrate
Structure specifically includes:
While first substrate and the second substrate assemble, extrusion coated on first weld pad being capable of curing molding
Conductive bonding material, enable its flow into the through-hole；
It is capable of the conductive bonding material of curing molding described in solidification, to be formed for connecting the first substrate and described
The interconnection structure of the second substrate.
In conjunction in the second aspect of the application and its any of the above-described possible implementation, the 4th kind of possible realization side
It is described to fit together first substrate and the second substrate in formula, it specifically includes:
First substrate and the second substrate fitting are fitted together using surface mount process.
In conjunction in the second aspect of the application and its any of the above-described possible implementation, the 5th kind of possible realization side
In formula, the method also includes:
The second weld pad is formed on the second surface of the second substrate, second weld pad with external circuit for being electrically connected
It connects.
In conjunction in the second aspect of the application and its any of the above-described possible implementation, the 6th kind of possible realization side
In formula, before assembly, further includes:
Third substrate is formed on the first surface of the first substrate；Between the third substrate and the first substrate
It is electrically connected；
The second chip is formed in the top of the third substrate, second chip is electrically connected to the table of the third substrate
On face.
Compared to the prior art, the application has the advantages that
Based on above technical scheme it is found that in stack packaged device provided by the embodiments of the present application, by being fixed on
On first weld pad of two substrates, and it is extruded the interconnection structure in the through-hole for being filled in first substrate and realizes first substrate and second
The connection of substrate is connected.The through-hole being used to form on the first substrate can be realized by smaller spacing technique, such as galvanizer
Skill, therefore, be formed in it is in the through-hole, may be implemented for realizing the interconnection structure that first substrate is connected with the second substrate it is smaller
Spacing connection, can satisfy smaller spacing technological ability demand.Therefore, provided by the embodiments of the present application by being fixed on the second base
On first weld pad of plate, and it is extruded the interconnection structure in the through-hole for being filled in first substrate and can be realized first substrate and second
The smaller spacing of substrate and short-range electric connection, to be conducive to be promoted the packaging density of stack packaged device.
In addition, in the embodiment of the present application, the packaging technology process of the stack packaged device is simple, it is low in cost, thus
Advantageously reduce the packaging cost of stack packaged device.
Detailed description of the invention
Fig. 1 is a kind of existing the schematic diagram of the section structure of stack packaged device in this field；
Fig. 2 is a kind of the schematic diagram of the section structure of stack packaged device provided by the embodiments of the present application；
Fig. 3 is the schematic diagram of the section structure of another stack packaged device provided by the embodiments of the present application；
Fig. 4 is a kind of packaging method flow diagram of stack packaged device provided by the embodiments of the present application；
Fig. 5 A1 to Fig. 5 E is a kind of a series of processing procedures pair of packaging method of stack packaged device provided by the embodiments of the present application
The schematic diagram of the section structure answered；
Fig. 6 is that the section for the device that the packaging method of another stack packaged device provided by the embodiments of the present application is formed shows
It is intended to.
Specific embodiment
In semiconductor packages field, a kind of cross-section structure of stack packaged device is as shown in Figure 1.In Fig. 1, stack
Packaging is bonded welding structure using biradical plate, in the biradical plate fitting welding structure, system-level 11 (SOC of integrated chip
Chip) between upper substrate 12 and lower substrate 13, so, when designing the device architecture, it is ensured that upper and lower substrates 12 and 13
Between there is a certain distance, and can be realized the electric connection between upper and lower substrates 12 and 13.In Fig. 1, in order to realize
The electric connection of upper and lower substrates 12 and 13 is welded together upper and lower substrates 12 and 13 using copper caryosphere 14.
Currently, the attainable minimum spacing of copper caryosphere technique institute is 270 μm, which leads to the encapsulation of stack package structure
Density is lower.With the development of electronic device technology, the technique of smaller spacing is needed to realize the welding of upper and lower substrates, to mention
Rise the packaging density of stack packaged device.
In addition, because placing SOC chip 11 between upper and lower substrates 12 and 13, and SOC chip 11 is welded using reverse installation process
On lower substrate 13, therefore, when welding together upper and lower substrates 12 and 13, need to stay between upper and lower substrates 12 and 13
There is certain gap space to accommodate SOC chip 11.If in the case where gap space size is constant, according to too small copper caryosphere
If upper and lower substrates 12 and 13 are welded together, then it can be easy to happen rosin joint, caused between upper and lower substrates 12 and 13 not
Good welding.
Therefore, it is had the following deficiencies: in stack packaged device shown in Fig. 1
The first, the minimum spacing for realizing the copper caryosphere technique of upper and lower substrates is larger, leads to the envelope of stack package structure
It is lower to fill density；
The second, the connection that upper and lower substrates are realized using copper caryosphere, if the size selection of copper caryosphere is improper, be easy to happen,
The defect of lower substrate failure welding.
In order to solve defect existing for stack packaged device shown in FIG. 1, the embodiment of the present application provides the embodiment of the present application
A kind of new stack packaged device.In the stack packaged device, by being fixed on the first weld pad of the second substrate, and by
Extrusion packing realizes the welding conducting of first substrate and the second substrate in the interconnection structure in the through-hole of first substrate.It is used to form
Through-hole on the first substrate can be realized by smaller spacing technique, such as therefore electroplating technology is formed in the through-hole
, smaller spacing may be implemented with the interconnection structure that the second substrate is welded for realizing first substrate connect, can satisfy smaller
Spacing technological ability demand.Therefore, provided by the embodiments of the present application by being fixed on the first weld pad of the second substrate, and be squeezed
The interconnection structure that pressure is filled in the through-hole of first substrate can be realized first substrate and the electrical property of the smaller spacing of the second substrate connects
It connects, to be conducive to be promoted the packaging density of stack packaged device.
In addition, in the embodiment of the present application, the packaging technology process of the stack packaged device is simple, it is low in cost, thus
Advantageously reduce the packaging cost of stack packaged device.
In addition, in stack packaged device provided by the embodiments of the present application, for connecting first substrate and the second substrate
Interconnection structure is formed directly on the first weld pad of the second substrate, and is extruded in the through-hole of filling first substrate, thus, this is mutually
Linking structure is not in rosin joint defect existing for copper caryosphere technique.Therefore, it is realized compared to the prior art using copper caryosphere technique
The scheme of the connection of upper and lower base plate, the interconnection structure can increase the binding force between first substrate and the second substrate, Er Qiehui
Enhance solder joint reliability.
The structure of stack packaged device provided by the embodiments of the present application is described in detail with reference to the accompanying drawing.
Fig. 2 is referred to, stack packaged device provided by the embodiments of the present application includes with flowering structure:
First substrate 21, the second substrate 22 and cavity structure 23；
The first substrate 21 and the second substrate 22 include opposite first surface and second surface, the second substrate 22
The first chip 221 and the first weld pad 222 are provided on first surface；As an example, the first chip 221 can be system-level collection
At chip (SOC chip)；
The cavity structure 23 includes the cavity structure wall 231 that is set on 21 second surface of first substrate and by this
The void space 232 that cavity structure wall 231 surrounds；
The second substrate 22 is set to the lower section of cavity structure 23, and the first weld pad 222 is located at the cavity structure wall 231
Lower section.Moreover, in order to reduce the entire device size of stack packaged device, the first chip 221 can be by void space 232
It is accommodated, in this way, in the embodiment of the present application, the first chip 221 can be oppositely arranged with void space 232, and void space
232 space size can satisfy the requirement for accommodating the first chip 221.
The stack packaged device further includes the first surface and second surface and cavity knot for running through first substrate 21 up and down
The through-hole 24 of structure wall 231, the through-hole 24 are oppositely arranged with the first weld pad 222.
In addition, in order to realize the electric connection of first substrate 21 and the second substrate 22 and the bonding of the two substrates, the heap
Folded packaging further includes being fixed on 222 top of the first weld pad and extending to be extruded filling to the interconnection structure 25 in through-hole 24.
In addition, can also be formed with metal layer 26 on the surface of the through-hole 24, which is used for and first substrate 21
Electronic device be electrically connected.As an example, the metal layer can be the copper metal layer formed using electroplating technology.
It is to be appreciated that in the embodiment of the present application, the quantity of the first weld pad 222 can be it is multiple, correspondingly, be formed in
The quantity of the through-hole 24 of first weld pad, 222 top may be multiple.More specifically, through-hole 24 and the first weld pad 222 it
Between be it is one-to-one, in this way, corresponding first weld pad 222 of a through-hole 24.In this way, in heap provided by the embodiments of the present application
It may include multiple interconnection structures 25 in folded packaging.In the embodiment of the present application, interconnection structure 25 can use a variety of sides
Formula is formed.
As an example, interconnection structure 25 can be formed by the conductive bonding material for capableing of curing molding.As an example, the energy
The conductive bonding material of enough curing moldings can be conducting resinl.As an example, the conducting resinl can be in tin cream, copper cream and silver paste
At least one.When forming interconnection structure 25 using conducting resinl, specific implementation be can be such that in the embodiment of the present application
In, on the second surface that cavity structure 23 is formed in first substrate 21 after, can be using surface mount process by first substrate
21 and the second substrate 22 link together.Before carrying out two substrates attachment, coated on the first weld pad 222 of the second substrate 22
Conducting resinl applies certain pressure, is squeezed into through-hole 24 by the pressure drop conducting resinl, then then when two substrates mount
The conducting resinl for being squeezed into through-hole 24 is solidified into interconnection structure 25 by flowing back or toasting.
When the embodiment of the present application using above-mentioned implementation to form interconnection structure 25 when, the opening of through-hole 24 can be less than
The size of first weld pad 222, therefore, interconnection structure 25 can be big in bottom area, the small rivet arrangement of topside area.More specifically
Say that the elongated portion in the interconnection structure 25 of rivet arrangement is located in through-hole 24 in ground.This can in the interconnection structure 25 of rivet arrangement
Reliability to increase the binding force between first substrate 21 and the second substrate 22, at both enhancings welding position.Moreover,
In the embodiment of the present application, the height which extends in through-hole 24 is coated in leading for 222 top of the first weld pad with point
The amount of electric glue is related, and the amount of conducting resinl is more, and the height extended in through-hole 24 is higher, and the welding performance of interconnection structure 25 is more steady
It is fixed secured.As the alternative embodiment of the application, in order to guarantee that the welding between first substrate 21 and the second substrate 22 is stablized
Property, the height that interconnection structure 25 extends in through-hole 24 is at least the 30% of 24 total depth of through-hole, as a more specific optional reality
Example is applied, it is identical as 24 total depth of through-hole that interconnection structure 25 extends to the height in through-hole 24.As another specific embodiment, when leading
When the amount of electric glue is enough, under the action of extruding force, conducting resinl can be full of entire through-hole, and spill into first substrate 21
On first surface, the interconnection structure 25 formed in this case can be extended on the first surface of first substrate 21, the interconnection
Structure 25 can be further improved the welding stability between first substrate 21 and the second substrate 22.
From the foregoing, it will be observed that in the embodiment of the present application, substituting copper caryosphere shown in FIG. 1 by interconnection structure 25 described above
14 realize the connection between first substrate 21 and the second substrate 22, and there is no rosin joints existing for copper caryosphere technique for the interconnection structure 25
Defect.Therefore, the two substrates that the stack packaged device in the embodiment of the present application is able to solve in existing stack packaged device are deposited
Failure welding defect,
In addition, in the embodiment of the present application, through-hole 24 can be realized by smaller spacing technique, such as electroplating technology, because
This, being formed in interconnection structure in the through-hole, welding for realizing first substrate and the second substrate may be implemented smaller spacing
Connection, can satisfy smaller spacing technological ability demand.Therefore, provided by the embodiments of the present application by being fixed on the second substrate
On first weld pad, and it is extruded the mutual connection in the through-hole for being filled in first substrate and can be realized the electric connection of smaller spacing,
To be conducive to promote the packaging density of stack packaged device.As an example, the manufacture craft parameter of through-hole 24 is as follows: spacing is
230 μm, aperture is 100 μm, and porose disc is 200 μm.
In addition, the connection of first substrate 21 and the second substrate 22 is realized using the interconnection structure 25 being formed in through-hole 24,
There is no string tin risks.
In addition, in the embodiment of the present application, being set to cavity structure 23 on 21 second surface of first substrate can be the
One substrate 21 plays certain supporting role, thus enhance the integral rigidity of first substrate 21, it is therefore, free compared to not set
The integral thickness of the substrate of cavity configuration, first substrate 21 can be thinned relatively, to achieve the effect that reduce thickness of detector.As
Example, in the embodiment of the present application, compared to the substrate for being not provided with cavity structure, the thickness of first substrate 21 can be thinned to
It is 60 μm few.
In addition, since the integral rigidity of first substrate 21 can be enhanced in cavity structure 23, in the embodiment of the present application
Stack packaged device encapsulation process working process it is more convenient be easy, encapsulation yield get a promotion.
It, can also in stack packaged device provided by the embodiments of the present application it is to be appreciated that the extension as the embodiment of the present application
Not include the cavity structure 23 in above-mentioned stack packaged device shown in Fig. 2.In this way, in this embodiment, correspondingly just not
With effect brought by cavity structure 23, still, the embodiment is by being formed in above the first weld pad 222 of the second substrate 22
And filling to the interconnection structure in the through-hole 24 of first substrate 21 can be realized first substrate 21 and the smaller spacing of the second substrate 22
And short-range electric connection, to be conducive to be promoted the packaging density of stack packaged device.
As the specific example of the application, first substrate 21 can be copper-clad plate, more specifically, the copper-clad plate can be
Double face copper, and in order to make fine-line layer, it can be respectively arranged on the surface of the copper-clad plate certain thickness
Extra thin copper foil, as an example, the thickness of the extra thin copper foil can be 3 μm.
As the another specific embodiment of the application, the second substrate 22 can using 3 layers of ETS (route embedded substrate,
Emmbeded Trace Substrate) technique completes.
As the still another embodiment of the application, the first weld pad 222 can be metal pad, metal soldered ball or other
For realizing the structure of electrical connection.In the embodiment of the present application, the first weld pad 222 illustrates by taking metal pad as an example.
The conductive bonding material for capableing of curing molding in order to prevent overflows the first weld pad 222, as the embodiment of the present application
Still another embodiment, as shown in Fig. 2, solder mask 223 is provided on the first surface of the second substrate 22, the solder mask 223
Around the first weld pad 222.More more specifically, the solder mask can for solder mask limit (Solder-Mask Defined,
SMD) structure or non-solder mask limit (Non-Solder-Mask Defined, NSMD) structure.Wherein, the solder mask of SMD structure
Opening is less than metal pad.Circuit board designer defines the norminal size of shape code, position and pad；The reality of bonding pad opening
Size is controlled by solder mask producer.Liquid photosensitive glue can be generally imaged in solder mask.
The metal pad of NSMD structure is open less than solder mask.On the NSMD pad of surface layer wiring circuit, printing electricity
A part of line conductor will will receive the infiltration of scolding tin.
As the still another embodiment of the application, be also provided on the second surface of the second substrate 22 for it is outer
Second weld pad 224 of portion's circuit electrical connection, the specific structure of second weld pad 224 can for metal pad, metal soldered ball or
Other electric connection structures.
As the still another embodiment of the application, as shown in figure 3, stack packaged device provided in this embodiment is above-mentioned
On the basis of structure shown in Fig. 2, can also include:
The third substrate 31 being set to above the first surface of first substrate 21；
It is set to the second chip 32 of 31 top of third substrate, which is electrically connected to the table of third substrate 31
On face, it is electrically connected between the third substrate 31 and the first substrate 21 by third weld pad 33.
As an example, second chip 32 can be storage chip (Memory).Third weld pad 33 can for metal soldered ball,
Metal pad or other electric connection structures.
In addition, the internal part in order to protect stack packaged device, stack packaged device structure shown in Fig. 3 can also be wrapped
Include the plastic-sealed body 34 of package the second chip 32 and third substrate 31.
The above are the specific structures of stack packaged device provided by the embodiments of the present application.Tool based on the stack packaged device
Body structure, the embodiment of the present application also provides the specific embodiments of the packaging method of the stack packaged device.
Refer to Fig. 4 to Fig. 5 D, the packaging method of stack packaged device provided by the embodiments of the present application the following steps are included:
S401: providing first substrate 21 and the second substrate 22, and first substrate 21 and the second substrate 22 include opposite the
One surface and second surface are provided with the first chip 221 and the first weld pad 222 on the first surface of the second substrate 22.
As shown in Fig. 5 A1, first substrate 21 is internally provided with blind hole 211, and route 212 is provided on second surface.It is blind
The electrical connection of 21 first surface and second surface of first substrate may be implemented in hole 211.
In the embodiment of the present application, first substrate 21 can be double face copper, and in order in the table of first substrate 21
Fine-line is made on face, is also provided with certain thickness extra thin copper foil on two surfaces of the first substrate 21.
In the embodiment of the present application, the structural profile illustration of the second substrate 22 may include opposite as shown in Fig. 5 A2
First surface and second surface, and the first chip 221 and the first weld pad are provided on the first surface of the second substrate 22
222.In addition, being also provided with solder mask 223 on the first surface of the second substrate 22, which is located at the first weldering
Around pad 222.
The second substrate 22 can be completed using 3 layers of ETS technique.In the embodiment of the present application, 3 layers of ETS work are being used
After skill completes, the first chip 221 and the first weld pad 222 are formed on the first surface of the second substrate 22.
As an example, in the embodiment of the present application, the first chip 221 can be formed in the second base using flip chip mounting process
On the first surface of plate 22.The detailed process can be such that
The grinding wafer for being formed with more the first chips is thinned, and is cut into many independent first chips, is utilized
First chip is bonded on the first surface of the second substrate 22 by die Bonder, then in the underfill bottom filler of the first chip
(under fill) forms the first chip 221 to realize on the first surface of the second substrate 22.
In the embodiment of the present application, the first chip 221 can be SOC chip.In addition, the first weld pad 222 can be metal
Pad, metal soldered ball or other electric connection structures.
S402: forming cavity structure 23 on the second surface of first substrate 21, and cavity structure 23 includes being set to first
Cavity structure wall 231 on 21 second surface of substrate and the void space 232 surrounded by cavity structure wall 231.
As an example, one layer of photosensitive dielectric material can be coated on the second surface of first substrate 21, is then passed through
Lithographic etch process forms cavity structure 23 on the second surface of first substrate 21.
In addition, as another example, a copper-clad plate or semi-solid preparation can also be formed on the second surface of first substrate 21
Resin sheet (PrePreg, PPG) then forms cavity structure 23 in such a way that power auger mills copper-clad plate or semi-solid preparation resin sheet.
It is as shown in Figure 5 B that the step has executed corresponding the schematic diagram of the section structure.
S403: it is formed up and down in position corresponding with the first weld pad 222 through the first surface of first substrate 21 and the
The through-hole 24 of two surfaces and cavity structure wall 231.
It is to be appreciated that in the embodiment of the present application, position corresponding with the first weld pad 222 is when first substrate and second
When substrate is placed in parallel relatively up and down, with the position opposing upper and lower of the first weld pad 222.
This step can be specially to be that the first weld pad 222 is corresponding using mechanical drilling process or electroplating ventilating hole technique
Position at formed up and down through first substrate 21 first surface and second surface and cavity structure wall 231 through-hole 24.
It is to be appreciated that in the embodiment of the present application, one layer of metal layer 26 can also be formed, on the surface of through-hole 24 with reality
Now with the electrical connection of the electronic device on first substrate 21.
It is as shown in Figure 5 C that the step has executed corresponding the schematic diagram of the section structure.
S404: conducting resinl 51 is coated on the first weld pad 222.
This step can be coated on needing the first weld pad 222 be connected with first substrate welding conductive using gluing process
Glue 51.
In this step, which can be at least one of tin cream, copper cream and silver paste.In order to guarantee first substrate
The amount of welding stability between 21 and the second substrate 22, the conducting resinl 51 of coating is more as much as possible.
It is as shown in Figure 5 D that the step has executed corresponding the schematic diagram of the section structure.
S405: the first substrate 21 for being formed with cavity structure 23 and the second substrate 22 are fitted together, and make the first core
Piece 221 is accommodated by void space 232, and through-hole 24 is oppositely arranged with the first weld pad 222, and while assembling, is applied certain
Pressure, will be coated in the first weld pad 222 on conducting resinl 51 squeeze flow into through-hole 24 in.
As an example, this step can will be formed with the first of cavity structure 23 using surface mount process (Mounting)
Substrate 21 and the fitting of the second substrate 22 fit together.
While first substrate 21 and the second substrate fit together, apply certain pressure, makes to be coated in the first weldering
Conducting resinl 51 on pad 222 is squeezed into through-hole 24.
The step has executed corresponding the schematic diagram of the section structure as shown in fig. 5e.
S406: Curing conductive adhesive 51 extends in through-hole 24 so that conducting resinl 51 be made to be formed in the top of the first weld pad 333
Interconnection structure 25.
Using reflux or baking process Curing conductive adhesive 51, to make conducting resinl 51 in the upper rectangular of the first weld pad 333
At the interconnection structure 25 extended in through-hole 24.The interconnection structure 25 for realizing first substrate 21 and the second substrate 22 electrical property
Connection and the bonding of the two substrates.
As the alternative embodiment of the application, in order to guarantee that the welding between first substrate 21 and the second substrate 22 is stablized
Property, the height that interconnection structure 25 extends in through-hole 24 is at least the 30% of 24 total depth of through-hole.
The step has executed corresponding the schematic diagram of the section structure as shown in fig. 5e.
It is to be appreciated that in the embodiment of the present application, S402 to S403 is the processing procedure on first substrate 21, S404 is
Processing procedure on two substrates 22, because first substrate 21 and the second substrate 22 fit together not yet, therefore, the embodiment of the present application is not
Limit S402 to S403 and S404 executes sequence.Specifically, as shown in figure 4, S402 to S403 can be first carried out, then execute
S404 can also first carry out S404, then execute S402 to S403, also may be performed simultaneously.
The above are the specific implementations of the packaging method of stack packaged device provided by the embodiments of the present application.It is specific at this
In implementation, using conducting resinl as the material for forming interconnection structure for illustrate.In fact, in the embodiment of the present application, shape
It is not limited to conducting resinl at the material of interconnection structure, can also be other conductive bonding materials for capableing of curing molding.Correspondingly,
It is corresponding to form the specific of interconnection structure when forming interconnection structure using other conductive bonding materials for capableing of curing molding
Mode can also correspondingly change.
For example, one as the embodiment of the present application extends embodiment, it can be before two substrates assembling, not in the first weld pad
Upper coating conducting resinl, but after the two assembling, the conductive bonding material for capableing of curing molding is introduced in Xiang Tongkong 24, then
By corresponding process the conductive bonding material of the curing molding is formed again to be located above the first weld pad and extend to
Interconnection structure in through-hole 24.
In addition, another extension embodiment as the embodiment of the present application, when using conducting resinl as capableing of curing molding
When conductive bonding material, conducting resinl can also not be coated on the first weld pad, but is assembled in the two before two substrates assembling
Later, conducting resinl is introduced in Xiang Tongkong 24, then again by flowing back or being toasted by conductive adhesive curing, so that this is led accordingly
Electric glue, which is formed, to be located above the first weld pad and extends to the interconnection structure in through-hole 24.
In addition, the alternative embodiment as the application before S405, further includes on the basis of the above embodiments
Following steps:
Third substrate 31 is formed on the first surface of first substrate 21；
The second chip 32 is formed in the top of the third substrate 31, second chip 32 is electrically connected to the third base
On the surface of plate 31, it is electrically connected between the third substrate 31 and the first substrate 21 by third weld pad 33.
In addition, the internal part in order to protect stack packaged device, above-mentioned packaging method can further include:
The second chip 32 and third substrate 31 are molded using plastic packaging material, to form the second chip 32 of package and the
The plastic-sealed body 34 of three substrates 31.
The structure of the finally formed stack packaged device of the specific implementation as shown in fig. 6, corresponding structure diagram such as
Shown in Fig. 3.
The above are the specific embodiments of the application.
Claims (18)
1. a kind of semiconductor devices characterized by comprising
First substrate and the second substrate being set on the first substrate；
The first substrate and the second substrate include opposite first surface and second surface；
It is provided with the through-hole through first substrate first surface and second surface on the first substrate, the of the second substrate
The first weld pad is provided on one surface, the through-hole is oppositely arranged with first weld pad；
The device further includes the interconnection structure for connecting the first substrate and the second substrate, and the interconnection structure is solid
It is scheduled on first weld pad, and is extruded and is filled in the through-hole.
2. device according to claim 1, which is characterized in that be formed with metal layer, the gold on the surface of the through-hole
The electronic device belonged on layer and the first substrate is electrically connected.
3. device according to claim 1 or 2, which is characterized in that the device further includes being set to the first substrate
Cavity structure on second surface, the cavity structure include the cavity structure wall being set on the first substrate second surface
And the void space surrounded by the cavity structure wall；
The first chip is additionally provided on the first surface of the second substrate, first chip is held by the void space
It receives.
4. device according to claim 1-3, which is characterized in that the interconnection structure filling out in the through-hole
Fill height is at least via depth 30%.
5. device according to claim 1-4, which is characterized in that the interconnection structure is rivet arrangement.
6. device according to claim 1-5, which is characterized in that the interconnection structure is by capableing of curing molding
Conductive bonding material is formed.
7. according to the described in any item devices of claim 6, which is characterized in that the conductive bonding material is conducting resinl.
8. device according to claim 1-7, which is characterized in that also set on the first surface of the second substrate
It is equipped with solder mask, the solder mask is located at around first weld pad.
9. device according to claim 8, which is characterized in that the solder mask is solder mask limiting structure or non-solder mask
Limiting structure.
10. -9 described in any item devices according to claim 1, which is characterized in that the device further includes setting described the
The second weld pad on the second surface of two substrates, second weld pad with external circuit for being electrically connected.
11. -10 described in any item devices according to claim 1, which is characterized in that the device further include:
The third substrate being set to above the first surface of the first substrate；Between the third substrate and the first substrate
It is electrically connected；
The second chip being set to above the third substrate, second chip are electrically connected on third substrate surface.
12. a kind of packaging method of semiconductor devices characterized by comprising
There is provided first substrate and the second substrate, the first substrate and the second substrate include opposite first surface and the
Two surfaces are provided with the first weld pad on the first surface of the second substrate；
The first surface and second surface for running through the first substrate up and down are formed in position corresponding with first weld pad
Through-hole；
First substrate and the second substrate are fitted together, and are oppositely arranged the through-hole with first weld pad；
The interconnection structure for connecting the first substrate and the second substrate is formed in the top of first weld pad, it is described
Interconnection structure is fixed on first weld pad, and is extruded and is filled in the through-hole.
13. according to the method for claim 12, which is characterized in that after forming the through-hole, form the mutual connection
Before structure, further includes:
Metal layer is formed on the surface of the through-hole, the metal layer is used for electrical with the electronic device on the first substrate
Connection.
14. method according to claim 12 or 13, which is characterized in that before forming the through-hole, further includes:
Cavity structure is formed on the second surface of the first substrate, the cavity structure includes being set to the first substrate
Cavity structure wall on second surface and the void space surrounded by the cavity structure wall；The void space is for accommodating
The first chip being set on the second substrate first surface；
It is described that the first surface and second for running through the first substrate up and down is formed in position corresponding with first weld pad
The through-hole on surface, specifically:
The first surface and second surface for running through the first substrate up and down are formed in position corresponding with first weld pad
And the through-hole of the cavity structure wall.
15. the described in any item methods of 2-14 according to claim 1, which is characterized in that described by first substrate and the second substrate
Before fitting together, further includes:
The conductive bonding material of curing molding is capable of in coating on first weld pad；
The top in first weld pad forms the interconnection structure for connecting the first substrate and the second substrate,
It specifically includes:
While first substrate and the second substrate assemble, extrusion coated is capable of leading for curing molding on first weld pad
Electric binding material enables its flow into the through-hole；
It is capable of the conductive bonding material of curing molding described in solidification, to be formed for connecting the first substrate and described second
The interconnection structure of substrate.
16. the described in any item methods of 2-15 according to claim 1, which is characterized in that described by first substrate and the second substrate
It fits together, specifically includes:
First substrate and the second substrate fitting are fitted together using surface mount process.
17. the described in any item methods of 2-16 according to claim 1, which is characterized in that the method also includes:
The second weld pad is formed on the second surface of the second substrate, second weld pad with external circuit for being electrically connected.
18. the described in any item methods of 2-17 according to claim 1, which is characterized in that before assembly, further includes:
Third substrate is formed on the first surface of the first substrate；Between the third substrate and the first substrate electrically
Connection；
The second chip is formed in the top of the third substrate, second chip is electrically connected to the surface of the third substrate
On.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810233595.3A CN110299328B (en) | 2018-03-21 | 2018-03-21 | A stacked package device and packaging method thereof |
| PCT/CN2018/116159 WO2019179145A1 (en) | 2018-03-21 | 2018-11-19 | Package on package device and packaging method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810233595.3A CN110299328B (en) | 2018-03-21 | 2018-03-21 | A stacked package device and packaging method thereof |
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| CN110299328B CN110299328B (en) | 2021-08-13 |
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| WO (1) | WO2019179145A1 (en) |
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| CN115516629A (en) * | 2020-12-23 | 2022-12-23 | 华为技术有限公司 | Optoelectronic device and optoelectronic integrated structure |
| CN115340062A (en) * | 2022-09-23 | 2022-11-15 | 华天科技(南京)有限公司 | Highly integrated MEMS sensor packaging structure and packaging method thereof |
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| WO2019179145A1 (en) | 2019-09-26 |
| CN110299328B (en) | 2021-08-13 |
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