WO2019116464A1 - Semiconductor device and semiconductor device production method - Google Patents

Abstract

This semiconductor device comprises: a substrate (1) having a first main surface and a second main surface facing each other, a groove (9) being formed on the first main surface; a semiconductor region (2) formed so as to be in contact with the surface of the groove (9); and an electron supply region (3) which is formed so as to be in contact with the surface of the semiconductor region (2) and causes the semiconductor region (2) to generate a two-dimensional electron gas layer (2a). In addition, this semiconductor device comprises a first electrode (6) which electrically connects to the two-dimensional electron gas layer (2a) and a second electrode (7) which electrically connects to the two-dimensional electron gas layer (2a) at a position that is separated from the first electrode (6). Among a first side-surface (9a) and a second side-surface (9b) facing one another in the groove (9), the semiconductor region (2) is formed only on the first side-surface (9a).

Description

Semiconductor device and method of manufacturing semiconductor device

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

Conventionally, a semiconductor device capable of increasing the current has been known (Patent Document 1). The semiconductor device described in Patent Document 1 is a HEMT (High Electron Mobility Transistor), and forms a concavo-convex portion in an epitaxial semiconductor layer. The semiconductor device described in Patent Document 1 causes a large current to flow by utilizing the surface (right and left side surfaces) of the uneven portion.

JP 2012-222354 A

However, in the epitaxial semiconductor layer described in Patent Document 1, the crystal planes of the left and right side surfaces of the uneven portion are different. Thus, the semiconductor device described in Patent Document 1 may have different characteristics on the left and right sides of the uneven portion. For example, when the material of the epitaxial semiconductor layer described in Patent Document 1 is gallium nitride, a gallium surface is formed on one side surface of the uneven portion, and a nitrogen surface is formed on the other side surface. Thereby, when forming a HEMT, the contact resistance with the electrode differs depending on the plane orientation. Thereby, even when the same voltage is applied, the currents flowing to the left and right side surfaces of the uneven portion are different.

In addition, since the energy barrier with the electrode is different depending on the plane orientation, the threshold voltage is different. For this reason, in the semiconductor device described in Patent Document 1, there is a possibility that the threshold voltages become unbalanced at the left and right side surfaces of the uneven portion, and the flowing current also becomes unbalanced. As a result, the reliability of the semiconductor device may be reduced.

The present invention has been made in view of the above problems, and an object thereof is to provide a highly reliable semiconductor device and a method of manufacturing the semiconductor device.

A semiconductor device according to one aspect of the present invention is formed in contact with a substrate in which a groove is formed, a semiconductor region formed in contact with the surface of the groove, and the surface of the semiconductor region, and a two-dimensional electron gas layer in the semiconductor region An electron supply region for generating The semiconductor device further includes a first electrode electrically connected to the two-dimensional electron gas layer, and a second electrode electrically connected to the two-dimensional electron gas layer at a position separated from the first electrode. The semiconductor region is formed only on the first side surface of the first side surface and the second side surface facing each other in the groove.

According to the present invention, a highly reliable semiconductor device and a method of manufacturing the semiconductor device can be provided.

FIG. 1 is a perspective view for explaining the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view as viewed from the direction AA of FIG. FIG. 3 is a perspective view for explaining the method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 4 is a perspective view for explaining the method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 5 is a perspective view for explaining the method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 6 is a perspective view for explaining the configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 7 is a cross-sectional view as viewed from the AA direction of FIG. FIG. 8 is a perspective view for explaining the configuration of the semiconductor device according to the third embodiment of the present invention. FIG. 9 is a cross-sectional view as viewed from the direction AA of FIG. FIG. 10 is a perspective view for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 11 is a cross-sectional view as viewed from the AA direction of FIG. FIG. 12 is a perspective view for explaining the configuration of the semiconductor device according to the fifth embodiment of the present invention. FIG. 13 is a cross-sectional view as viewed from the AA direction of FIG. FIG. 14 is a perspective view for explaining the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention. FIG. 15 is a cross-sectional view as viewed from the AA direction of FIG. FIG. 16 is a perspective view for explaining the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention. FIG. 17 is a view of FIG. 16 as viewed from above. FIG. 18 is a perspective view for explaining the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention. FIG. 19 is a perspective view for explaining the configuration of the semiconductor device according to the sixth embodiment of the present invention. FIG. 20 is a cross-sectional view as viewed from the AA direction of FIG. FIG. 21 is a perspective view for explaining the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. FIG. 22 is a view of FIG. 21 as viewed from above. FIG. 23 is a perspective view for explaining the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. FIG. 24 is a view of FIG. 23 as viewed from above. FIG. 25 is a perspective view for explaining the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. FIG. 26 is a cross-sectional view as viewed in the direction of arrows AA in FIG. FIG. 27 is a perspective view illustrating the configuration of the semiconductor device according to the seventh embodiment of the present invention. FIG. 28 is a cross-sectional view as viewed in the direction of arrows AA in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same parts will be denoted by the same reference numerals and the description thereof will be omitted. In the present specification, the definitions of "upper" and "lower", such as "upper surface" and "lower surface", are merely a representational problem on the cross-sectional view illustrated, for example, by changing the orientation of the semiconductor device by 90 °. It goes without saying that, when observed, the names of “upper” and “lower” become “left” and “right”, and when changed 180 ° and observed, the relationship between the names of “upper” and “lower” is reversed. In addition, “back side” is a problem of expression on the cross-sectional view illustrated, and as in the case of “upper” and “lower” selection, if specific semiconductor device orientation is changed, its affirmation or definition Of course it can change.

First Embodiment
(Structure of semiconductor device)
The configuration of the semiconductor device according to the first embodiment will be described with reference to FIGS. 1 and 2. The semiconductor device according to the first embodiment includes a substrate 1, a semiconductor region 2, an electron supply region 3, a back electrode 4, a gate electrode 5, a source electrode 6, a drain electrode 7, a groove 9, and a mask. The material 12 and the insulating layer 13 are provided.

The substrate 1 is a flat plate made of an insulator. As an insulator to be a material of the substrate 1, for example, silicon can be adopted. The substrate 1 has, for example, a thickness of about several hundred μm. The substrate 1 has a first main surface (upper surface shown in FIG. 1) and a second main surface (lower surface shown in FIG. 1) facing each other. The groove 9 is formed in the first main surface of the substrate 1. The groove 9 has two side surfaces (first side surface 9 a and second side surface 9 b) which are orthogonal to the first main surface of the substrate 1 and parallel to each other, and one bottom surface parallel to the first main surface of the substrate 1. The first side surface 9a and the second side surface 9b face each other. The substrate 1 is selected such that the first side surface 9 a of the groove 9 is a silicon crystal surface. The silicon crystal face of the first side face 9a is a (111) face.

The semiconductor region 2 is formed in contact with only the first side surface 9 a of the groove 9. In other words, the semiconductor region 2 is formed in contact with only one of the two side surfaces of the groove 9. The semiconductor region 2 is formed in contact with the bottom surface of the groove 9 via the insulating layer 13. The semiconductor region 2 may be in direct contact with the bottom surface of the groove 9 without the insulating layer 13 interposed therebetween. The semiconductor region 2 is made of, for example, gallium nitride (GaN) and has a thickness of about several μm.

The electron supply region 3 is formed in contact with the surface of the semiconductor region 2. The electron supply region 3 is made of, for example, aluminum gallium nitride (AlGaN). The electron supply region 3 formed on the surface of the semiconductor region 2 generates a two-dimensional electron gas layer 2 a in the semiconductor region 2 due to the work function difference between gallium nitride and aluminum gallium nitride. The two-dimensional electron gas layer 2a is a layer in which a two-dimensional electron gas to be a channel is formed, and is an electron transit layer. The two-dimensional electron gas layer 2 a is formed in the vicinity of the interface between the semiconductor region 2 and the electron supply region 3.

As shown in FIG. 2, the gate electrode 5, the source electrode 6, and the drain electrode 7 are formed so as to be sandwiched between the electron supply region 3 and the insulating layer 13 inside the groove 9. The gate electrode 5, the source electrode 6, and the drain electrode 7 are in contact with the bottom of the groove 9 via the insulating layer 13. The gate electrode 5, the source electrode 6, and the drain electrode 7 constitute a transistor.

The source electrode 6 (first electrode) is electrically connected to the two-dimensional electron gas layer 2 a and formed to be separated from the drain electrode 7. The drain electrode 7 (second electrode) is electrically connected to the two-dimensional electron gas layer 2 a and formed to be separated from the source electrode 6. Further, the source electrode 6 and the drain electrode 7 are in ohmic contact with the semiconductor region 2.

The gate electrode 5 (third electrode) is located between the source electrode 6 and the drain electrode 7 and formed in contact with the electron supply region 3. Specifically, the gate electrode 5 is disposed between the source electrode 6 and the drain electrode 7 in proximity to the two-dimensional electron gas layer 2a. The gate electrode 5 controls the number of carriers in the two-dimensional electron gas layer 2a.

The back surface electrode 4 is formed on the lower surface (second main surface) of the substrate 1. The back electrode 4 is made of titanium (Ti), nickel (Ni), Ag (silver) or the like, and has a ground potential.

The insulating layer 13 is a film that electrically insulates the semiconductor device from other circuits and the like and mechanically protects the semiconductor device. The insulating layer 13 is made of an insulator including a ceramic material such as a silicon nitride film (Si ₃ N ₄ ) or a silicon oxide film (SiO ₂ ). The insulating layer 13 is formed to be deposited on the bottom surface of the groove 9, the second side surface 9 b of the groove 9, and the mask material 12.

(Method of manufacturing semiconductor device)
Next, an example of a method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS.

(Step 1)
First, the method of forming the groove 9 will be described with reference to FIG. As shown in FIG. 3, the mask material 12 is formed on the first main surface of the substrate 1. The mask material 12 is, for example, a silicon oxide film (SiO ₂ ). The thickness of the mask material 12 is preferably several μm. The mask material 12 is deposited on the first main surface of the substrate 1 by a chemical vapor deposition method such as a thermal CVD method or a plasma CVD method.

Next, a resist material (not shown) is applied to the upper surface of the mask material 12. Next, the resist material is patterned using a general photolithography method. Next, the mask material 12 is etched using the patterned resist material as a mask. Thereby, the groove forming mask is formed. Note that dry etching such as reactive ion etching can be used as the etching method.

Thereafter, the resist material is removed by oxygen plasma, sulfuric acid or the like. Next, using the patterned mask material 12 as a mask, grooves 9 are formed in the first main surface of the substrate 1 by dry etching as shown in FIG. Although the dimension of the groove 9 is not particularly limited, for example, the width of the groove 9 is 6 μm and the depth is 10 μm.

(Step 2)
Next, with reference to FIG. 4, the exposure of the first side surface 9 a of the groove 9 will be described.

As shown in FIG. 4, the insulating layer 13 is formed on the substrate 1. Specifically, the insulating layer 13 is formed to be deposited on the bottom surface of the groove 9, the second side surface 9b of the groove 9, and the mask material 12. The insulating layer 13 is deposited using, for example, LPCVD. The thickness of the insulating layer 13 is, for example, about 100 nm. By forming the insulating layer 13, the surface of the substrate 1 is protected by the insulating layer 13. Next, a resist material is applied to the upper surface of the mask material 12. The resist material is patterned using a general photolithography method. Next, the mask material 12 is etched using the patterned resist material as a mask. Thereby, the first side surface 9 a of the groove 9 is exposed. Note that wet etching with phosphoric acid can be used as the etching method.

(Third step)
Next, a method of forming the semiconductor region 2 and the electron supply region 3 will be described with reference to FIG.

As shown in FIG. 5, a buffer layer is grown on the substrate 1 in which the grooves 9 are formed by the MOCVD method. Specifically, the substrate 1 is introduced into the MOCVD apparatus, and the temperature is raised to a predetermined temperature (for example, 600 ° C.). When the temperature is stabilized, the substrate 1 is rotated to introduce trimethylaluminum (TMA) as a raw material to the surface of the substrate 1 at a predetermined flow rate. The buffer layer is made of, for example, aluminum gallium nitride (AlGaN) represented by the general formula Al _x Ga _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ 1-x−y ≦ 1), It has a thickness of about several hundred nm.

Thereafter, non-doped gallium nitride is deposited on the buffer layer to form the semiconductor region 2 composed of the buffer layer and the non-doped gallium nitride layer. The semiconductor region 2 formed by this method is a mismatch of lattice multipliers, and a high quality crystal layer is formed only on the (111) plane. A layer to be the semiconductor region 2 is basically not formed on the silicon oxide film or the silicon nitride film. The thickness of the non-doped gallium nitride layer is determined by the required breakdown voltage value, and is described as 5 μm in this embodiment, for example. Next, the electron supply region 3 is formed using the same method. The thickness of the electron supply region 3 is, for example, several tens of nm.

(Step 4)
A resist material is formed on the electron supply region 3 formed in the third step, and patterning is performed so that the positions at which the source electrode 6 and the drain electrode 7 are to be formed are exposed. Thereafter, a metal material to be the source electrode 6 and the drain electrode 7 is deposited. The metal material is, for example, titanium (Ti), aluminum (Al), molybdenum (Mo), gold (Au). Note that a vacuum evaporation method can be used as a deposition method. In order to improve the coverage, the substrate 1 may be rotated at a predetermined angle and a predetermined speed.

After depositing the metal material on the resist material, the metal material is lifted off in an acetone solution to form the source electrode 6 and the drain electrode 7.

Next, annealing is performed to improve the ohmic property. Annealing treatment is performed, for example, using a rapid thermal annealing apparatus (RTA: Rapid Thermal Anneal). The heat treatment temperature is preferably 850 ° C., and the treatment time is preferably 30 seconds.

Next, the gate electrode 5 is formed. The formation method is the same as the formation method of the source electrode 6 and the drain electrode 7. First, patterning is performed so as to expose the position where the gate electrode 5 is to be formed. Thereafter, a metal material to be the gate electrode 5 is deposited. The metal material is, for example, nickel (Ni), gold (Au). As a deposition method, a vacuum deposition method using an electron beam deposition apparatus can be used. Further, in order to improve the coverage, the substrate 1 may be rotated at a predetermined angle and a predetermined speed. After depositing a metal material on a resist material, the metal material is lifted off in an acetone solution to form a gate electrode 5.

Next, a metal material is deposited on the back surface of the substrate 1 using a vacuum evaporation method to form the back surface electrode 4. The metal material is, for example, titanium (Ti), nickel (Ni), silver (Ag). Thus, the semiconductor device shown in FIG. 1 is manufactured.

(Operation example of semiconductor device)
Next, the basic operation of the semiconductor device according to the first embodiment shown in FIG. 1 will be described.

The semiconductor device has a semiconductor region 2 and an electron supply region 3. A high concentration two-dimensional electron gas layer 2a is formed in the vicinity of the interface between the semiconductor region 2 and the electron supply region 3, and the source electrode 6 and the drain electrode 7 are in ohmic contact with the two-dimensional electron gas layer 2a. The semiconductor device can control the presence or absence of the two-dimensional electron gas in the lower part of the gate electrode 5 by controlling the voltage applied to the gate electrode 5, and can conduct or disconnect the source and the drain.

Specifically, the semiconductor device functions as a transistor by controlling the potential of the gate electrode 5 in a state where a predetermined positive potential is applied to the drain electrode 7 based on the potential of the source electrode 6. When the gate-source voltage is equal to or higher than a predetermined threshold value, the depletion layer extending from the gate electrode 5 to the semiconductor region 2 via the electron supply region 3 disappears. Thereby, the two-dimensional electron gas layer 2a is formed at the interface between the electron supply region 3 and the semiconductor region 2 (below the gate electrode 5), and the transistor is turned on. A current flows from the drain electrode 7 to the source electrode 6. In the semiconductor device, the density of the channel connecting the source and the drain can be improved by using the side surface of the groove 9, and a large current can be obtained as compared with the planar structure.

When the gate-source voltage is smaller than a predetermined threshold, the depletion layer spreads from the gate electrode 5 to the semiconductor region 2 through the electron supply region 3, and the two-dimensional electron gas layer 2a disappears. Thereby, the transistor is turned off and the current is cut off. At this time, a high voltage is instantaneously applied between the source and drain, and the depletion layer spreads from the gate electrode 5 toward the drain electrode 7. The breakdown voltage of the semiconductor device is ensured by this depletion layer. Since the semiconductor region 2 is formed of gallium nitride, the band gap and the dielectric breakdown electric field are large, and a large breakdown voltage can be obtained even if the thickness of the semiconductor region 2 is thin. Thereby, the thickness of the semiconductor region 2 can be reduced and the width of the groove 9 can be reduced, so that the area efficiency of the substrate 1 is improved. Thus, a semiconductor device with a large current density can be provided.

Further, in the first embodiment, the semiconductor region 2 is formed only on the first side surface 9 a of the groove 9. Thereby, as compared with the case where the semiconductor regions 2 are formed on the left and right side surfaces of the groove 9, the imbalance of the threshold voltage and the imbalance of the flowing current can be improved. Furthermore, the width of the groove 9 can be further reduced by using only the first side surface 9 a of the groove 9. Thereby, the area efficiency of the substrate 1 is improved, and the current density is also improved. Thus, a semiconductor device with high reliability and large current density can be provided.

Further, according to the semiconductor device of the first embodiment, the groove 9 has a depth equal to or greater than the width of the groove 9. As a result, the area efficiency is improved compared to a semiconductor device using only a plane, and a large current can be realized.

In addition, gate electrode 5 may be formed in contact with electron supply region 3 inside groove 9. In order to flow a large current, it is necessary to reduce the wiring resistance. By forming gate electrode 5 in contact with electron supply region 3 inside groove 9, gate electrode 5 can be provided in groove 9. Thereby, the area of the gate electrode 5 used on the surface of the substrate 1 can be reduced. Thus, the source electrode 6 or the drain electrode 7 can be formed thick, and the wiring resistance can be reduced. Thus, a semiconductor device with a large current density can be provided.

Further, according to the semiconductor device of the first embodiment, the substrate 1 is made of an insulator. As a result, when a high voltage is applied to the drain electrode 7, it is possible to prevent a leak current flowing from the drain electrode 7 to the back surface electrode 4 via the semiconductor region 2 and the substrate 1. This improves the reliability of the semiconductor device. Further, since the thickness of the semiconductor region 2 can be further reduced, the width of the groove 9 can be further reduced. As a result, the area efficiency of the substrate 1 is improved, and a semiconductor device with a large current density can be provided. As described later, even if the substrate 1 is a semi-insulating semiconductor, the same effect can be obtained.

Second Embodiment
Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 6 and 7. The second embodiment differs from the first embodiment in that the semiconductor device constitutes not a transistor but a diode. In the second embodiment, the source electrode 6 according to the first embodiment is described as the anode electrode 6. In the second embodiment, the drain electrode 7 according to the first embodiment is described as the cathode electrode 7. Further, the method of manufacturing the semiconductor device according to the second embodiment is the same as that of the first embodiment except for the gate electrode 5, so the description will be omitted. In addition, with regard to the same configuration as the first embodiment, the reference numerals will be cited and the description thereof will be omitted, and the following description will be made focusing on the differences.

(Structure of semiconductor device)
As shown in FIGS. 6 and 7, the anode electrode 6 has an energy barrier with the semiconductor region 2. The cathode electrode 7 is in ohmic contact with the semiconductor region 2.

(Operation example of semiconductor device)
The basic operation of the semiconductor device according to the second embodiment shown in FIG. 6 will be described.

In the on operation, a forward voltage is applied which makes the cathode electrode 7 a low potential with reference to the potential of the anode electrode 6. As a result, the energy barrier is lowered and forward current flows from the anode electrode 6 to the cathode electrode 7. In the semiconductor device, the density of the channel connecting between the anode and the cathode can be improved by utilizing the side surface of the groove 9, and the current can be increased as compared with the planar structure.

In the off operation, a reverse voltage is applied to set the cathode electrode 7 to a high potential with reference to the potential of the anode electrode 6. Thus, the energy barrier becomes high, the forward current is interrupted, and the semiconductor device is turned off. At this time, a high voltage is instantaneously applied between the cathode electrode 7 and the anode electrode 6. Thus, the depletion layer spreads from the anode electrode 6 toward the cathode electrode 7. The breakdown voltage of the semiconductor device is ensured by this depletion layer. Since the semiconductor region 2 is formed of gallium nitride, the band gap and the dielectric breakdown electric field are large, and a large breakdown voltage can be obtained even if the thickness of the semiconductor region 2 is thin. Thereby, the thickness of the semiconductor region 2 can be reduced and the width of the groove 9 can be reduced, so that the area efficiency of the substrate 1 is improved. Thus, a semiconductor device with a large current density can be provided.

In the second embodiment, the semiconductor region 2 is formed only on the first side surface 9 a of the groove 9. Thereby, as compared with the case where the semiconductor regions 2 are formed on the left and right side surfaces of the groove 9, the imbalance of the threshold voltage and the imbalance of the flowing current can be improved. Furthermore, the width of the groove 9 can be further reduced by using only the first side surface 9 a of the groove 9. Thereby, the area efficiency of the substrate 1 is improved, and the current density is also improved. Thus, a semiconductor device with high reliability and large current density can be provided.

Also, according to the semiconductor device of the second embodiment, the groove 9 has a depth equal to or greater than the width of the groove 9. As a result, the area efficiency is improved compared to a semiconductor device using only a plane, and a large current can be realized.

Third Embodiment
Next, with reference to FIGS. 8 to 11, a semiconductor device according to a third embodiment of the present invention will be described. The third embodiment is different from the first embodiment in that the electron supply region 3 is in contact with the second side surface 9 b via the insulating layer 13. About the composition which overlaps with a 1st embodiment, a code is quoted, the explanation shall be omitted and it explains focusing on difference below.

(Structure of semiconductor device)
As shown in FIGS. 8 and 9, the electron supply region 3 has a region which is not in contact with the gate electrode 5, the source electrode 6, and the drain electrode 7 inside the groove 9. In this region, the electron supply region 3 is in contact with the second side surface 9 b opposed to the first side surface 9 a via the insulating layer 13.

(Method of manufacturing semiconductor device)
An example of a method of manufacturing the semiconductor device shown in FIG. 8 will be described with reference to FIGS. 10 and 11. As shown in FIG. 10, the mask material 12 is formed on the first main surface of the substrate 1. The mask material 12 is, for example, a silicon oxide film (SiO ₂ ). The thickness of the mask material 12 is preferably several μm. The mask material 12 is deposited on the first main surface of the substrate 1 by a chemical vapor deposition method such as a thermal CVD method or a plasma CVD method.

Next, a resist material is applied to the upper surface of the mask material 12. Next, the resist material is patterned using a general photolithography method. Next, the mask material 12 is etched using the patterned resist material as a mask. Thereby, the groove forming mask is formed. Note that dry etching such as reactive ion etching can be used as the etching method.

Thereafter, the resist material is removed by oxygen plasma, sulfuric acid or the like. Next, using the patterned mask material 12 as a mask, grooves 9 are formed in the first main surface of the substrate 1 by dry etching as shown in FIG. Although the dimension of the groove 9 is not particularly limited, for example, the width of the groove 9 is 6 μm and the depth is 10 μm. The subsequent manufacturing method is the same as that of the first embodiment, and thus the description thereof is omitted.

(Operation example of semiconductor device)
Next, the basic operation of the semiconductor device according to the third embodiment shown in FIG. 8 will be described.

The semiconductor device has a semiconductor region 2 and an electron supply region 3. A high concentration two-dimensional electron gas layer 2a is formed in the vicinity of the interface between the semiconductor region 2 and the electron supply region 3, and the source electrode 6 and the drain electrode 7 are in ohmic contact with the two-dimensional electron gas layer 2a. The semiconductor device can control the presence or absence of the two-dimensional electron gas in the lower part of the gate electrode 5 by controlling the voltage applied to the gate electrode 5, and can conduct or disconnect the source and the drain.

Specifically, the semiconductor device functions as a transistor by controlling the potential of the gate electrode 5 in a state where a predetermined positive potential is applied to the drain electrode 7 based on the potential of the source electrode 6. When the gate-source voltage is equal to or higher than a predetermined threshold value, the depletion layer extending from the gate electrode 5 to the semiconductor region 2 via the electron supply region 3 disappears. Thereby, the two-dimensional electron gas layer 2a is formed at the interface between the electron supply region 3 and the semiconductor region 2 (below the gate electrode 5), and the transistor is turned on. A current flows from the drain electrode 7 to the source electrode 6. In the semiconductor device, the density of the channel connecting the source and the drain can be improved by using the side surface of the groove 9, and a large current can be obtained as compared with the planar structure.

When the gate-source voltage is smaller than a predetermined threshold, the depletion layer spreads from the gate electrode 5 to the semiconductor region 2 through the electron supply region 3, and the two-dimensional electron gas layer 2a disappears. Thereby, the transistor is turned off and the current is cut off. At this time, a high voltage is instantaneously applied between the source and drain, and the depletion layer spreads from the gate electrode 5 toward the drain electrode 7. The breakdown voltage of the semiconductor device is ensured by this depletion layer. Since the semiconductor region 2 is formed of gallium nitride, the band gap and the dielectric breakdown electric field are large, and a large breakdown voltage can be obtained even if the thickness of the semiconductor region 2 is thin. Thereby, the thickness of the semiconductor region 2 can be reduced and the width of the groove 9 can be reduced, so that the area efficiency of the substrate 1 is improved. Thus, a semiconductor device with a large current density can be provided.

In the third embodiment, the semiconductor region 2 is formed only on the first side surface 9 a of the groove 9. Thereby, as compared with the case where the semiconductor regions 2 are formed on the left and right side surfaces of the groove 9, the imbalance of the threshold voltage and the imbalance of the flowing current can be improved. Furthermore, the width of the groove 9 can be further reduced by using only the first side surface 9 a of the groove 9. Thereby, the area efficiency of the substrate 1 is improved, and the current density is also improved. Thus, a semiconductor device with high reliability and large current density can be provided.

Further, according to the semiconductor device of the third embodiment, the groove 9 has a depth equal to or greater than the width of the groove 9. As a result, the area efficiency is improved compared to a semiconductor device using only a plane, and a large current can be realized.

Further, according to the semiconductor device of the third embodiment, the electron supply region 3 has a region not in contact with the gate electrode 5, the source electrode 6, and the drain electrode 7 in the inside of the groove 9. In this region, the electron supply region 3 is in contact with the second side surface 9 b opposed to the first side surface 9 a via the insulating layer 13. Thereby, the groove 9 can be filled. Thus, for example, assuming that the thickness of the semiconductor region 2 is 5 μm, the thickness of the electron supply region 3 is 30 nm, and the thickness of the insulating layer 13 is 50 nm, the width of the groove 9 is 5080 nm. Can be made smaller. Thereby, the area efficiency of the substrate 1 is improved, and the current density of the device is also improved. Further, heat generated when the semiconductor device operates as a transistor can be released from the electron supply region 3 to the substrate 1 through the insulating layer 13. Thus, it is possible to provide a low loss semiconductor device capable of reducing an increase in resistance due to temperature rise.

Fourth Embodiment
Next, a semiconductor device according to a fourth embodiment of the present invention will be described. In the fourth embodiment, a semi-insulating semiconductor is used as the material of the substrate 1. For example, silicon carbide (SiC) can be adopted as the semi-insulating semiconductor. The semi-insulating substrate is a substrate in which the first side surface 9 a of the groove 9 for growing the semiconductor region 2 is the Si surface of silicon carbide. About the composition which overlaps with a 1st embodiment, a code is quoted, the explanation shall be omitted and it explains focusing on difference below.

(Method of manufacturing semiconductor device)
Next, an example of a method of manufacturing a semiconductor device according to the fourth embodiment will be described. In the fourth embodiment, the step of exposing the first side surface 9 a of the groove 9 is different from that of the first embodiment.

The insulating layer 13 is formed on the semi-insulating substrate. It is preferable to use a silicon oxide film as the insulating layer 13. Thermal oxidation can be used as a deposition method. The semi-insulating substrate is heated at 1000 ° C. to 1200 ° C. for 200 minutes to 300 minutes in an oxygen atmosphere. Thereby, a Si surface is formed on the semi-insulating substrate. The thickness of the silicon oxide film is preferably about 10 nm to 100 nm. Silicon carbide differs in thermal oxidation rate depending on the crystal plane orientation, and the Si surface is the slowest surface compared to other surfaces. Next, the silicon oxide film is removed. The method of removing the silicon oxide film is preferably wet etching with diluted hydrofluoric acid. At this time, the time is set so that only the silicon oxide film on the Si surface can be removed. As a result, only the Si surface is exposed, and the silicon oxide film remains on the other surface. Next, the process proceeds to the step of forming the semiconductor region 2. The subsequent manufacturing method is the same as that of the first embodiment, and thus the description thereof is omitted.

According to the semiconductor device of the fourth embodiment, a semi-insulating substrate is used as the substrate 1. Since the semi-insulating substrate has higher insulation than a silicon substrate, leakage current can be reduced. Thereby, the thickness of the semiconductor region 2 can be reduced, and the width of the groove 9 can be reduced. Thereby, the area efficiency of the substrate 1 is improved, and the current density is also improved. Furthermore, silicon carbide has high thermal conductivity and can suppress the temperature rise of the element when a large current flows. Thus, the increase in resistance of the element due to temperature rise can be reduced, and a low loss semiconductor device can be provided.

Further, by forming the semiconductor region 2 on the Si surface of silicon carbide, the photolithography process using a mask becomes unnecessary in the process of exposing the first side surface 9 a of the groove 9. Thus, the misalignment due to the mask alignment is eliminated, and a highly reliable semiconductor device can be provided. In addition, since the cost of the mask becomes unnecessary, the manufacturing cost of the semiconductor device can be reduced. In addition, silicon carbide differs in thermal oxidation rate depending on the crystal plane orientation, and the Si surface is the slowest surface compared to other surfaces. Therefore, only the Si surface can be exposed by the oxide film wet etching process for a predetermined time. This makes it possible to provide a semiconductor device that is easy to manufacture.

Fifth Embodiment
Next, a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIG. 12 to FIG. The fifth embodiment is different from the first embodiment in that the conductive region 15 is formed in a part of the substrate 1. The substrate 1 is a semi-insulating substrate. About the composition which overlaps with a 1st embodiment, a code is quoted, the explanation shall be omitted and it explains focusing on difference below. The substrate 1 may be an insulator.

(Structure of semiconductor device)
As shown in FIGS. 12 and 13, the substrate 1 has a conductive region 15 formed by ion implantation. The conductive region 15 is in contact with the electron supply region 3 via the insulating layer 13. Conductive region 15 is electrically connected to gate electrode 5.

(Method of manufacturing semiconductor device)
An example of a method of manufacturing the semiconductor device shown in FIG. 12 will be described with reference to FIGS. 14 to 18.

(Step 1)
As shown in FIG. 14, the mask material 12 is formed on the first main surface of the substrate 1. The mask material 12 is, for example, a silicon oxide film (SiO ₂ ). The thickness of the mask material 12 is preferably several μm. The mask material 12 is deposited on the first main surface of the substrate 1 by a chemical vapor deposition method such as a thermal CVD method or a plasma CVD method.

Next, a resist material is applied to the upper surface of the mask material 12. Next, the resist material is patterned using a general photolithography method. Next, the mask material 12 is etched using the patterned resist material as a mask. Thereby, the groove forming mask is formed. Note that dry etching such as reactive ion etching can be used as the etching method.

Thereafter, the resist material is removed by oxygen plasma, sulfuric acid or the like. Next, using the patterned mask material 12 as a mask, grooves 9 are formed on the first main surface of the substrate 1 by dry etching as shown in FIG. Although the dimension of the groove 9 is not particularly limited, for example, the width of the groove 9 is 6 μm and the depth is 10 μm. Thereafter, the mask material 12 is removed using diluted hydrofluoric acid.

Next, as shown in FIG. 16, the resist material 16 is patterned. Next, aluminum ion implantation is performed to form a P-type conductive region 15. Thereafter, the resist material 16 is removed by oxygen plasma, sulfuric acid or the like to perform activation. As an activation method, annealing is preferably performed for 10 minutes to 20 minutes in an atmosphere of argon (Ar) gas at 1500 ° C. to 1800 ° C. Thereby, as shown in FIG. 18, the conductive region 15 is formed.

(Step 2)
Next, the insulating layer 13 is formed on the semi-insulating substrate (substrate 1). It is preferable to use a silicon oxide film as the insulating layer 13. Thermal oxidation can be used as a deposition method. The semi-insulating substrate is heated at 1000 ° C. to 1200 ° C. for 200 minutes to 300 minutes in an oxygen atmosphere. Thereby, a Si surface is formed on the semi-insulating substrate. The thickness of the silicon oxide film is preferably about 10 nm to 100 nm. Silicon carbide differs in thermal oxidation rate depending on the crystal plane orientation, and the Si surface is the slowest surface compared to other surfaces. Next, the silicon oxide film is removed. The method of removing the silicon oxide film is preferably wet etching with diluted hydrofluoric acid. At this time, the time is set so that only the silicon oxide film on the Si surface can be removed. As a result, only the Si surface is exposed, and the silicon oxide film remains on the other surface.

(Third step)
The buffer layer is grown on the substrate 1 in which the groove 9 is formed by the MOCVD method. Specifically, the substrate 1 is introduced into the MOCVD apparatus, and the temperature is raised to a predetermined temperature (for example, 600 ° C.). When the temperature is stabilized, the substrate 1 is rotated to introduce trimethylaluminum (TMA) as a raw material to the surface of the substrate 1 at a predetermined flow rate. The buffer layer is made of, for example, aluminum gallium nitride (AlGaN) represented by the general formula Al _x Ga _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ 1-x−y ≦ 1), It has a thickness of about several hundred nm.

Thereafter, non-doped gallium nitride is deposited on the buffer layer to form the semiconductor region 2 composed of the buffer layer and the non-doped gallium nitride layer. The semiconductor region 2 formed by this method is a mismatch of lattice multipliers, and a high quality crystal layer is formed only on the (111) plane. A layer to be the semiconductor region 2 is basically not formed on the silicon oxide film or the silicon nitride film. The thickness of the non-doped gallium nitride layer is determined by the required breakdown voltage value, and is described as 5 μm in this embodiment, for example. Next, the electron supply region 3 is formed using the same method. The thickness of the electron supply region 3 is, for example, several tens of nm.

(Step 4)
A resist material is formed on the electron supply region 3 formed in the third step, and patterning is performed so that the positions at which the source electrode 6 and the drain electrode 7 are to be formed are exposed. Thereafter, a metal material to be the source electrode 6 and the drain electrode 7 is deposited. The metal material is, for example, titanium (Ti), aluminum (Al), molybdenum (Mo), gold (Au). Note that a vacuum evaporation method can be used as a deposition method. In order to improve the coverage, the substrate 1 may be rotated at a predetermined angle and a predetermined speed.

After depositing the metal material on the resist material, the metal material is lifted off in an acetone solution to form the source electrode 6 and the drain electrode 7. Next, annealing is performed to improve the ohmic property. Annealing treatment is performed, for example, using a rapid thermal annealing apparatus (RTA: Rapid Thermal Anneal). The heat treatment temperature is preferably 850 ° C., and the treatment time is preferably 30 seconds.

Next, the gate electrode 5 is formed. The formation method is the same as the formation method of the source electrode 6 and the drain electrode 7. First, patterning is performed so as to expose the position where the gate electrode 5 is to be formed. Next, the conductive region 15 is exposed on the surface of the substrate 1. As an exposure method, patterning is performed so that the position where the gate electrode 5 is to be formed is exposed. Next, the silicon oxide film on the surface of the substrate 1 is removed with diluted hydrofluoric acid.

Thereafter, a metal material to be the gate electrode 5 is deposited. The metal material is, for example, nickel. Although the deposition amount is not particularly limited, for example, 100 nm of nickel is deposited. As a deposition method, a vacuum deposition method using an electron beam deposition apparatus can be used. Further, in order to improve the coverage, the substrate 1 may be rotated at a predetermined angle and a predetermined speed. After depositing the metal material, the gate electrode 5 is formed by lifting off the metal material in an acetone solution.

Next, a metal material is deposited on the back surface of the substrate 1 using a vacuum evaporation method to form the back surface electrode 4. The metal material is, for example, titanium (Ti), nickel (Ni), silver (Ag). Thus, the semiconductor device shown in FIG. 12 is manufactured.

(Operation example of semiconductor device)
Next, the basic operation of the semiconductor device according to the fifth embodiment shown in FIG. 12 will be described.

The semiconductor device has a semiconductor region 2 and an electron supply region 3. A high concentration two-dimensional electron gas layer 2a is formed in the vicinity of the interface between the semiconductor region 2 and the electron supply region 3, and the source electrode 6 and the drain electrode 7 are in ohmic contact with the two-dimensional electron gas layer 2a. The semiconductor device can control the presence or absence of the two-dimensional electron gas in the lower part of the gate electrode 5 by controlling the voltage applied to the gate electrode 5, and can conduct or disconnect the source and the drain.

Specifically, the semiconductor device functions as a transistor by controlling the potential of the gate electrode 5 in a state where a predetermined positive potential is applied to the drain electrode 7 based on the potential of the source electrode 6. When the gate-source voltage is equal to or higher than a predetermined threshold value, the depletion layer extending from the gate electrode 5 to the semiconductor region 2 via the electron supply region 3 disappears. Thereby, the two-dimensional electron gas layer 2a is formed at the interface between the electron supply region 3 and the semiconductor region 2 (below the gate electrode 5), and the transistor is turned on. A current flows from the drain electrode 7 to the source electrode 6. In the semiconductor device, the density of the channel connecting the source and the drain can be improved by using the side surface of the groove 9, and a large current can be obtained as compared with the planar structure.

When the gate-source voltage is smaller than a predetermined threshold, the depletion layer spreads from the gate electrode 5 to the semiconductor region 2 through the electron supply region 3, and the two-dimensional electron gas layer 2a disappears. Thereby, the transistor is turned off and the current is cut off. At this time, a high voltage is instantaneously applied between the source and drain, and the depletion layer spreads from the gate electrode 5 toward the drain electrode 7. The breakdown voltage of the semiconductor device is ensured by this depletion layer. Since the semiconductor region 2 is formed of gallium nitride, the band gap and the dielectric breakdown electric field are large, and a large breakdown voltage can be obtained even if the thickness of the semiconductor region 2 is thin. Thereby, the thickness of the semiconductor region 2 can be reduced and the width of the groove 9 can be reduced, so that the area efficiency of the substrate 1 is improved. Thus, a semiconductor device with a large current density can be provided.

Further, according to the semiconductor device of the fifth embodiment, the conductive region 15 is made to be the gate electrode 5, thereby eliminating the need for the step of embedding the gate electrode 5 in the groove 9, and the manufacturing becomes easy. Further, the width of the groove 9 can be reduced by the thickness of the gate electrode 5. Therefore, the area efficiency of the substrate 1 is improved, and the current density is also improved. Furthermore, since the conductive region 15 is a semiconductor material, a depletion layer is formed of the semiconductor material when a predetermined voltage is applied. This improves the breakdown voltage of the device.

Sixth Embodiment
Next, a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. The sixth embodiment is different from the first embodiment in that the conductive region 15 is formed in a part of the substrate 1. Furthermore, two N-type conductive regions 17 are formed in a part of the substrate 1. The substrate 1 is a semi-insulating substrate. About the composition which overlaps with a 1st embodiment, a code is quoted, the explanation shall be omitted and it explains focusing on difference below. The substrate 1 may be an insulator.

(Structure of semiconductor device)
As shown in FIGS. 19 and 20, the substrate 1 has a conductive region 15 formed by ion implantation and two N-type conductive regions 17. The conductive region 15 and the two N-type conductive regions 17 are in contact with the electron supply region 3 via the insulating layer 13. The conductive region 15 has the same function as the gate electrode 5 and is electrically connected to the gate electrode 5. One of the two N-type conductive regions 17 has the same function as the source electrode 6 and is electrically connected to the source electrode 6. The other of the two N-type conductive regions 17 has the same function as the drain electrode 7 and is electrically connected to the drain electrode 7.

(Method of manufacturing semiconductor device)
An example of a method of manufacturing the semiconductor device shown in FIG. 19 will be described with reference to FIGS. 21 to 26.

(Step 1)
A mask material 12 is formed on the first main surface of the substrate 1. The mask material 12 is, for example, a silicon oxide film (SiO ₂ ). The thickness of the mask material 12 is preferably several μm. The mask material 12 is deposited on the first main surface of the substrate 1 by a chemical vapor deposition method such as a thermal CVD method or a plasma CVD method.

Next, a resist material is applied to the upper surface of the mask material 12. Next, the resist material is patterned using a general photolithography method. Next, the mask material 12 is etched using the patterned resist material as a mask. Thereby, the groove forming mask is formed. Note that dry etching such as reactive ion etching can be used as the etching method.

Thereafter, the resist material is removed by oxygen plasma, sulfuric acid or the like. Next, using the patterned mask material 12 as a mask, grooves 9 are formed in the first main surface of the substrate 1 by dry etching as shown in FIG. Although the dimension of the groove 9 is not particularly limited, for example, the width of the groove 9 is 6 μm and the depth is 10 μm. Thereafter, the mask material 12 is removed using diluted hydrofluoric acid.

Next, as shown in FIG. 21, the resist material 16 is patterned. Next, aluminum ion implantation is performed to form a P-type conductive region 15.

Next, as shown in FIG. 23, the resist material 16 is patterned. Next, aluminum ion implantation is performed to form an N-type conductive region 17. Thereafter, the resist material 16 is removed by oxygen plasma, sulfuric acid or the like to perform activation. As an activation method, annealing is preferably performed for 10 minutes to 20 minutes in an atmosphere of argon (Ar) gas at 1500 ° C. to 1800 ° C. Thereby, as shown in FIG. 25, the conductive region 15 and the N-type conductive region 17 are formed.

(Step 2)
Next, the insulating layer 13 is formed on the semi-insulating substrate (substrate 1). It is preferable to use a silicon oxide film as the insulating layer 13. Thermal oxidation can be used as a deposition method. The semi-insulating substrate is heated at 1000 ° C. to 1200 ° C. for 200 minutes to 300 minutes in an oxygen atmosphere. Thereby, a Si surface is formed on the semi-insulating substrate. The thickness of the silicon oxide film is preferably about 10 nm to 100 nm. Silicon carbide differs in thermal oxidation rate depending on the crystal plane orientation, and the Si surface is the slowest surface compared to other surfaces. Next, the silicon oxide film is removed. The method of removing the silicon oxide film is preferably wet etching with diluted hydrofluoric acid. At this time, the time is set so that only the silicon oxide film on the Si surface can be removed. As a result, only the Si surface is exposed, and the silicon oxide film remains on the other surface. Next, the resist material 16 is patterned, and the silicon oxide film in the opening of the resist material 16 is removed with diluted hydrofluoric acid to expose the groove side surface (second side surface 9 b) of the N-type conductive region 17.

(Third step)
The buffer layer is grown on the substrate 1 in which the groove 9 is formed by the MOCVD method. Specifically, the substrate 1 is introduced into the MOCVD apparatus, and the temperature is raised to a predetermined temperature (for example, 600 ° C.). When the temperature is stabilized, the substrate 1 is rotated to introduce trimethylaluminum (TMA) as a raw material to the surface of the substrate 1 at a predetermined flow rate. The buffer layer is made of, for example, aluminum gallium nitride (AlGaN) represented by the general formula Al _x Ga _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ 1-x−y ≦ 1), It has a thickness of about several hundred nm.

Thereafter, non-doped gallium nitride is deposited on the buffer layer to form the semiconductor region 2 composed of the buffer layer and the non-doped gallium nitride layer. The semiconductor region 2 formed by this method is a mismatch of lattice multipliers, and a high quality crystal layer is formed only on the (111) plane. A layer to be the semiconductor region 2 is basically not formed on the silicon oxide film or the silicon nitride film. The thickness of the non-doped gallium nitride layer is determined by the required breakdown voltage value, and is described as 5 μm in this embodiment, for example. Next, the electron supply region 3 is formed using the same method. The thickness of the electron supply region 3 is, for example, several tens of nm.

(Step 4)
A resist material 16 is formed on the electron supply region 3 formed in the third step, and patterning is performed so that positions where the source electrode 6 and the drain electrode 7 are to be formed are exposed. Thereafter, a metal material to be the source electrode 6 and the drain electrode 7 is deposited. The metal material is, for example, titanium (Ti), aluminum (Al), molybdenum (Mo), gold (Au). Note that a vacuum evaporation method can be used as a deposition method. In order to improve the coverage, the substrate 1 may be rotated at a predetermined angle and a predetermined speed.

After depositing the metal material on the resist material, the metal material is lifted off in an acetone solution to form the source electrode 6 and the drain electrode 7. Next, annealing is performed to improve the ohmic property. Annealing treatment is performed, for example, using a rapid thermal annealing apparatus (RTA: Rapid Thermal Anneal). The heat treatment temperature is preferably 850 ° C., and the treatment time is preferably 30 seconds.

Next, the gate electrode 5 is formed. The formation method is the same as the formation method of the source electrode 6 and the drain electrode 7. First, patterning is performed so as to expose the position where the gate electrode 5 is to be formed. Next, the conductive region 15 is exposed on the surface of the substrate 1. As an exposure method, patterning is performed so that the position where the gate electrode 5 is to be formed is exposed. Next, the silicon oxide film on the surface of the substrate 1 is removed with diluted hydrofluoric acid.

Thereafter, a metal material to be the gate electrode 5 is deposited. The metal material is, for example, nickel. Although the deposition amount is not particularly limited, for example, 100 nm of nickel is deposited. As a deposition method, a vacuum deposition method using an electron beam deposition apparatus can be used. Further, in order to improve the coverage, the substrate 1 may be rotated at a predetermined angle and a predetermined speed. After depositing the metal material, the gate electrode 5 is formed by lifting off the metal material in an acetone solution. Next, annealing is performed to improve the ohmic property. Annealing treatment is performed, for example, using a rapid thermal annealing apparatus (RTA: Rapid Thermal Anneal). The heat treatment temperature is preferably 850 ° C., and the treatment time is preferably 30 seconds.

(Operation example of semiconductor device)
Next, the basic operation of the semiconductor device according to the sixth embodiment shown in FIG. 19 will be described.

The semiconductor device has a semiconductor region 2 and an electron supply region 3. A high concentration two-dimensional electron gas layer 2a is formed in the vicinity of the interface between the semiconductor region 2 and the electron supply region 3, and the source electrode 6 and the drain electrode 7 are in ohmic contact with the two-dimensional electron gas layer 2a. The semiconductor device can control the presence or absence of the two-dimensional electron gas in the lower part of the gate electrode 5 by controlling the voltage applied to the gate electrode 5, and can conduct or disconnect the source and the drain.

Specifically, the semiconductor device functions as a transistor by controlling the potential of the gate electrode 5 in a state where a predetermined positive potential is applied to the drain electrode 7 based on the potential of the source electrode 6. When the gate-source voltage is equal to or higher than a predetermined threshold value, the depletion layer extending from the gate electrode 5 to the semiconductor region 2 via the electron supply region 3 disappears. Thereby, the two-dimensional electron gas layer 2a is formed at the interface between the electron supply region 3 and the semiconductor region 2 (below the gate electrode 5), and the transistor is turned on. A current flows from the drain electrode 7 to the source electrode 6. In the semiconductor device, the density of the channel connecting the source and the drain can be improved by using the side surface of the groove 9, and a large current can be obtained as compared with the planar structure.

When the gate-source voltage is smaller than a predetermined threshold, the depletion layer spreads from the gate electrode 5 to the semiconductor region 2 through the electron supply region 3, and the two-dimensional electron gas layer 2a disappears. Thereby, the transistor is turned off and the current is cut off. At this time, a high voltage is instantaneously applied between the source and drain, and the depletion layer spreads from the gate electrode 5 toward the drain electrode 7. The breakdown voltage of the semiconductor device is ensured by this depletion layer. Since the semiconductor region 2 is formed of gallium nitride, the band gap and the dielectric breakdown electric field are large, and a large breakdown voltage can be obtained even if the thickness of the semiconductor region 2 is thin. Thereby, the thickness of the semiconductor region 2 can be reduced and the width of the groove 9 can be reduced, so that the area efficiency of the substrate 1 is improved. Thus, a semiconductor device with a large current density can be provided.

Further, according to the semiconductor device of the sixth embodiment, the conductive region 15 is made to be the gate electrode 5, thereby eliminating the need for the step of embedding the gate electrode 5 in the groove 9, and the manufacturing becomes easy. Further, the width of the groove 9 can be reduced by the thickness of the gate electrode 5. Therefore, the area efficiency of the substrate 1 is improved, and the current density is also improved. Furthermore, since the conductive region 15 is a semiconductor material, a depletion layer is formed of the semiconductor material when a predetermined voltage is applied. This improves the breakdown voltage of the device.

Furthermore, according to the semiconductor device of the sixth embodiment, the step of embedding the source electrode 6 and the drain electrode 7 in the groove 9 becomes unnecessary by using the N-type conductive region 17 as the source electrode 6 and the drain electrode 7. , Easy to manufacture. Further, the width of the groove 9 can be reduced by the thickness of the source electrode 6 and the drain electrode 7. Therefore, the area efficiency of the substrate 1 is improved, and the current density is also improved. Thus, a semiconductor device with a large current density can be provided.

Seventh Embodiment
Next, with reference to FIGS. 27 and 28, a semiconductor device according to a seventh embodiment of the present invention will be described. The seventh embodiment is different from the sixth embodiment in that the field plate electrode 11 is formed on a part of the substrate 1. About the structure which overlaps with 6th Embodiment, the code | symbol is quoted and the description shall be abbreviate | omitted, and, below, it demonstrates centering on difference. The substrate 1 may be an insulator.

(Structure of semiconductor device)
As shown in FIGS. 27 and 28, the substrate 1 has a conductive region 15 formed by ion implantation and two N-type conductive regions 17. The conductive region 15 and the two N-type conductive regions 17 are in contact with the electron supply region 3 via the insulating layer 13. The conductive region 15 has the same function as the gate electrode 5 and is electrically connected to the gate electrode 5. One of the two N-type conductive regions 17 has the same function as the source electrode 6 and is electrically connected to the source electrode 6. The other of the two N-type conductive regions 17 has the same function as the drain electrode 7 and is electrically connected to the drain electrode 7. Further, a part of the N-type conductive region 17 to be the source electrode 6 is in contact with the electron supply region 3 via the insulating layer 13. A part of this is the field plate electrode 11. The field plate electrode 11 is formed between the gate electrode 5 and the source electrode 6 and is in contact with the electron supply region 3 via the insulating layer 13. Further, the field plate electrode 11 is at the same potential as the source electrode 6.

(Method of manufacturing semiconductor device)
The structure is the same as the manufacturing method of the sixth embodiment except that the shape of the resist mask for forming the N-type conductive region 17 is different.

(Operation example of semiconductor device)
Next, the basic operation of the semiconductor device according to the seventh embodiment shown in FIG. 27 will be described.

The semiconductor device has a semiconductor region 2 and an electron supply region 3. A high concentration two-dimensional electron gas layer 2a is formed in the vicinity of the interface between the semiconductor region 2 and the electron supply region 3, and the source electrode 6 and the drain electrode 7 are in ohmic contact with the two-dimensional electron gas layer 2a. The semiconductor device can control the presence or absence of the two-dimensional electron gas in the lower part of the gate electrode 5 by controlling the voltage applied to the gate electrode 5, and can conduct or disconnect the source and the drain.

Specifically, the semiconductor device functions as a transistor by controlling the potential of the gate electrode 5 in a state where a predetermined positive potential is applied to the drain electrode 7 based on the potential of the source electrode 6. When the gate-source voltage is equal to or higher than a predetermined threshold value, the depletion layer extending from the gate electrode 5 to the semiconductor region 2 via the electron supply region 3 disappears. Thereby, the two-dimensional electron gas layer 2a is formed at the interface between the electron supply region 3 and the semiconductor region 2 (below the gate electrode 5), and the transistor is turned on. A current flows from the drain electrode 7 to the source electrode 6. In the semiconductor device, the density of the channel connecting the source and the drain can be improved by using the side surface of the groove 9, and a large current can be obtained as compared with the planar structure.

When the gate-source voltage is smaller than a predetermined threshold, the depletion layer spreads from the gate electrode 5 to the semiconductor region 2 through the electron supply region 3, and the two-dimensional electron gas layer 2a disappears. Thereby, the transistor is turned off and the current is cut off. At this time, a high voltage is instantaneously applied between the source and drain, and the depletion layer spreads from the gate electrode 5 toward the drain electrode 7. The breakdown voltage of the semiconductor device is ensured by this depletion layer. Further, the electric field is concentrated on the edge of the conductive region 15 to be the gate electrode 5. According to the semiconductor device of the seventh embodiment, by having the field plate electrode 11, a part of the electric field can be dispersed in the field plate electrode 11, and the electric field applied to the conductive region 15 to be the gate electrode 5 is descend. This improves the breakdown voltage of the device. Further, since the semiconductor region 2 is formed of gallium nitride, the band gap and the dielectric breakdown electric field are large, and a large withstand voltage can be obtained even if the thickness of the semiconductor region 2 is thin. Thereby, the thickness of the semiconductor region 2 can be reduced and the width of the groove 9 can be reduced, so that the area efficiency of the substrate 1 is improved. Thus, a semiconductor device with a large current density can be provided.

Further, according to the semiconductor device of the seventh embodiment, by using the conductive region 15 as the gate electrode 5, the step of embedding the gate electrode 5 in the groove 9 becomes unnecessary, and the semiconductor device can be easily manufactured. Further, the width of the groove 9 can be reduced by the thickness of the gate electrode 5. Therefore, the area efficiency of the substrate 1 is improved, and the current density is also improved. Furthermore, since the conductive region 15 is a semiconductor material, a depletion layer is formed of the semiconductor material when a predetermined voltage is applied. This improves the breakdown voltage of the device.

Furthermore, according to the semiconductor device of the seventh embodiment, the step of embedding the source electrode 6 and the drain electrode 7 in the groove 9 becomes unnecessary by using the N-type conductive region 17 as the source electrode 6 and the drain electrode 7. , Easy to manufacture. Further, the width of the groove 9 can be reduced by the thickness of the source electrode 6 and the drain electrode 7. Therefore, the area efficiency of the substrate 1 is improved, and the current density is also improved.

Furthermore, according to the semiconductor device of the seventh embodiment, the step of burying the field plate electrode 11 in the groove 9 becomes unnecessary, which facilitates manufacture. Further, since a part of the N-type conductive region 17 becomes the field plate electrode 11, the area of the field plate electrode 11 used on the surface of the substrate 1 can be reduced. Thus, the source electrode 6 or the drain electrode 7 can be formed thick, and the wiring resistance can be reduced. Thus, a semiconductor device with a large current density can be provided. Furthermore, since the field plate electrode 11 is a semiconductor material, a depletion layer is formed of the semiconductor material when a predetermined voltage is applied. This improves the breakdown voltage of the device.

(Other embodiments)
While the embodiments of the present invention have been described above, it should not be understood that the statements and drawings that form a part of this disclosure limit the present invention. Various alternative embodiments, examples and operation techniques will be apparent to those skilled in the art from this disclosure.

In the embodiments described above, the manufacture of a semiconductor device using gallium nitride has been described, but materials other than gallium nitride can also be used, and for example, gallium arsenide (GaAs) may be used. Further, the substrate 1 may be sapphire. Since a sapphire substrate has a smaller mismatch of crystal lattice constant with gallium nitride as compared with a silicon substrate and can obtain a high quality substrate, a semiconductor device with high withstand voltage can be provided. Furthermore, since the buffer layer required for the silicon substrate can be largely reduced, a semiconductor device which can be manufactured inexpensively can be provided.

Moreover, although one semiconductor device is described in the above-described embodiment, the present invention is not limited to this. The present invention may include two semiconductor devices (a first semiconductor device and a second semiconductor device). The semiconductor devices according to the first to seventh embodiments can be used as the two semiconductor devices. The two semiconductor devices may be the same or different. By using two semiconductor devices, the source electrode 6 or the drain electrode 7 can be shared with each other, so that an electrode used for the semiconductor device can be a half. Thereby, the area efficiency of the substrate 1 is improved, and a large current can be realized.

Reference Signs List 1 substrate 2 semiconductor region 2a two-dimensional electron gas layer 3 electron supply region 4 back surface electrode 5 gate electrode 6 source electrode 7 source electrode 7 drain electrode 9 groove 9a first side surface 9b second side surface 11 field plate electrode 12 mask material 13 insulating layer 15 conductivity Region 16 Resist material 17 N-type conductive region

Claims (16)

A substrate having a first main surface and a second main surface facing each other, wherein a groove is formed on the first main surface;
A semiconductor region formed in contact with the surface of the groove;
An electron supply region formed in contact with the surface of the semiconductor region and generating a two-dimensional electron gas layer in the semiconductor region;
A first electrode electrically connected to the two-dimensional electron gas layer;
A second electrode electrically connected to the two-dimensional electron gas layer at a position separated from the first electrode;
Equipped with
The semiconductor device is characterized in that the semiconductor region is formed only on the first side surface of the first side surface and the second side surface facing each other in the groove. The first electrode has an energy barrier with the semiconductor region,
The semiconductor device according to claim 1, wherein the second electrode is in ohmic contact with the semiconductor region. The first electrode and the second electrode are ohmically connected to the semiconductor region;
A third electrode is provided between the first electrode and the second electrode and disposed in the vicinity of the two-dimensional electron gas layer to control the number of carriers in the two-dimensional electron gas layer. The semiconductor device according to 1. The semiconductor device according to any one of claims 1 to 3, wherein the depth of the groove is equal to or greater than the width of the groove. The semiconductor device according to any one of claims 1 to 4, wherein at least a part of the electron supply region is in contact with the second side surface facing the first side surface via an insulating layer. The semiconductor device according to claim 3, wherein the third electrode is formed in contact with the electron supply region inside the groove. A field plate electrode is provided between the third electrode and the first electrode in the groove, the field plate electrode being in contact with the electron supply region via an insulating layer,
7. The semiconductor device according to claim 6, wherein the field plate electrode is at the same potential as the first electrode. The semiconductor device according to any one of claims 1 to 7, wherein the substrate is made of an insulator or a semi-insulating semiconductor. A conductive region is formed on a portion of the substrate,
9. The semiconductor device according to claim 8, wherein the conductive region is in contact with the electron supply region via an insulating layer and serves as a third electrode. An N-type conductive region is formed on a portion of the substrate,
The semiconductor device according to claim 8, wherein the N-type conductive region is in contact with the electron supply region and becomes the first electrode and the second electrode. 11. The semiconductor device according to claim 10, wherein at least a part of the N-type conductive region to be the first electrode is in contact with the electron supply region via an insulating layer. The semiconductor device according to any one of claims 1 to 11, wherein the substrate is made of silicon carbide. The semiconductor device according to any one of claims 1 to 12, wherein the first side surface is a Si surface. The semiconductor device according to any one of claims 1 to 13, wherein the semiconductor region is made of gallium nitride. A first semiconductor device comprising the semiconductor device according to any one of claims 1 to 14, and a second semiconductor device comprising the semiconductor device according to any one of claims 1 to 14.
The semiconductor device according to any one of claims 1 to 14, wherein the first semiconductor device and the second semiconductor device share the first electrode or the second electrode with each other. Forming a groove in the first main surface of the substrate having the first main surface and the second main surface facing each other;
Forming a semiconductor region on the side surface of the groove;
Forming an electron supply region for generating a two-dimensional electron gas layer in the semiconductor region in contact with the surface of the semiconductor region;
Forming a first electrode and a second electrode electrically connected to the two-dimensional electron gas layer at mutually spaced positions;
Including
A method of manufacturing a semiconductor device, wherein in the step of forming the semiconductor region, the semiconductor region is formed only on the first side surface of the first side surface and the second side surface facing each other in the groove.

Images