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WO2018224003A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2018224003A1
WO2018224003A1 PCT/CN2018/090248 CN2018090248W WO2018224003A1 WO 2018224003 A1 WO2018224003 A1 WO 2018224003A1 CN 2018090248 W CN2018090248 W CN 2018090248W WO 2018224003 A1 WO2018224003 A1 WO 2018224003A1
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WO
WIPO (PCT)
Prior art keywords
metal trace
retaining wall
forming
array substrate
electrode
Prior art date
Application number
PCT/CN2018/090248
Other languages
English (en)
French (fr)
Inventor
彭勇
张鹏举
李鑫
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/346,025 priority Critical patent/US10923513B2/en
Publication of WO2018224003A1 publication Critical patent/WO2018224003A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate, a preparation method thereof, and a display device.
  • the touch screen can be divided into an external touch screen and an in-line touch screen according to the position of the touch sensor.
  • the control screen can be divided into: an on-cell touch panel (On Cell Touch Panel) and an embedded touch screen (In Cell Touch Panel).
  • the In Cell touch screen can be further divided into a composite in-cell (Hybrid In Cell, HIC) touch screen and a full in-cell (Full In Cell, FIC) touch screen.
  • a first aspect provides a method for fabricating an array substrate, the method comprising: forming a strip-shaped retaining wall on a substrate; wherein a width of the retaining wall is less than or equal to a first metal trace to be formed And a spacing between the second metal traces; forming a conductive film on the barrier wall, and forming the surface on a side of the retaining wall along the extending direction by applying a photoresist, exposure, development, and etching process The first metal trace forms the second metal trace on the other side of the retaining wall along the extending direction.
  • the forming a strip-shaped retaining wall on the base substrate comprises: forming an insulating film on the base substrate, and forming a strip-shaped retaining wall by a patterning process; Forming the first metal trace on one side of the extending direction, and forming the second metal trace on the other side of the retaining wall in the extending direction, including: forming the first metal trace on one side, The second metal trace is formed on the other side of the retaining wall along the extending direction.
  • the forming a strip-shaped retaining wall on the base substrate comprises: forming a strip-shaped retaining wall on the base substrate by using a printing process or an evaporation process; Forming the first metal trace on one side of the extending direction, and forming the second metal trace on the other side of the retaining wall in the extending direction, including: using a printing process or an evaporation process, in the retaining wall The first metal trace is formed on one side in the extending direction, and the second metal trace is formed on the other side of the retaining wall in the extending direction.
  • the retaining wall has a continuous structure; or the retaining wall includes at least two sub-retaining walls spaced apart, and the at least two sub-retaining walls are arranged in a strip shape.
  • the forming an insulating film on the base substrate and forming a strip-shaped retaining wall by a patterning process comprises: forming an insulating film on the base substrate, and reducing thickness of a portion of the insulating film Thin treatment; the remaining portion of the insulating film that has not undergone the thickness thinning treatment forms a strip-shaped retaining wall compared to a portion that protrudes through the partial portion of the thickness thinning treatment.
  • a width of the retaining wall is equal to a spacing between the first metal trace and the second metal trace.
  • the thickness of the retaining wall is less than or equal to the thickness of the first metal trace and the second metal trace.
  • the first metal trace and the second metal trace are respectively formed on the two sides of the retaining wall along the extending direction by applying a photoresist, an exposure, a developing, and an etching process, including: passing Applying a photoresist, exposing, developing, and etching processes to form a source and a drain, and forming a first metal trace on one side of the retaining wall in the extending direction, and another in the extending direction of the retaining wall The side forms a second metal trace, and the source is electrically connected to the first metal trace.
  • the method further includes: forming a gate electrode and a gate insulating layer on the substrate substrate in sequence before forming the insulating film on the substrate; forming the first metal trace and the After the second metal trace, the preparation method further includes: sequentially forming a buffer layer and a flat layer on the first metal trace and the second metal trace; forming a first electrode on the flat layer The first electrode is electrically connected to the second metal trace through a via hole penetrating the buffer layer and the planar layer; forming a passivation layer on the first electrode; and the passivation layer A second electrode is formed thereon, the second electrode being electrically connected to the drain through a via hole penetrating the passivation layer, the flat layer, and the buffer layer.
  • an array substrate in a second aspect, includes: a substrate substrate; a first metal trace and a second metal trace disposed on the base substrate; and the array substrate further includes a substrate disposed thereon a strip-shaped retaining wall between the first metal trace and the second metal trace; wherein the width of the retaining wall is less than or equal to the first metal trace and the second metal trace The spacing between the two.
  • the retaining wall has a continuous structure; or the retaining wall includes at least two sub-retaining walls spaced apart, and the at least two sub-retaining walls are arranged in a strip shape.
  • the array substrate further includes: an insulating film disposed on a surface of the base substrate; a thickness of a partial region on the insulating film is smaller than a thickness of a remaining region, wherein the remaining region is compared to the The protruding portion of the partial region constitutes a strip-shaped retaining wall; the first metal trace and the second metal trace are disposed on a surface of the partial region.
  • a width of the retaining wall is equal to a spacing between the first metal trace and the second metal trace.
  • the array substrate further includes: a source and a drain disposed in the same layer as the first metal trace and the second metal trace, the source and the first metal go a wire electrical connection; the array substrate further includes a gate and a gate insulating layer disposed on a side of the first metal trace and the second metal trace adjacent to the substrate substrate; wherein the gate is close
  • the base substrate is disposed.
  • the array substrate further includes: a buffer layer, a flat layer, a first electrode, a passivation layer and a second electrode which are sequentially disposed on the first metal trace and the second metal trace
  • the first electrode is electrically connected to the second metal trace through a via hole penetrating the buffer layer and the planar layer; the second electrode passes through the passivation layer, the flat
  • the vias on the layer and the buffer layer are electrically connected to the drain.
  • a third aspect provides a display device comprising the array substrate according to any one of the above.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an exemplary embodiment of the present disclosure
  • FIG. 2 is a schematic flow chart of a method for fabricating an array substrate according to some embodiments of the present disclosure
  • 3A is a schematic structural view 1 of forming a retaining wall on a base substrate according to some embodiments of the present disclosure
  • 3B is a schematic structural view 2 of forming a retaining wall on a base substrate according to some embodiments of the present disclosure
  • FIG. 4A is a schematic structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 4B is a top plan view showing the structure of the array substrate illustrated in FIG. 4A;
  • FIG. 4C is another schematic top view of the structure of the array substrate illustrated in FIG. 4A;
  • FIG. 5 is a schematic structural diagram of forming a conductive film on a barrier wall according to some embodiments of the present disclosure
  • FIG. 6 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 7 is a schematic structural diagram of forming a gate and a gate insulating layer on a base substrate according to some embodiments of the present disclosure
  • FIG. 8 is a schematic structural diagram of another array substrate according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 11 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 12 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • an FIC touch product incorporating a touch sensor (Thin Film Transistor, TFT for short) is provided.
  • the touch signal line 20 for transmitting a touch signal is disposed adjacent to the data line (Date) 10 in the pixel region, and the data line 10 is formed on the base substrate 30. At the same time, the touch signal line 20 is formed.
  • the touch signal line 20 and the data line 10 are formed by a patterning process including a coating photoresist, exposure, development, and etching process, in the process of exposing the photoresist, the touch to be formed
  • a patterning process including a coating photoresist, exposure, development, and etching process
  • the touch to be formed The problem of insufficient exposure is easily generated at the position of the gap between the control signal line 20 and the data line 10 to be formed.
  • the material of the photoresist is usually a positive photoresist, if the exposure is insufficient, the etching between the touch signal line 20 and the data line 10 may be incomplete, so that the data line 10 and the adjacent touch signal line 20 are Contact occurs, that is, a short circuit occurs, resulting in a defect.
  • the line width of the formed data line 10 and the touch signal line 20 is narrowed.
  • the narrower data line 10 causes the data line 10 to be easily broken, thereby affecting the normal illumination of a column of pixels connected to the broken data line.
  • Some embodiments of the present disclosure provide a method for fabricating an array substrate, as shown in FIG. 2, including:
  • a strip-shaped retaining wall 40 is formed on the base substrate 30; wherein the width of the retaining wall 40 is less than or equal to the spacing between the first metal trace and the second metal trace to be formed .
  • a first metal trace 10 is formed on one side of the retaining wall 40 in the extending direction
  • a second metal trace 20 is formed on the other side of the retaining wall 40 in the extending direction.
  • the material of the insulating film is not limited, and may be at least one of silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy) as long as it is a non-conductive material.
  • the number of the retaining walls 40 formed is not limited, and may be set according to the design requirements of the product.
  • the retaining wall 40 has a certain thickness, that is, a three-dimensional structure, the first metal trace 10 and the second metal trace 20 can be prevented from occurring during the formation of the first metal trace 10 and the second metal trace 20. For example, contact is not good.
  • the number of the retaining walls 40 is the same as the number of the first metal traces 10 or the second metal traces 20, that is, each of the first metal traces 10 to be formed and each of the second metals A retaining wall 40 is disposed between the wires 20.
  • the thickness of the formed retaining wall 40 is not limited, and the thickness of the retaining wall 40 may be the same as the thickness of the first metal trace 10 to be formed and the second metal trace 20 to be formed, or may be smaller or larger than The thickness of the first metal trace 10 formed and the second metal trace 20 to be formed.
  • first metal trace 10 and the second metal trace 20 are formed in the same process, and the thicknesses of the two are the same.
  • a method for fabricating an array substrate is that a barrier wall 40 is formed on the substrate substrate 30 before the first metal trace 10 and the second metal trace 20 are formed.
  • the width of the wall 40 is less than or equal to the spacing between the first metal trace 10 and the second metal trace 20 to be formed, so that when the first metal trace 10 and the second metal trace 20 are formed again, the retaining wall 40
  • As a three-dimensional blocking structure it is possible to avoid short-circuit defects such as contact between the first metal trace 10 and the second metal trace 20 due to the influence of the manufacturing process.
  • the width of the retaining wall 40 is equal to the spacing between the first metal trace 10 and the second metal trace 20.
  • the steps of S100 above include:
  • an insulating film is formed on the base substrate 30, and a strip-shaped retaining wall 40 is formed by a patterning process.
  • the steps of the above S101 include:
  • a conductive film is formed on the retaining wall 40, as shown in FIG. 4A, and a first metal is formed on one side of the retaining wall 40 along the extending direction by applying a photoresist, exposure, development, and etching process.
  • the trace 10 forms a second metal trace 20 on the other side of the retaining wall 40 in the extending direction.
  • the material of the conductive film is not limited as long as it can conduct electricity.
  • the conductive film may be, for example, at least one of a metal element, an alloy, or a metal oxide.
  • the patterning process described above may include a photoresist coating, exposure, development, and etching process.
  • the photoresist is usually a positive photoresist
  • the first metal trace 10 and the second metal trace 20 are underexposed, the first metal trace 10 and the second after development A portion of the photoresist remains between the metal traces 20, which may result in incomplete etching of the conductive film 50 between the first metal trace 10 and the second metal trace 20, thereby possibly causing the first metal trace 10
  • the second metal trace 20 is in contact with the short circuit, and since the embodiment of the present disclosure forms the retaining wall 40 before forming the first metal trace 10 and the second metal trace 20, thus, when formed on the retaining wall 40
  • the height of the conductive film 50 on the retaining wall 40 is higher than that of the conductive film 50 in other regions, so that after the photoresist is applied, the height of the photoresist above the retaining wall 40 is higher than that of the photoresist in other regions.
  • the exposure of the area facing the retaining wall 40 can be enhanced, so that the area facing the retaining wall 40 is sufficiently exposed, thereby solving the problem between the first metal trace 10 and the second metal trace 20
  • the gap position is underexposed.
  • the formed retaining wall 40 can enhance the exposure at the gap position between the first metal trace 10 and the second metal trace 20, thereby ensuring the line width of the first metal trace 10 and the second metal trace 20
  • the conductive film 50 between the first metal trace 10 and the second metal trace 20 to be formed may be The etch is sufficiently etched, thereby reducing the risk of contact shorting between the first metal trace 10 and the second metal trace 20.
  • the step of forming an insulating film on the base substrate 30 and forming the strip-shaped retaining wall 40 by a patterning process may include:
  • an insulating film 40a is formed on the base substrate 30, and a portion of the insulating film 40a is subjected to a thickness thinning treatment; the remaining portion of the insulating film 40a which has not been subjected to the thickness thinning treatment is thinner than the thickness.
  • the protruding portion of the treated partial portion forms a strip-shaped retaining wall 40.
  • the thickness thinning treatment example may include a process such as dry etching to reduce the thickness of a partial region of the insulating film 40a.
  • the foregoing structure shown in FIG. 3A is to completely remove a partial region in the insulating film, so that the portion left by the insulating film forms a strip-shaped retaining wall 40;
  • the structure shown in FIG. 3B is a portion of the insulating film.
  • the thickness is thinned so that the region of constant thickness protrudes compared to the region where the thickness is thinned, and the protruding portion forms a strip-shaped retaining wall 40.
  • the width of the retaining wall 40 is smaller than the spacing between the first metal trace 10 and the second metal trace 20
  • the conductive film 50 is formed on the retaining wall 40
  • only the retaining wall The height of the conductive film 50 on 40 is higher than other regions, and the height of the conductive film between the first metal trace 10 to be formed and the retaining wall 40 and between the second metal trace 20 to be formed and the retaining wall 40
  • There is no change so there is still a problem of photoresist residue between the first metal trace 10 to be formed and the retaining wall 40 and between the second metal trace 20 to be formed and the retaining wall 40, which may cause formation
  • the conductive film between the first metal trace 10 and the retaining wall 40 and between the second metal trace 20 and the retaining wall 40 to be formed is not completely etched, eventually resulting in the formation of the first metal trace 10 and the second
  • the width of the metal trace 20 is greater than the originally set width, so that the distance between the formed first metal trace 10 and the second metal trace 20 is small.
  • the width of the retaining wall 40 is equal to the spacing between the first metal trace 10 and the second metal trace 20.
  • the width of the retaining wall 40 is equal to the distance between the first metal trace 10 and the second metal trace 20, when the photoresist is formed on the conductive film, the photoresist is located at the first to be formed.
  • the portion between the metal trace 10 and the second metal trace 20 to be formed can be sufficiently exposed, such that the conductive film between the first metal trace 10 to be formed and the second metal trace 20 to be formed can be Completely etching, thereby avoiding increasing the width of the finally formed first metal trace 10 and second metal trace 20, further reducing the short circuit between the first metal trace 10 and the second metal trace 20 due to contact risks of.
  • the step of S100 may further include:
  • the steps of the above S101 may further include:
  • a first metal trace is formed on one side of the retaining wall along the extending direction, and a second metal trace is formed on the other side of the retaining wall in the extending direction by a printing process or an evaporation process.
  • the above strip-shaped retaining wall, the first metal trace, and the second metal trace are formed by a printing process or an evaporation process.
  • the gap between the first metal trace and the second metal trace is not provided with the above-mentioned retaining wall, when the first metal trace and the second metal trace are formed by using a printing process or an evaporation process Since the gap between the first metal trace to be formed and the second metal trace to be formed is set small, the printing material or the evaporation material drips after a slight deviation in the printing process or the evaporation process The gap position is likely to cause the first metal trace to come into contact with the second metal trace.
  • the present disclosure by providing the above-mentioned retaining wall, utilizes a three-dimensional structure having a certain thickness of the retaining wall, so that it is difficult to directly connect the first metal wire and the second wire even when the printing material or the vapor deposition material is dropped on the surface of the retaining wall.
  • the metal traces are connected together to avoid short-circuiting of the first metal trace and the second metal trace.
  • the retaining wall 40 has a continuous structure; or, as shown in FIG. 4C, the retaining wall 40 includes at least two sub-retaining walls 401 spaced apart, and at least two sub-retaining walls 401 are arranged in a strip shape.
  • FIG. 4C only illustrates the case where the retaining wall 40 includes six sub-retaining walls 401 disposed at intervals.
  • the specific number and specific shape of the sub-retaining wall 401 are not limited in the present disclosure, as long as at least two sub-retaining walls 401 are arranged. It can be stripped.
  • the length of the retaining wall 40 is the same as the length of the first metal trace 10 or the second metal trace 20 to be formed.
  • the retaining wall 40 is a continuous unitary structure having a length equal to the length of the first metal trace 10 or the second metal trace 20; for reference to FIG. 4C Structure, along the extending direction of the first metal trace 10 or the second metal trace 20, the length of the strip-shaped whole formed by the spacing between the at least two sub-retaining walls 401 and the adjacent two sub-retaining walls 401 is equal to the first metal The length of the trace 10 or the second metal trace 20.
  • the thickness of the retaining wall 40 is less than or equal to the thickness of the first metal trace 10 and the second metal trace 20.
  • the thickness of the first metal trace 10 and the thickness of the second metal trace 20 are equal.
  • the first metal trace 10 is formed on one side of the retaining wall 40 in the extending direction by the photoresist coating, exposure, development, and etching processes, and the other side of the retaining wall 40 along the extending direction is formed.
  • the second metal trace 20 specifically includes:
  • the source electrode 601 and the drain electrode 602 are formed by applying a photoresist, exposure, development, and etching process, and the first metal trace 10 is formed on the side of the retaining wall 40 along the extending direction.
  • the other side of the wall 40 in the extending direction forms a second metal trace 20, and the source 601 is electrically connected to the first metal trace 10.
  • the source 601 is electrically connected to the first metal trace 10, and the first metal trace 10 is a data line.
  • the portion where the source 601 is electrically connected to the first metal trace 10 is not illustrated in FIG. 6 above because of the limitation of the cross-sectional direction.
  • FIG. 6 the structure in FIG. 6 above is described by taking the case where the retaining wall 40 is directly formed on the base substrate 30 as an example.
  • the strip-shaped retaining wall 40 may also be a portion of the insulating film 40a which is not subjected to the thickness thinning treatment as compared with the portion which has been subjected to the thickness thinning treatment, that is, the source 601 and the drain described above.
  • the pole 602 can also be formed on a partial region subjected to thickness thinning treatment on the insulating film 40a shown in Fig. 3B.
  • the thin film transistor formed on the array substrate may be a top gate thin film transistor or a bottom gate thin film transistor.
  • the above preparation method further includes the following steps:
  • a gate insulating layer and a gate are sequentially formed on the source 601 and the drain 602.
  • the above preparation method further includes the following steps before forming the source 601 and the drain 602:
  • a gate electrode and a gate insulating layer are sequentially formed on the base substrate 30.
  • the first metal trace 10, the second metal trace 20, and the source 601 are simultaneously formed by applying a photoresist, exposure, development, and etching process. And the drain 602, thereby simplifying the fabrication process of the array substrate.
  • the preparation method before the step S100, the preparation method further includes:
  • a gate electrode 70 and a gate insulating layer (GI) 80 are sequentially formed on the base substrate 30.
  • the material of the gate electrode 70 is not limited as long as it can conduct electricity.
  • the material of the gate 70 may be at least one of a metal element, an alloy, and a metal oxide.
  • the material of the gate insulating layer 80 is not limited, and may be at least one of silicon nitride, silicon oxide, or silicon oxynitride, as long as it is an insulating material.
  • the thin film transistor formed at this time is a bottom gate type. Thin film transistor.
  • the thin film transistor further includes an active layer (the active layer is not illustrated in the above embodiments of the present disclosure), and the active layer is in contact with both the source 601 and the drain 602.
  • the active layer may be formed before the formation of the retaining wall 40; or, after the retaining wall 40 is formed, and before the first metal trace 10 and the second metal trace 20 are formed, an active layer may be formed; It is of course also possible to form the active layer after forming the first metal trace 10 and the second metal trace 20.
  • the preparation method further includes:
  • a buffer layer 90 and a flat layer 100 are sequentially formed on the first metal trace 10 and the second metal trace.
  • the material of the buffer layer 90 and the material of the flat layer 100 are both insulating materials.
  • the material of the buffer layer 90 may be, for example, at least one of SiO 2 (silica), TiO 2 (titanium dioxide), or CeO 2 (ceria).
  • the material of the flat layer 100 may be, for example, a resin (Resin).
  • the buffer layer 90 and the flat layer 100 may be exemplified by a vapor deposition method.
  • a first electrode 110 is formed on the flat layer 100.
  • the first electrode 110 is connected to the second metal trace 20 through a via hole penetrating the buffer layer 90 and the flat layer 100.
  • the first electrode 110 may be configured by a plurality of block-shaped sub-electrodes. By time-multiplexing the first electrode 110, the first electrode 110 may be used for both display and touch control. The function.
  • the first electrode 110 is electrically connected to the second metal trace 20, and the second metal trace 20 is a touch signal line for transmitting a touch signal to the first electrode 110.
  • the first electrode 110 may be a common electrode (Vcom).
  • the first electrode 110 may be a transparent electrode, and the material of the first electrode 110 may be, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or At least one of FTO (Fluorine-Doped Tin Oxide).
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • FTO Fluorine-Doped Tin Oxide
  • a passivation layer 120 (Passivation, abbreviated as PVX) is formed on the first electrode 110.
  • the material of the passivation layer 120 is not limited, and may be, for example, at least one of silicon nitride, silicon oxide, or silicon oxynitride.
  • the formation process of the passivation layer 120 is not limited, and may be formed, for example, by a sputtering method or a deposition method.
  • a second electrode 130 is formed on the passivation layer 120.
  • the second electrode 130 is electrically connected to the drain 602 through a via hole penetrating through the passivation layer 120, the flat layer 100, and the buffer layer 90.
  • the first electrode 110 is composed of a plurality of bulk sub-electrodes, and thus the second electrode 130 can be electrically connected to the drain 602 through a gap between the bulk sub-electrodes in the first electrode 110.
  • the via holes penetrating through the passivation layer 120, the flat layer 100, and the buffer layer 90 do not penetrate the first electrode 110. Therefore, limited to the cross-sectional direction in FIG. 11, the vias penetrating the passivation layer 120, the flat layer 100, and the buffer layer 90 may not be illustrated.
  • the second electrode 130 is electrically connected to the drain 602 through via holes penetrating the passivation layer 120, the planarization layer 100, and the buffer layer 90.
  • the material of the second electrode 130 may be a transparent material, and may be, for example, at least one of ITO, IZO, or FTO.
  • the material of the second electrode 130 and the material of the first electrode 110 may be the same or different.
  • the second electrode 130 is electrically connected to the drain 602, and the second electrode 130 is a pixel electrode.
  • the touch electrodes ie, the first electrodes 110
  • the in-cell touch substrate can be formed, so that the thickness of the array substrate can be reduced.
  • the array substrate includes:
  • first metal traces 10 and second metal traces 20 disposed on the base substrate 30; strip-shaped retaining walls disposed between the first metal traces 10 and the second metal traces 20 40; wherein the width of the retaining wall 40 is less than or equal to the spacing between the first metal trace 10 and the second metal trace 20.
  • the array substrate further includes an insulating film 40a disposed on the surface of the base substrate 30 as shown in FIG. 3B; wherein a thickness of a partial region on the insulating film 40a is smaller than a thickness of the remaining region, and the remaining region The portion protruding from the partial region constitutes the strip-shaped retaining wall 40 described above; the first metal trace 10 and the second metal trace 20 are disposed on the surface of the partial region.
  • the above-mentioned retaining wall 40 has a continuous structure; or, as shown in FIG. 4C, the retaining wall 40 includes at least two sub-retaining walls 401 spaced apart, and at least two sub-retaining walls 401 are arranged. In a strip.
  • the present disclosure does not limit the material of the retaining wall 40 as long as it is an insulating non-conductive material, and may be, for example, at least one of silicon nitride, silicon oxide, or silicon oxynitride.
  • the function of the retaining wall 40 is to prevent the first metal trace 10 and the second metal trace 20 from being bad during the formation of the first metal trace 10 and the second metal trace 20, for example, Specifically, the formed first metal trace 10 and the second metal are avoided by sufficiently exposing the photoresist at the gap position between the first metal trace 10 to be formed and the second metal trace 20 to be formed. The line 20 is bad.
  • the length of the retaining wall 40 is the same as the length of the first metal trace 10 or the second metal trace 20 to be formed.
  • the thickness of the retaining wall 40 is not limited.
  • the thickness of the retaining wall 40 may be the same as the thickness of the first metal trace 10 and the second metal trace 20, or may be smaller or larger than the first metal trace 10 and the second.
  • the thickness of the metal trace 20 is not limited. The thickness of the retaining wall 40 may be the same as the thickness of the first metal trace 10 and the second metal trace 20, or may be smaller or larger than the first metal trace 10 and the second. The thickness of the metal trace 20.
  • the thickness of the first metal trace 10 and the thickness of the second metal trace 20 are equal.
  • the materials of the first metal trace 10 and the second metal trace 20 are not limited as long as they can conduct electricity.
  • the material may be, for example, at least one of a metal element, an alloy, or a metal oxide.
  • the first metal trace 10 and the second metal trace 20 are formed by a patterning process including a coating photoresist, an exposure, a development, and an etch process, and an embodiment of the present disclosure provides an array substrate.
  • a retaining wall 40 is formed on the base substrate 30, and the width of the retaining wall 40 is less than or equal to the first metal trace 10 to be formed and the to-be-formed a spacing between the second metal traces 20, such that when a conductive film is formed (the conductive film is used to form the first metal trace 10 and the second metal trace 20 by etching), the conductive film is overlaid on the retaining wall 40 The height will be higher than that of other areas.
  • the height of the photoresist above the retaining wall 40 is higher than the height of the photoresist in other regions, so that the retaining wall 40 can be enhanced in the exposure process.
  • the exposure of the photoresist in the region causes the photoresist in the region facing the barrier 40 to be sufficiently exposed, thereby solving the problem between the first metal trace 10 to be formed and the second metal trace 20 to be formed.
  • the photoresist is usually a positive photoresist
  • the photoresist at the gap between the first metal trace 10 to be formed and the second metal trace 20 to be formed is insufficiently exposed
  • the photoresist After the development process, a portion of the photoresist remains between the first metal trace 10 to be formed and the second metal trace 20 to be formed, which causes the first metal trace 10 to be formed to be formed.
  • the conductive film between the second metal traces 20 is incompletely etched, which easily causes a contact short circuit between the formed first metal traces 10 and the second metal traces 20.
  • the exposure of the photoresist at the gap position between the first metal trace 10 to be formed and the second metal trace 20 to be formed can be enhanced by providing the retaining wall 40, thereby ensuring
  • the first metal trace 10 and the second metal trace 20 to be formed have a suitable line width, residual photolithography between the first metal trace 10 to be formed and the second metal trace 20 to be formed is avoided.
  • a film, so that when the conductive film is etched, the conductive film between the first metal trace 10 to be formed and the second metal trace 20 to be formed can be sufficiently etched, thereby reducing the first after formation. There is a risk of contact shorting between the metal trace 10 and the second metal trace 20.
  • the width of the retaining wall 40 is smaller than the spacing between the first metal trace 10 and the second metal trace 20
  • the conductive film on the retaining wall 40 has a higher height than other regions.
  • the height of the conductive film between the first metal trace 10 to be formed and the retaining wall 40 and between the second metal trace 20 to be formed and the retaining wall 40 does not change, and thus the first metal trace to be formed There is still a problem of photoresist residue between the 10 and the retaining wall 40 and between the second metal trace 20 and the retaining wall 40 to be formed, so that the first metal trace 10 and the retaining wall 40 to be formed may be formed.
  • the conductive film between the second metal trace 20 and the retaining wall 40 to be formed is not completely etched, resulting in a wide width of the first metal trace 10 and the second metal trace 20 formed, that is, the first The distance between the metal trace 10 and the second metal trace 20 is small.
  • the distance between the first metal trace 10 and the second metal trace 20 is small, the signal transmitted on the first metal trace 10 and the signal transmitted on the second metal trace 20 are easily interfered with each other.
  • the width of the retaining wall 40 is equal to the spacing between the first metal trace 10 and the second metal trace 20.
  • the width of the retaining wall 40 is equal to the distance between the first metal trace 10 and the second metal trace 20
  • the first metal trace 10 to be formed and the second metal trace 20 to be formed are The photoresist can be sufficiently exposed, so that the conductive film between the first metal trace 10 to be formed and the second metal trace 20 to be formed can be completely etched, thereby avoiding the increase of the first after formation.
  • the width of the metal trace 10 and the second metal trace 20 further reduces the risk of shorting of the first metal trace 10 and the second metal trace 20 due to contact.
  • the thickness of the retaining wall 40 is less than or equal to the thickness of the first metal trace 10 and the second metal trace 20.
  • the thickness of the first metal trace 10 is equal to the thickness of the second metal trace 20 .
  • the array substrate further includes a source 601 and a drain 602 disposed in the same layer as the first metal trace 10 and the second metal trace 20, and the source 601 and the first A metal trace 10 is electrically connected; a gate 70 and a gate insulating layer 80 disposed on a side of the first metal trace 10 and the second metal trace 20 near the base substrate 30; wherein the gate 70 is adjacent to the base substrate 30 Settings.
  • the above thin film transistor further includes an active layer (the active layer is not illustrated in all the drawings in the embodiment of the present disclosure), and the active layer is in contact with the source 601 and the drain 602.
  • the active layer may be formed before the formation of the retaining wall 40; or, after the retaining wall 40 is formed, and before the first metal trace 10 and the second metal trace 20 are formed, an active layer may be formed; It is of course also possible to form the active layer after forming the first metal trace 10 and the second metal trace 20.
  • the material of the gate electrode 70 is not limited as long as it can conduct electricity.
  • the material of the gate 70 may be at least one of a metal element, an alloy, and a metal oxide.
  • the material of the gate insulating layer 80 is not limited as long as it is an insulating material, and may be, for example, at least one of silicon nitride, silicon oxide, or silicon oxynitride.
  • the source 601 is electrically connected to the first metal trace 10, and the first metal trace 10 is specifically a data line.
  • the source electrode 601 and the drain electrode 602 are disposed on the gate electrode 70 and the gate insulating layer 80, and the formed thin film transistor is a bottom gate type thin film transistor, but the embodiment of the present disclosure is not limited thereto.
  • the thin film transistor in the array substrate may also be a top gate type thin film transistor.
  • a gate insulating layer 80 and a gate electrode 70 are sequentially formed on the source electrode 601 and the drain electrode 602.
  • the source 601 and the drain 602 are disposed in the same layer as the first metal trace 10 and the second metal trace 20, the first metal trace 10 and the second metal trace 20 may be simultaneously formed.
  • the source 601 and the drain 602 are used to simplify the fabrication process of the array substrate.
  • the array substrate further includes:
  • the vias on layer 90 and planar layer 100 are electrically coupled to second metal traces 20; second electrodes 130 are electrically coupled to drain 602 by vias through passivation layer 120, planar layer 100, and buffer layer 90.
  • the materials of the buffer layer 90, the planarization layer 100, and the passivation layer 120 are all insulating materials.
  • the material of the buffer layer 90 may be, for example, at least one of SiO 2 , TiO 2 or CeO 2 .
  • the material of the flat layer 100 may be, for example, a resin.
  • the material of the passivation layer 120 may be, for example, at least one of silicon nitride, silicon oxide, or silicon oxynitride.
  • first electrode 110 and the second electrode 130 may all be transparent electrodes, and the materials of the first electrode 110 and the second electrode 130 may be at least one of ITO, IZO or FTO.
  • the material of the second electrode 130 may be the same as or different from the material of the first electrode 110.
  • the first electrode 110 may be a common electrode (Vcom)
  • the second electrode 130 is electrically connected to the drain 602
  • the second electrode 130 is a pixel electrode.
  • the first electrode 110 is composed of a plurality of block-shaped sub-electrodes. By time-multiplexing the first electrode 110, the first electrode 110 has a function of being used for both display and touch.
  • the first electrode 110 is electrically connected to the second metal trace 20, and the second metal trace 20 is a touch signal line for transmitting a touch signal to the first electrode 110.
  • the second electrode 130 may be electrically connected to the drain 602 through a gap between the bulk sub-electrodes in the first electrode 110.
  • the touch electrodes ie, the first electrodes 110
  • the touch electrodes are built in the array substrate to form an in-cell touch substrate, thereby reducing the thickness of the array substrate.
  • Embodiments of the present disclosure also provide a display device including the above array substrate.
  • the display device may be a liquid crystal display device or an organic electroluminescent diode display device.
  • the display device may include, in addition to the array substrate, a pair of cassette substrates facing the array substrate and a liquid crystal layer disposed between the array substrate and the counter substrate.
  • an organic electroluminescent layer is further formed on the array substrate.
  • the display device may further include a package substrate for packaging the array substrate described above.
  • the above display device may be any device that displays an image regardless of motion (eg, video) or fixed (eg, still image) and is either text or picture. More specifically, it is contemplated that the described embodiments can be implemented in or associated with a variety of electronic devices including, for example, but not limited to, mobile phones, wireless devices, personal data assistants (PADs).
  • PDAs personal data assistants
  • Portable Android Device Handheld or Portable Computer
  • GPS Global Positioning System
  • Camera MP4 (full name MPEG-4 Part 14) video player, camera, game console, watch , clock, calculator, television monitor, flat panel display, computer monitor, car display (eg, odometer display, etc.), navigator, cockpit controller and/or display, camera view display (eg, rear view in the vehicle) Camera display), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (eg, displays for images of a piece of jewelry).
  • the display device may also be a display panel.
  • an embodiment of the present disclosure provides a display device in which a retaining wall 40 is formed on a base substrate 30 before the first metal trace 10 and the second metal trace 20 are formed, and the width of the retaining wall 40 is smaller than Or equal to the spacing between the first metal trace 10 and the second metal trace 20 to be formed, and thus when a conductive film is formed (the conductive film is used to form the first metal trace 10 and the second metal trace by etching) 20), the height of the conductive film on the retaining wall 40 is higher than that of the conductive film in other regions, so that after coating the photoresist, the height of the photoresist above the retaining wall 40 is also higher than the height of the photoresist in other regions.
  • the exposure of the photoresist in the region facing the retaining wall 40 can be enhanced, so that the photoresist in the region facing the retaining wall 40 is sufficiently exposed, thereby solving the first metal to be formed.

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Abstract

提供一种阵列基板的制备方法，所述阵列基板的制备方法包括：在衬底基板上形成条状的挡墙；其中，所述挡墙的宽度小于或等于待形成的第一金属走线和第二金属走线之间的间距；在所述挡墙沿延伸方向的一侧形成所述第一金属走线、在所述挡墙沿延伸方向的另一侧形成所述第二金属走线。还提供一种阵列基板、显示装置。

Description

阵列基板及其制备方法、显示装置
本申请要求于2017年06月09日提交中国专利局、申请号为201710437465.7、申请名称为“一种阵列基板及其制备方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
随着显示技术的发展，触控屏(Touch Panel)技术进入快速发展时期，触控屏按照触控传感器的设置位置可以分为外挂式触控屏和内嵌式触控屏，内嵌式触控屏可以分为：外置式触摸屏(On cell Touch Panel)和嵌入式触摸屏(In Cell Touch Panel)。其中，In Cell触控屏又可分为复合内嵌式(Hybrid In Cell，简称HIC)触控屏和完全内嵌式(Full In Cell，简称FIC)触控屏。
公开内容
本公开提供如下技术方案：
第一方面、提供一种阵列基板的制备方法，所述制备方法包括：在衬底基板上形成条状的挡墙；其中，所述挡墙的宽度小于或等于待形成的第一金属走线和第二金属走线之间的间距；在所述挡墙上形成导电薄膜，并通过涂布光刻胶、曝光、显影及刻蚀工艺在所述挡墙沿延伸方向的一侧形成所述第一金属走线、在所述挡墙沿延伸方向的另一侧形成所述第二金属走线。
可选的，其中，所述在衬底基板上形成条状的挡墙，包括：在衬底基板上形成绝缘薄膜，并通过构图工艺形成条状的挡墙；所述在所述挡墙沿延伸方向的一侧形成所述第一金属走线、在所述挡墙沿延伸方向的另一侧形成所述第二金属走线，包括：一侧形成所述第一金属走线、在所述挡墙沿延伸方向的另一侧形成所述第二金属走线。
可选的，其中，所述在衬底基板上形成条状的挡墙，包括：采用打印工艺或蒸镀工艺，在衬底基板上形成条状的挡墙；所述在所述挡墙沿延伸 方向的一侧形成所述第一金属走线、在所述挡墙沿延伸方向的另一侧形成所述第二金属走线，包括：采用打印工艺或蒸镀工艺，在所述挡墙沿延伸方向的一侧形成所述第一金属走线、在所述挡墙沿延伸方向的另一侧形成所述第二金属走线。
可选的，其中，所述挡墙具有连续的结构；或者，所述挡墙包括间隔设置的至少两个子挡墙，所述至少两个子挡墙排列成条状。
可选的，其中，所述在衬底基板上形成绝缘薄膜，并通过构图工艺形成条状的挡墙，包括：在衬底基板上形成绝缘薄膜，对所述绝缘薄膜的部分区域进行厚度减薄处理；所述绝缘薄膜上未经过所述厚度减薄处理的其余区域相比于经过所述厚度减薄处理的所述部分区域突出的部分形成条状的挡墙。
可选的，其中，所述挡墙的宽度等于所述第一金属走线和所述第二金属走线之间的间距。
可选的，其中，所述挡墙的厚度小于或等于所述第一金属走线和所述第二金属走线的厚度。
可选的，其中，所述通过涂布光刻胶、曝光、显影及刻蚀工艺在所述挡墙沿延伸方向的两侧分别形成第一金属走线和第二金属走线，包括：通过涂布光刻胶、曝光、显影及刻蚀工艺形成源极和漏极，并在所述挡墙沿延伸方向的一侧形成第一金属走线、在所述挡墙沿延伸方向的另一侧形成第二金属走线，所述源极与所述第一金属走线电连接。
可选的，其中，所述在衬底基板上形成绝缘薄膜之前，所述制备方法还包括：在衬底基板上依次形成栅极以及栅绝缘层；在形成所述第一金属走线和所述第二金属走线之后，所述制备方法还包括：在所述第一金属走线和所述第二金属走线上依次形成缓冲层和平坦层；在所述平坦层上形成第一电极，所述第一电极通过贯穿所述缓冲层和所述平坦层上的过孔与所述第二金属走线电连接；在所述第一电极上形成钝化层；在所述钝化层上形成第二电极，所述第二电极通过贯穿所述钝化层、所述平坦层和所述缓冲层上的过孔与所述漏极电连接。
第二方面、提供一种阵列基板，所述阵列基板包括：衬底基板；设置在所述衬底基板上的第一金属走线和第二金属走线；所述阵列基板还包括设置在所述第一金属走线和所述第二金属走线之间的条状的挡墙；其中，所述挡墙的宽度小于或等于所述第一金属走线和所述第二金属走线之间的 间距。
可选的，其中，所述挡墙具有连续的结构；或者，所述挡墙包括间隔设置的至少两个子挡墙，所述至少两个子挡墙排列成条状。
可选的，其中，所述阵列基板还包括：设置在所述衬底基板表面的绝缘薄膜；所述绝缘薄膜上的部分区域的厚度小于其余区域的厚度，所述其余区域相比于所述部分区域突出的部分构成条状的挡墙；所述第一金属走线和所述第二金属走线设置在所述部分区域的表面。
可选的，其中，所述挡墙的宽度等于所述第一金属走线和所述第二金属走线之间的间距。
可选的，其中，所述阵列基板还包括：与所述第一金属走线和所述第二金属走线同层设置的源极和漏极，所述源极与所述第一金属走线电连接；所述阵列基板还包括设置在所述第一金属走线和所述第二金属走线靠近所述衬底基板一侧的栅极和栅绝缘层；其中，所述栅极靠近所述衬底基板设置。
可选的，其中，所述阵列基板还包括：依次设置在所述第一金属走线和所述第二金属走线上的缓冲层、平坦层、第一电极、钝化层和第二电极；其中，所述第一电极通过贯穿所述缓冲层和所述平坦层上的过孔与所述第二金属走线电连接；所述第二电极通过贯穿所述钝化层、所述平坦层和所述缓冲层上的过孔与所述漏极电连接。
第三方面、提供一种显示装置，所述显示装置包括上述任一项所述的阵列基板。
附图说明
图1为本公开的示例性实施例提供的一种阵列基板的结构示意图；
图2为本公开的一些实施例提供的一种阵列基板的制备方法的流程示意图；
图3A为本公开的一些实施例提供的一种在衬底基板上形成挡墙的结构示意图一；
图3B为本公开的一些实施例提供的一种在衬底基板上形成挡墙的结构示意图二；
图4A为本公开的一些实施例提供的一种阵列基板的结构示意图；
图4B为图4A示意出的阵列基板结构的一种俯视结构示意图；
图4C为图4A示意出的阵列基板结构的另一种俯视结构示意图；
图5为本公开的一些实施例提供的一种在挡墙上形成导电薄膜的结构示意图；
图6为本公开的一些实施例提供的再一种阵列基板的结构示意图；
图7为本公开的一些实施例提供的一种在衬底基板上形成栅极和栅绝缘层的结构示意图；
图8为本公开的一些实施例提供的另一种阵列基板的结构示意图；
图9为本公开的一些实施例提供的又一种阵列基板的结构示意图；
图10为本公开的一些实施例提供的又一种阵列基板的结构示意图；
图11为本公开的一些实施例提供的又一种阵列基板的结构示意图；
图12为本公开的一些实施例提供的又一种阵列基板的结构示意图。
具体实施方式
在本公开的一些示例性的实施例中，为了降低显示屏的厚度，提供了一种将触控传感器(Touch Sensor)内置于薄膜晶体管(Thin Film Transistor，简称TFT)的FIC触控产品。
如图1所示，在TDDI(Touch and Display Driver Integration，触控技术与显示驱动器集成于一体)型的触控产品中，由于还需要给触控信号线传输触控信号，因此，为便于触控信号的传输，一般在像素区域内将用于传输触控信号(例如为Tx信号)的触控信号线20与数据线(Date)10相邻设置，在衬底基板30上形成数据线10的同时形成触控信号线20。
然而，对于高分辨率(Pixels Per Inch，简称PPI)的触控产品，由于触控信号线20与数据线10之间的间隙(Space)的宽度很小，在制作触控信号线20与数据线10时容易产生不良。
示例的，当通过包括有涂布光刻胶、曝光、显影及刻蚀工艺的构图工艺形成触控信号线20与数据线10时，在对光刻胶曝光的过程中，在待形成的触控信号线20与待形成的数据线10之间的间隙位置处容易产生曝光不足的问题。
由于光刻胶的材料通常为正性光刻胶时，如果曝光不足，会导致触控信号线20与数据线10之间刻蚀不彻底，使得数据线10与相邻的触控信号线20发生接触，即发生短路(short)，从而产生不良。
如果间隙位置处的光刻胶被过曝光(即原本预设的曝光区域被扩大)，又会导致形成的数据线10和触控信号线20的线宽较窄。这样在fanout(扇出)区内，由于数据线10更窄，会导致数据线10极易发生断裂，进而影 响了与断裂的数据线相连的一列像素的正常发光。
本公开的一些实施例提供了一种阵列基板的制备方法，如图2所示，包括：
S100、如图3A所示，在衬底基板30上形成条状的挡墙40；其中，挡墙40的宽度小于或等于待形成的第一金属走线和第二金属走线之间的间距。
S101、如图4A所示，在挡墙40沿延伸方向的一侧形成第一金属走线10、在挡墙40沿延伸方向的另一侧形成第二金属走线20。
其中，对于绝缘薄膜的材料不进行限定，只要是非导电材料即可，例如可以是氮化硅(SiNx)、氧化硅(SiOx)或氮氧化硅(SiOxNy)中的至少一种。
需要说明的是，对于形成的挡墙40的数量不进行限定，可以根据产品的设计需要进行设置。
由于挡墙40具有一定的厚度，即是一个立体的结构，能够在形成第一金属走线10和第二金属走线20的过程中避免第一金属走线10与第二金属走线20发生例如接触等不良。
因此，在一些实施例中，挡墙40的数量与第一金属走线10或第二金属走线20的数量相同，即在待形成的每条第一金属走线10与每条第二金属走线20之间都设置有挡墙40。此外，对于形成的挡墙40的厚度不进行限定，挡墙40的厚度可以与待形成的第一金属走线10和待形成的第二金属走线20的厚度相同，也可以小于或大于待形成的第一金属走线10和待形成的第二金属走线20的厚度。
这里，第一金属走线10和第二金属走线20由于通常在同一工艺下形成，故二者的厚度相同。
基于此，本公开一些实施例提供的一种阵列基板的制备方法，由于在形成第一金属走线10和第二金属走线20之前，先在衬底基板30上形成挡墙40，且挡墙40的宽度小于或等于待形成的第一金属走线10和第二金属走线20之间的间距，因而当再形成第一金属走线10和第二金属走线20时，挡墙40作为一个立体的阻挡结构，能够避免由于制作工艺的影响使得第一金属走线10和第二金属走线20发生例如相接触等短路不良。
在一些实施例中，挡墙40的宽度等于第一金属走线10和第二金属走线20之间的间距。
在一些实施例中，上述S100的步骤包括：
参考图3A所示，在衬底基板30上形成绝缘薄膜，并通过构图工艺形成条状的挡墙40。
上述S101的步骤包括：
如图5所示，在挡墙40上形成导电薄膜，参考图4A所示，并通过涂布光刻胶、曝光、显影及刻蚀工艺在挡墙40沿延伸方向的一侧形成第一金属走线10、在挡墙40沿延伸方向的另一侧形成第二金属走线20。
需要说明的是，对于导电薄膜的材料不进行限定，只要能够导电即可。例如，该导电薄膜例如可以是金属单质、合金或金属氧化物中的至少一种。
上述的构图工艺可以包括涂布光刻胶、曝光、显影以及刻蚀工艺。
这样一来，由于光刻胶通常为正性光刻胶，若第一金属走线10和第二金属走线20之间的间隙位置曝光不足，则显影后第一金属走线10和第二金属走线20之间会残留部分光刻胶，这样便会导致第一金属走线10和第二金属走线20之间的导电薄膜50刻蚀不彻底，从而可能导致第一金属走线10和第二金属走线20接触短路，而由于本公开实施例在形成第一金属走线10和第二金属走线20之前先形成了挡墙40，这样一来，当在挡墙40上形成导电薄膜50时，挡墙40上导电薄膜50的高度会高于其它区域的导电薄膜50，这样在涂布光刻胶后，挡墙40上方光刻胶的高度高于其它区域光刻胶的高度，因而在曝光工序中，可以增强挡墙40正对的区域的曝光，使挡墙40正对的区域被充分曝光，从而解决了第一金属走线10和第二金属走线20之间的间隙位置曝光不足的问题。
即，形成的挡墙40可以增强第一金属走线10和第二金属走线20之间的间隙位置处的曝光，从而可以在确保第一金属走线10和第二金属走线20线宽的情况下，避免了第一金属走线10和第二金属走线20之间残留光刻胶，因而待形成的第一金属走线10和第二金属走线20之间的导电薄膜50可以被充分刻蚀，进而降低了第一金属走线10和第二金属走线20接触短路的风险。在一些实施例中，在衬底基板30上形成绝缘薄膜，并通过构图工艺形成条状的挡墙40的步骤可以包括：
参考图3B所示，在衬底基板30上形成绝缘薄膜40a，对绝缘薄膜40a的部分区域进行厚度减薄处理；绝缘薄膜40a上未经过厚度减薄处理的其余区域相比于经过厚度减薄处理的部分区域突出的部分形成条状的挡墙40。
这里，厚度减薄处理示例的可以包括干法刻蚀等工艺，以降低绝缘薄膜40a的部分区域厚度。
即，前述图3A所示的结构为将绝缘薄膜中的部分区域完全去除，使得绝缘薄膜留下的部分形成条状的挡墙40；图3B所示的结构为将绝缘薄膜中的部分区域的厚度进行减薄，以使得厚度不变的区域相比于厚度减薄的区域突出，突出的部分形成条状的挡墙40。
在本公开的一些实施例中，当挡墙40的宽度小于第一金属走线10与第二金属走线20之间的间距时，则在挡墙40上形成导电薄膜50时，只有挡墙40上的导电薄膜50的高度高于其它区域，而待形成的第一金属走线10与挡墙40之间以及待形成的第二金属走线20与挡墙40之间的导电薄膜的高度没有变化，因而待形成的第一金属走线10与挡墙40之间以及待形成的第二金属走线20与挡墙40之间仍然会存在光刻胶残留的问题，从而可能使得待形成的第一金属走线10与挡墙40之间以及待形成的第二金属走线20与挡墙40之间的导电薄膜刻蚀不彻底，最终导致形成的第一金属走线10和第二金属走线20的宽度大于原本设定的宽度，进而使得形成后的第一金属走线10与第二金属走线20之间的距离较小。
当第一金属走线10与第二金属走线20之间的距离较小时，容易导致第一金属走线10上传输的信号与第二金属走线20上传输的信号发生相互干扰。因此，在一些实施例中，参考图4A-4C所示，挡墙40的宽度等于第一金属走线10与第二金属走线20之间的间距。
这样一来，由于挡墙40的宽度等于第一金属走线10与第二金属走线20之间的间距，因而光刻胶形成在导电薄膜上时，光刻胶中位于待形成的第一金属走线10与待形成的第二金属走线20之间的部分能够得到充分曝光，这样待形成的第一金属走线10与待形成的第二金属走线20之间的导电薄膜可以被完全刻蚀，从而避免增加最终形成的第一金属走线10和第二金属走线20的宽度，进一步降低了第一金属走线10与第二金属走线20之间由于发生接触而导致短路的风险。
在一些实施例中，上述S100的步骤或者可以包括：
采用打印工艺或蒸镀工艺，在衬底基板上形成条状的挡墙；
上述S101的步骤或者可以包括：
采用打印工艺或蒸镀工艺，在挡墙沿延伸方向的一侧形成第一金属走线、在挡墙沿延伸方向的另一侧形成第二金属走线。
即，采用打印工艺或者蒸镀工艺形成以上的条状的挡墙、第一金属走线、第二金属走线。
其中，打印工艺或者蒸镀工艺的具体工艺过程可参见相关技术，本公开对此不再赘述。
这样一来，如果第一金属走线与第二金属走线之间的间隙没有设置上述的挡墙，在采用打印工艺或蒸镀工艺形成上述的第一金属走线、第二金属走线时，由于待形成的第一金属走线与待形成的第二金属走线之间的间隙被设置得很小，当打印工艺或蒸镀工艺发生轻微偏差后，打印材料或蒸镀材料滴落在间隙位置处容易导致第一金属走线与第二金属走线发生接触。
而本公开通过设置上述的挡墙，利用挡墙具有的一定厚度的立体结构，使得即使当打印材料或蒸镀材料滴落在挡墙表面时，也难以直接将第一金属走线与第二金属走线连接在一起，从而避免第一金属走线与第二金属走线发生短路不良。
进一步的，如图4B所示，挡墙40具有连续的结构；或者，如图4C所示，挡墙40包括间隔设置的至少两个子挡墙401，至少两个子挡墙401排列成条状。
其中，以上图4C中仅示意出挡墙40包括间隔设置的6个子挡墙401的情况，本公开对于子挡墙401的具体数量及具体形状均不作限定，只要使得至少两个子挡墙401排列成条状即可。
在一些实施例中，参考图4B或图4C所示，挡墙40的长度与待形成的第一金属走线10或第二金属走线20的长度相同。
即，对于参考图4B所示的结构，挡墙40为一个连续的整体结构，该整体结构的长度等于第一金属走线10或第二金属走线20的长度；对于参考图4C所示的结构，沿第一金属走线10或第二金属走线20的延伸方向，由至少两个子挡墙401以及相邻两个子挡墙401之间的间距构成的条状整体的长度等于第一金属走线10或第二金属走线20的长度。在一些实施例中，为了确保形成的阵列基板表面的平整度，挡墙40的厚度小于或等于第一金属走线10和第二金属走线20的厚度。
其中，第一金属走线10的厚度和第二金属走线20的厚度相等。
在一些实施例中，通过涂布光刻胶、曝光、显影及刻蚀工艺在挡墙40沿延伸方向的一侧形成第一金属走线10、在挡墙40沿延伸方向的另一侧形成第二金属走线20，具体包括：
如图6所示，通过涂布光刻胶、曝光、显影及刻蚀工艺形成源极601和漏极602，并在挡墙40沿延伸方向的一侧形成第一金属走线10、在挡墙40沿延伸方向的另一侧形成第二金属走线20，源极601与第一金属走线10电连接。其中，源极601与第一金属走线10电连接，此时第一金属走线10为数据线。这里，因为剖视方向的限制，源极601与第一金属走线10电连接的部分在以上图6中未示意出。
此外，以上图6中的结构仅以挡墙40直接形成在衬底基板30上为例进行说明。
参考图3B所示，条状的挡墙40还可以是绝缘薄膜40a上未经过厚度减薄处理的其余区域相比于经过厚度减薄处理的部分区域突出的部分，即上述源极601和漏极602还可以形成在参考图3B所示的绝缘薄膜40a上经过厚度减薄处理的部分区域上。
需要说明的是，本公开实施例提供的阵列基板上形成的薄膜晶体管可以是顶栅型薄膜晶体管，也可以是底栅型薄膜晶体管。
当薄膜晶体管是顶栅型薄膜晶体管时，形成源极601和漏极602后，上述的制备方法还包括以下步骤：
在源极601和漏极602上依次形成栅绝缘层和栅极。
当薄膜晶体管是底栅型薄膜晶体管时，在形成源极601和漏极602之前，上述的制备方法还包括以下步骤：
在衬底基板30上依次形成栅极和栅绝缘层。
在一些实施例中，在挡墙40上形成导电薄膜50后，通过涂布光刻胶、曝光、显影以及刻蚀工艺同时形成第一金属走线10、第二金属走线20、源极601和漏极602，从而可以简化阵列基板的制作工艺。
在一些实施例中，在上述步骤S100之前，上述制备方法还包括：
如图7所示，在衬底基板30上依次形成栅极70以及栅绝缘层(Gate Insulator，简称GI)80。
其中，对于栅极70的材料不进行限定，只要能够导电即可。
示例的，栅极70的材料可以是金属单质、合金和金属氧化物中的至少一种。
此处，对于栅绝缘层80的材料不进行限定，只要是绝缘材料即可，例如可以是氮化硅、氧化硅或氮氧化硅中的至少一种。
需要说明的是，在形成第一金属走线10、第二金属走线20、源极601 和漏极602之前，形成栅极70和栅绝缘层80，此时形成的薄膜晶体管是底栅型薄膜晶体管。
薄膜晶体管还包括有源层(本公开实施例以上各附图中均未示意出有源层)，有源层与源极601、漏极602均接触。
这里，可以在形成挡墙40之前形成有源层；或者，也可以在形成挡墙40之后，且在形成第一金属走线10和第二金属走线20之前形成有源层；再或者，当然也可以在形成第一金属走线10和第二金属走线20之后形成有源层。
在步骤S101之后，上述制备方法还包括：
S200、如图8所示，在第一金属走线10和所述第二金属走线上依次形成缓冲层(Buffer)90和平坦层100。
其中，缓冲层90的材料和平坦层100的材料都是绝缘材料。
缓冲层90的材料例如可以是SiO 2(二氧化硅)、TiO 2(二氧化钛)或CeO 2(二氧化铈)中的至少一种。
平坦层100的材料例如可以是树脂(Resin)。
此处，缓冲层90和平坦层100示例的可以通过气相沉积法形成。
S201、如图9所示，在平坦层100上形成第一电极110，第一电极110通过贯穿缓冲层90和平坦层100上的过孔与第二金属走线20相连接。
其中，第一电极110示例的可以由多个块状子电极构成，通过对第一电极110分时复用，可以使得第一电极110具有既可以用于实现显示，又可以用于实现触控的功能。
第一电极110与第二金属走线20电连接，第二金属走线20即为触控信号线，用于向第一电极110传输触控信号。
当阵列基板为液晶显示装置中的阵列基板时，上述的第一电极110具体可以为公共电极(Vcom)。
此处，为了不影响显示，第一电极110示例的可以为透明电极，第一电极110的材料例如可以是ITO(Indium Tin Oxide，氧化铟锡)、IZO(Indium Zinc Oxide，氧化铟锌)或FTO(Fluorine-Doped Tin Oxide，氟掺杂二氧化锡)中的至少一种。
S202、如图10所示，在第一电极110上形成钝化层120(Passivation，简称PVX)。
其中，对于钝化层120的材料不进行限定，例如可以是氮化硅、氧化 硅或氮氧化硅中的至少一种。
此处，对于钝化层120的形成工艺不进行限定，例如可以通过溅射法或沉积法形成。
S203、如图11所示，在钝化层120上形成第二电极130，第二电极130通过贯穿钝化层120、平坦层100和缓冲层90上的过孔与漏极602电连接。
需要说明的是，第一电极110由多个块状子电极构成，因而第二电极130可以穿过第一电极110中块状子电极之间的间隙与漏极602电连接。
这里，在图11中，由于第二电极130的下方示意出了第一电极110的部分，而贯穿钝化层120、平坦层100和缓冲层90上的过孔不会贯穿第一电极110。因此，受限于图11中的剖视方向，第二电极130贯穿钝化层120、平坦层100和缓冲层90上的过孔则无法示意出。
但本领域技术人员应当可以清楚地理解，第二电极130是通过贯穿钝化层120、平坦层100和缓冲层90上的过孔与漏极602电连接的。
此处，第二电极130的材料示例的可以为透明材料，例如可以为ITO、IZO或FTO中的至少一种。
第二电极130的材料和第一电极110的材料可以相同，也可以不同。
其中，当以上实施例中示意出的阵列基板具体为液晶显示装置中的阵列基板时，第二电极130与漏极602电连接，第二电极130即为像素电极。
在本公开一些实施例中，将触控电极(即第一电极110)内置于阵列基板中，可以形成内嵌式触控基板，从而可以降低阵列基板的厚度。
本公开一些实施例提供一种阵列基板，参考图4A所示，该阵列基板包括：
衬底基板30以及设置在衬底基板30上的第一金属走线10和第二金属走线20；设置在第一金属走线10与第二金属走线20之间的条状的挡墙40；其中，挡墙40的宽度小于或等于第一金属走线10与第二金属走线20之间的间距。
在一些实施例中，上述阵列基板还包括参考图3B所示的设置在衬底基板30表面的绝缘薄膜40a；其中，该绝缘薄膜40a上的部分区域的厚度小于其余区域的厚度，该其余区域相比于部分区域突出的部分构成上述的条状的挡墙40；第一金属走线10和第二金属走线20即设置在部分区域的表面。
在一些实施例，参考图4B所示，上述挡墙40具有连续的结构；或者，参考图4C所示，上述挡墙40包括间隔设置的至少两个子挡墙401，至少两个子挡墙401排列成条状。本公开对于挡墙40的材料不进行限定，只要是绝缘非导电材料即可，例如可以是氮化硅、氧化硅或氮氧化硅中的至少一种。
需要说明的是，由于设置挡墙40的作用是为了在形成第一金属走线10和第二金属走线20的过程中避免第一金属走线10和第二金属走线20发生不良，例如具体是通过使待形成的第一金属走线10与待形成的第二金属走线20之间的间隙位置处的光刻胶充分曝光而避免形成后的第一金属走线10和第二金属走线20发生不良。
因而，在一些实施例中，挡墙40的长度与待形成的第一金属走线10或第二金属走线20的长度相同。
此外，对于挡墙40的厚度不进行限定，挡墙40的厚度可以和第一金属走线10、第二金属走线20的厚度相同，也可以小于或大于第一金属走线10、第二金属走线20的厚度。
其中，由于第一金属走线10和第二金属走线20通常是在同一个工艺下形成的，故第一金属走线10的厚度和第二金属走线20的厚度相等。
对于第一金属走线10和第二金属走线20的材料不进行限定，只要能够导电即可。该材料例如可以是金属单质、合金或金属氧化物中的至少一种。
以第一金属走线10和第二金属走线20通过包括有涂布光刻胶、曝光、显影及刻蚀工艺的构图工艺形成为例，本公开实施例提供了一种阵列基板，由于在形成第一金属走线10和第二金属走线20之前，先在衬底基板30上形成挡墙40，且挡墙40的宽度小于或等于待形成的第一金属走线10与待形成的第二金属走线20之间的间距，因而当再形成导电薄膜(导电薄膜用于通过刻蚀形成第一金属走线10和第二金属走线20)时，导电薄膜覆盖在挡墙40上的高度会高于其它区域的导电薄膜。
这样一来，在导电薄膜上涂布光刻胶后，挡墙40上方光刻胶的高度也会高于其它区域光刻胶的高度，因而在曝光工序中，可以增强挡墙40正对的区域中的光刻胶的曝光，使挡墙40正对的区域中的光刻胶被充分曝光，从而解决了待形成的第一金属走线10与待形成的第二金属走线20之间的间隙位置处的光刻胶曝光不足的问题。
由于光刻胶通常为正性光刻胶时，若待形成的第一金属走线10与待形成的第二金属走线20之间的间隙位置处的光刻胶曝光不足，则光刻胶经过显影处理后，在待形成的第一金属走线10与待形成的第二金属走线20之间会残留部分光刻胶，这样便会导致待形成的第一金属走线10与待形成的第二金属走线20之间的导电薄膜刻蚀不彻底，容易导致形成的第一金属走线10与第二金属走线20之间发生接触短路。
在上述的阵列基板中，通过设置挡墙40可以增强待形成的第一金属走线10与待形成的第二金属走线20之间的间隙位置处的光刻胶的曝光，从而可以在确保待形成的第一金属走线10和第二金属走线20具有合适的线宽的情况下，避免待形成的第一金属走线10与待形成的第二金属走线20之间残留光刻胶，因而在对导电薄膜进行刻蚀时，待形成的第一金属走线10与待形成的第二金属走线20之间的导电薄膜可以被充分刻蚀，进而降低了形成后的第一金属走线10与第二金属走线20之间发生接触短路的风险。
当挡墙40的宽度小于第一金属走线10与第二金属走线20之间的间距时，在挡墙40上形成导电薄膜后，只有挡墙40上的导电薄膜的高度高于其它区域，而待形成的第一金属走线10与挡墙40之间以及待形成的第二金属走线20与挡墙40之间的导电薄膜的高度没有变化，因而待形成的第一金属走线10与挡墙40之间以及待形成的第二金属走线20与挡墙40之间仍会存在光刻胶残留的问题，从而可能使得待形成的第一金属走线10与挡墙40之间以及待形成的第二金属走线20与挡墙40之间的导电薄膜刻蚀不彻底，导致形成的第一金属走线10和第二金属走线20的宽度较宽，即使得第一金属走线10与第二金属走线20之间的距离较小。而当第一金属走线10与第二金属走线20之间的距离较小时，容易导致第一金属走线10上传输的信号与第二金属走线20上传输的信号发生相互干扰。
因此，在本公开一些实施例中，参考图4A所示，挡墙40的宽度等于第一金属走线10与第二金属走线20之间的间距。
这样一来，由于挡墙40的宽度等于第一金属走线10与第二金属走线20之间的间距，因而待形成的第一金属走线10与待形成的第二金属走线20之间的光刻胶可以被充分曝光，进而使得待形成的第一金属走线10与待形成的第二金属走线20之间的导电薄膜可以被完全刻蚀，从而避免增加形成后的第一金属走线10和第二金属走线20的宽度，进一步降低第一金 属走线10与第二金属走线20由于发生接触而导致短路的风险。
为了确保形成的阵列基板表面的平整度，在本公开一些实施例中，挡墙40的厚度小于或等于第一金属走线10和第二金属走线20的厚度。
其中，第一金属走线10的厚度与第二金属走线20的厚度相等。
在本公开一些实施例中，参考图12所示，上述阵列基板还包括与第一金属走线10和第二金属走线20同层设置的源极601和漏极602，源极601与第一金属走线10电连接；设置在第一金属走线10和第二金属走线20靠近衬底基板30一侧的栅极70和栅绝缘层80；其中，栅极70靠近衬底基板30设置。
其中，上述薄膜晶体管还包括有源层(本公开实施例所有附图中均未示意出有源层)，有源层和源极601、漏极602均接触。
此处，可以在形成挡墙40之前形成有源层；或者，也可以在形成挡墙40之后，且在形成第一金属走线10和第二金属走线20之前形成有源层；再或者，当然也可以在形成第一金属走线10和第二金属走线20之后形成有源层。
此处，对于栅极70的材料不进行限定，只要能够导电即可。
示例的，栅极70的材料可以是金属单质、合金和金属氧化物中的至少一种。
对于栅绝缘层80的材料不进行限定，只要是绝缘材料即可，例如可以是氮化硅、氧化硅或氮氧化硅中的至少一种。
此外，源极601与第一金属走线10电连接，第一金属走线10具体为数据线。
需要说明的是，本公开实施例在栅极70和栅绝缘层80上设置源极601和漏极602，形成的薄膜晶体管是底栅型薄膜晶体管，但本公开实施例并不限于此，上述阵列基板中的薄膜晶体管还可以是顶栅型薄膜晶体管。
当薄膜晶体管具体是顶栅型薄膜晶体管时，在源极601和漏极602上依次还形成有栅绝缘层80和栅极70。
在一些实施例中，由于源极601和漏极602与第一金属走线10、第二金属走线20同层设置，因而可以同时形成第一金属走线10、第二金属走线20、源极601和漏极602，以简化阵列基板的制作工艺。
进一步的，参考图11所示，上述阵列基板还包括：
依次设置在第一金属走线10和第二金属走线20上的缓冲层90、平坦 层100、第一电极110、钝化层120和第二电极130；其中，第一电极110通过贯穿缓冲层90和平坦层100上的过孔与第二金属走线20电连接；第二电极130通过贯穿钝化层120、平坦层100和缓冲层90上的过孔与漏极602电连接。
其中，缓冲层90、平坦层100以及钝化层120的材料都是绝缘材料。
缓冲层90的材料例如可以是SiO 2、TiO 2或CeO 2中的至少一种。
平坦层100的材料例如可以是树脂。
钝化层120的材料例如可以是氮化硅、氧化硅或氮氧化硅中的至少一种。
需要说明的是，第一电极110和第二电极130示例的可以均为透明电极，第一电极110和第二电极130的材料例如可以是ITO、IZO或FTO中的至少一种。
第二电极130的材料与第一电极110的材料可以相同，也可以不同。
当阵列基板为液晶显示装置中的阵列基板时，第一电极110可以为公共电极(Vcom)，第二电极130与漏极602电连接，第二电极130即为像素电极。
此外，第一电极110由多个块状子电极构成，通过对第一电极110分时复用，使得第一电极110具有既可以用于实现显示，又可以用于实现触控的功能。
第一电极110与第二金属走线20电连接，第二金属走线20即为触控信号线，用于向第一电极110传输触控信号。
这里，第二电极130可以穿过第一电极110中块状子电极之间的间隙与漏极602电连接。
本公开一些实施例，通过将触控电极(即第一电极110)内置于阵列基板中，以形成内嵌式触控基板，从而可以降低阵列基板的厚度。
本公开实施例还提供一种显示装置，包括上述的阵列基板。
其中，该显示装置可以是液晶显示装置，也可以有机电致发光二极管显示装置。
当该显示装置具体为液晶显示装置时，该显示装置除包括阵列基板，还可包括与阵列基板对盒的对盒基板以及设置在阵列基板和对盒基板之间的液晶层。
当该显示装置具体为有机电致发光二极管显示装置时，上述阵列基板 上还形成有有机电致发光层。该显示装置还可包括用于封装上述阵列基板的封装基板。
此外，本公开实施例提供的上述显示装置可以是显示不论运动(例如，视频)或是固定(例如，静止图像)的、且不论是文字或是图画的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置包括例如(但不限于)移动电话、无线装置、个人数据助理(PAD，Portable Android Device)、手持式或便携式计算机、GPS(Global Positioning System，全球定位系统)接收器/导航器、相机、MP4(全称为MPEG-4Part 14)视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。此外，该显示装置还可以是显示面板。
示例的，本公开实施例提供一种显示装置，由于在形成第一金属走线10和第二金属走线20之前，先在衬底基板30上形成挡墙40，且挡墙40的宽度小于或等于待形成的第一金属走线10和第二金属走线20之间的间距，因而当再形成导电薄膜(导电薄膜用于通过刻蚀形成第一金属走线10和第二金属走线20)时，挡墙40上导电薄膜的高度会高于其它区域的导电薄膜，这样在涂布光刻胶后，挡墙40上方光刻胶的高度也会高于其它区域光刻胶的高度，因而在曝光工序中，可以增强挡墙40正对的区域中的光刻胶的曝光，使挡墙40正对的区域中的光刻胶被充分曝光，从而解决了待形成的第一金属走线10与待形成的第二金属走线20之间的间隙位置处的光刻胶曝光不足的问题。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种阵列基板的制备方法，所述制备方法包括：
    在衬底基板上形成条状的挡墙；其中，所述挡墙的宽度小于或等于待形成的第一金属走线和第二金属走线之间的间距；
    在所述挡墙沿延伸方向的一侧形成所述第一金属走线、在所述挡墙沿延伸方向的另一侧形成所述第二金属走线。
  2. 根据权利要求1所述的阵列基板的制备方法，其中，
    所述在衬底基板上形成条状的挡墙，包括：
    在衬底基板上形成绝缘薄膜，并通过构图工艺形成条状的挡墙；
    所述在所述挡墙沿延伸方向的一侧形成所述第一金属走线、在所述挡墙沿延伸方向的另一侧形成所述第二金属走线，包括：
    在所述挡墙上形成导电薄膜，并通过涂布光刻胶、曝光、显影及刻蚀工艺在所述挡墙沿延伸方向的一侧形成所述第一金属走线、在所述挡墙沿延伸方向的另一侧形成所述第二金属走线。
  3. 根据权利要求1所述的阵列基板的制备方法，其中，
    所述在衬底基板上形成条状的挡墙，包括：
    采用打印工艺或蒸镀工艺，在衬底基板上形成条状的挡墙；
    所述在所述挡墙沿延伸方向的一侧形成所述第一金属走线、在所述挡墙沿延伸方向的另一侧形成所述第二金属走线，包括：
    采用打印工艺或蒸镀工艺，在所述挡墙沿延伸方向的一侧形成所述第一金属走线、在所述挡墙沿延伸方向的另一侧形成所述第二金属走线。
  4. 根据权利要求2所述的阵列基板的制备方法，其中，
    所述挡墙具有连续的结构；
    或者，
    所述挡墙包括间隔设置的至少两个子挡墙，所述至少两个子挡墙排列成条状。
  5. 根据权利要求2所述的阵列基板的制备方法，其中，
    所述在衬底基板上形成绝缘薄膜，并通过构图工艺形成条状的挡墙，包括：
    在衬底基板上形成绝缘薄膜，对所述绝缘薄膜的部分区域进行厚度减薄处理；所述绝缘薄膜上未经过所述厚度减薄处理的其余区域相比于经过所述厚度减薄处理的所述部分区域突出的部分形成条状的挡墙。
  6. 根据权利要求2所述的阵列基板的制备方法，其中，所述挡墙的宽度等于所述第一金属走线和所述第二金属走线之间的间距。
  7. 根据权利要求2所述的阵列基板的制备方法，其中，所述挡墙的厚度小于或等于所述第一金属走线和所述第二金属走线的厚度。
  8. 根据权利要求2所述的阵列基板的制备方法，其中，所述通过涂布光刻胶、曝光、显影及刻蚀工艺在所述挡墙沿延伸方向的一侧形成第一金属走线、在所述挡墙沿延伸方向的另一侧形成第二金属走线，包括：通过涂布光刻胶、曝光、显影及刻蚀工艺形成源极和漏极，并在所述挡墙沿延伸方向的一侧形成第一金属走线、在所述挡墙沿延伸方向的另一侧形成第二金属走线，所述源极与所述第一金属走线电连接。
  9. 根据权利要求2所述的阵列基板的制备方法，其中，所述在衬底基板上形成绝缘薄膜之前，所述制备方法还包括：
    在衬底基板上依次形成栅极以及栅绝缘层；
    在形成所述第一金属走线和所述第二金属走线之后，所述制备方法还包括：
    在所述第一金属走线和所述第二金属走线上依次形成缓冲层和平坦层；
    在所述平坦层上形成第一电极，所述第一电极通过贯穿所述缓冲层和所述平坦层上的过孔与所述第二金属走线电连接；
    在所述第一电极上形成钝化层；
    在所述钝化层上形成第二电极，所述第二电极通过贯穿所述钝化层、所述平坦层和所述缓冲层上的过孔与所述漏极电连接。
  10. 一种阵列基板，所述阵列基板包括：
    衬底基板；
    设置在所述衬底基板上的第一金属走线和第二金属走线；
    设置在所述第一金属走线和所述第二金属走线之间的条状的挡墙；
    其中，所述挡墙的宽度小于或等于所述第一金属走线和所述第二金属走线之间的间距。
  11. 根据权利要求10所述的阵列基板，其中，
    所述挡墙具有连续的结构；
    或者，
    所述挡墙包括间隔设置的至少两个子挡墙，所述至少两个子挡墙排列成条状。
  12. 根据权利要求10所述的阵列基板，其中所述阵列基板还包括：
    设置在所述衬底基板表面的绝缘薄膜；
    所述绝缘薄膜上的部分区域的厚度小于其余区域的厚度，所述其余区域相比于所述部分区域突出的部分构成条状的挡墙；
    所述第一金属走线和所述第二金属走线设置在所述部分区域的表面。
  13. 根据权利要求10所述的阵列基板，其中，所述挡墙的宽度等于所述第一金属走线和所述第二金属走线之间的间距。
  14. 根据权利要求10所述的阵列基板，其中，所述阵列基板还包括：
    与所述第一金属走线和所述第二金属走线同层设置的源极和漏极，所述源极与所述第一金属走线电连接；
    设置在所述第一金属走线和所述第二金属走线靠近所述衬底基板一侧的栅极和栅绝缘层；其中，所述栅极靠近所述衬底基板设置。
  15. 根据权利要求14所述的阵列基板，其中，所述阵列基板还包括：
    依次设置在所述第一金属走线和所述第二金属走线上的缓冲层、平坦层、第一电极、钝化层和第二电极；
    其中，所述第一电极通过贯穿所述缓冲层和所述平坦层上的过孔与所述第二金属走线电连接；所述第二电极通过贯穿所述钝化层、所述平坦层和所述缓冲层上的过孔与所述漏极电连接。
  16. 一种显示装置，所述显示装置包括权利要求10-15任一项所述的阵列基板。
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