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WO2017012075A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2017012075A1
WO2017012075A1 PCT/CN2015/084713 CN2015084713W WO2017012075A1 WO 2017012075 A1 WO2017012075 A1 WO 2017012075A1 CN 2015084713 W CN2015084713 W CN 2015084713W WO 2017012075 A1 WO2017012075 A1 WO 2017012075A1
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WIPO (PCT)
Prior art keywords
voltage
transistor
driving
line
pixel circuit
Prior art date
Application number
PCT/CN2015/084713
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English (en)
French (fr)
Inventor
袁泽
Original Assignee
深圳市柔宇科技有限公司
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Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to US15/738,714 priority Critical patent/US10424246B2/en
Priority to CN201580001767.9A priority patent/CN107077818A/zh
Priority to KR1020177036078A priority patent/KR20180008652A/ko
Priority to PCT/CN2015/084713 priority patent/WO2017012075A1/zh
Priority to EP15898631.5A priority patent/EP3327710A4/en
Priority to JP2018500929A priority patent/JP2018528455A/ja
Publication of WO2017012075A1 publication Critical patent/WO2017012075A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the transistor M1 is connected to the data signal V DATA and is controlled by the scan signal V SCAN
  • the driving transistor MD is connected to the pixel power source V DD and is also connected to the data signal V DATA through the transistor M1
  • the pixel power source V DD and the transistor are respectively connected across the capacitor C ST
  • the node A between the M1 and the driving transistor MD, the organic light emitting diode D OLED and the sensing capacitor C OLED are connected in parallel between the transistor MD and the external power source V SS .
  • the voltage of the external power source V SS is lower than the voltage of the pixel power source V DD , and may be, for example, a ground voltage.
  • the data signal V DATA starts to charge the capacitor C ST , and then the voltage in the capacitor C ST is applied to the gate of the driving transistor MD, thereby turning on the driving transistor.
  • the MD causes a current to flow through the organic light emitting device to emit light.
  • the current supplied to the organic light emitting device through the driving transistor MD is calculated by the following formula:
  • the present invention is directed to a pixel circuit and a driving method thereof, and a display panel which can eliminate the influence of a change in current caused by threshold unevenness or drift on a display effect.
  • a pixel circuit including a driving transistor having a gate; a first transistor connected between a data line and a gate of the driving transistor, and having a connection to a first a gate of the scan line; a second transistor connected between a first power line and the drive transistor and having a gate connected to a control line; and a third transistor connected to a second power line and Between the drive transistors, and having a gate connected to a second scan line; a light-emitting element connected to a third power line and the drive Between the transistors; a driving capacitor connected between the gate of the driving transistor and the light-emitting element; and an additional capacitor connected in parallel to the light-emitting element.
  • Another embodiment of the present invention further provides a display panel comprising a plurality of arrays of pixel circuits as described above; a scan driving unit for respectively providing scan signals to the first and second scan lines; and emission control a driving unit, configured to provide a transmission control signal to the control line; a data driving unit configured to provide a data signal to the data line; a first power source for providing a first voltage to the first power line; and a second power source Providing a second voltage to the second power line; and a third power source for providing a third voltage to the third power line.
  • FIG. 1 is a schematic diagram of a conventional pixel circuit.
  • FIG. 2 is a schematic view of a frame of a display panel of the present invention.
  • FIG. 3 is a schematic diagram of a pixel circuit of a first embodiment of the display panel of FIG. 1.
  • 4a and 4b are respectively a timing chart provided by the first embodiment of the present invention and a working diagram of the pixel circuit of FIG. 3 in the first stage of the timing chart.
  • 5a and 5b are respectively a timing diagram and a schematic diagram of the operation of the pixel circuit of FIG. 3 in the second stage of the timing chart.
  • 6a and 6b are respectively a timing diagram and a schematic diagram of the operation of the pixel circuit of FIG. 3 in the third stage of the timing chart.
  • 7a and 7b are respectively a timing chart and a working diagram of the pixel circuit of FIG. 3 in the fourth stage of the timing chart.
  • Figure 8 is a graph showing the relationship between the threshold value of the driving transistor of the pixel circuit of Figure 3 and the current through the light emitting diode.
  • 10a and 10b are respectively a timing diagram of a second embodiment of the pixel circuit of FIG. 3 and a schematic diagram of the operation of the pixel circuit in the third stage of the timing chart.
  • Fig. 11 is a view showing the relationship between the carrier mobility of the driving transistor of the pixel circuit and the current change of the light emitting diode at the timing of Fig. 10b.
  • the display panel 8 includes a scan driving unit 10, a data driving unit 20, an emission control driving unit 30, a display unit 40, a first power source 50, a second power source 60, and a third power source 65.
  • the display unit 40 includes a plurality of A pixel circuit 70 arranged in a matrix.
  • the scan driving unit 10, the data driving unit 20, and the emission control driving unit 30 are respectively configured to supply the scanning signals V SCAN (including the first scanning signal V SCAN1 and the second scanning signal V SCAN2 ), the data signal V DATA and each pixel circuit 70 .
  • the control signal V EM is transmitted.
  • the first power source 50, the second power source 60, and the third power source 65 are respectively configured to supply the first voltage V DD , the second voltage V RST , and the third voltage V SS to each of the pixel circuits 70.
  • the pixel circuit 70 of the first embodiment of the present invention has a first scan line for transmitting the first scan signal V SCAN1 and a second scan line for transmitting the second scan signal V SCAN2 for transmission.
  • the pixel circuit 70 further includes:
  • a first transistor M1 having a control electrode connected to the first scan line and two control electrodes connected to the data line and a control electrode of the drive transistor MD;
  • a second transistor M2 having a control electrode connected to the control line and two controlled electrodes connected to the first power supply line and a controlled electrode of the driving transistor MD;
  • a third transistor M3 having a control electrode connected to the second scan line and two controlled electrodes connected to the second power line and another controlled electrode of the drive transistor MD;
  • a driving capacitor C ST having two ends connected to the control electrode of the driving transistor MD and the other controlled electrode;
  • a light-emitting element comprising a light-emitting diode D OLED connected in parallel between the third power line and the other controlled pole of the drive transistor MD and a sensing capacitor C OLED of its own.
  • the illuminating element is exemplified by an organic light emitting diode (OLED), but it should be understood that the present invention is not limited thereto.
  • the illuminating element may also be an inorganic light emitting diode;
  • the driving transistor MD, the first transistor M1, the second transistor M2, and the third transistor M3 in the example are preferably thin film field effect transistors, specifically N-type thin film field effect transistors, but not limited thereto, or may be P Types or other electronic devices capable of implementing switching functions, such as transistors, those skilled in the art can understand how other types of transistors operate according to the description of the following embodiments, and thus other types of transistors will not be described in the present invention.
  • the voltage value of the second voltage V RST is lower than the voltage value of the first voltage V DD
  • the third voltage V SS may be the ground voltage.
  • the driving transistor MD includes a gate electrode and two controlled electrodes which are controlled by the gate electrode to be turned on or off, wherein the gate electrode is the gate G of the driving transistor MD, and the two controlled poles are
  • the drain D and the source S are identical in the first to third transistors M1, M2, and M3.
  • the drain D and the source S of the first transistor M1 are respectively connected to the data line and the gate G of the driving transistor MD, and the gate G is connected to the first scan line.
  • the drain D and the source S of the second transistor M2 are respectively connected to the first power line and the drain D of the driving transistor MD, and the gate G is connected to the control line.
  • the drain D and the source S of the third transistor M3 are respectively connected to the source S and the second power line of the driving transistor MD, and the gate G is connected to the second scanning line. Both ends G of the driving transistor MD and the source S are respectively connected to the driving capacitor C ST .
  • the light emitting diode D OLED of the light emitting element and its own sensing capacitor C OLED are connected in parallel to the source S of the driving transistor MD and the third power line, and the cathode of the light emitting diode D OLED is connected to the third power line.
  • the pixel circuit 70 of FIG. 3 operates in accordance with the timing diagram of one embodiment shown in FIG. 4a.
  • each operation cycle of the pixel circuit 70 can be divided into four stages.
  • the operation of the pixel circuit 70 is as shown in FIG. 4b.
  • the drive capacitor C ST and the sense capacitor C OLED are reset. Specifically, the emission control signal V EM , the first scan signal V SCAN1 , and the second scan signal V SCAN2 are at a high level, and the first transistor M1, the second transistor M2, and the third transistor M3 are turned on, and the driving capacitor C ST is turned on.
  • the two ends that is, the nodes N G and N O are respectively charged through the first transistor M1 and the third transistor M3 to the reference voltage V REF and the second voltage V RST written at the data line at this time, and the reference voltage V REF and the first
  • the voltage difference of the two voltages V RST is greater than the threshold voltage V TH of the driving transistor MD, that is, V REF -V RST >V TH
  • the voltage difference between the voltages of the second voltage V RST and the third voltage Vss is smaller than the threshold voltage of the LED D OLED .
  • the second voltage V RST is different from the third voltage V SS to match the transistors of different threshold voltages, thereby improving the flexibility of precharging the capacitors/nodes in the first stage.
  • the second voltage V RST can also be the same potential as the third voltage V SS , as long as the voltage difference relationship satisfies the above, that is, the third power source 65 can be omitted, the LED D OLED and the sensing capacitor.
  • the C OLED can thus be directly connected to the second power line, and the second power source 60 can now output a ground voltage.
  • the driving transistor MD is still in an on state, and the data line is still written with the reference voltage V REF , and the voltage Vg of the node N G is thus maintained at the reference voltage V REF . Since the driving transistor MD is turned on, the first voltage V DD is gradually charged to the driving capacitor C ST through the driving transistor MD until the voltage Vo of the node N O is charged to the difference between the reference voltage V REF and the threshold voltage V TH of the driving transistor MD ( V REF - V TH ), at this time, the voltage difference V GS between the gate G and the source S of the driving transistor MD is V TH .
  • the drive transistor MD is turned off, the node voltage V O N O is maintained at (V REF -V TH). In this stage, the driving transistor MD is in an on state and a final off state, and the light emitting element still does not emit light.
  • the voltage output from the data line becomes the data voltage V DATA higher than the reference voltage V REF , and the voltage of the node N G is thus raised to V DATA .
  • the voltage change of the node N G is shared by the driving capacitor C ST and the sensing capacitor C OLED .
  • the voltage change value ⁇ V at the node N O is:
  • the operation of the pixel circuit 70 is as shown in Figure 7b.
  • the emission control signal V EM , the first scan signal V SCAN1 , and the second scan signal V SCAN2 are respectively a high level, a low level, and a low level, and the first and third transistors M1 and M3 at this time.
  • the second transistor M2 is turned on, and under the action of the energy stored in the driving capacitor C ST , V GS is greater than V TH , and the driving transistor MD is thus turned on.
  • the current flows in the light emitting element of the fourth stage had only two voltage V REF and V DATA and V DATA before and after the data signal, and a drive capacitor C ST sensing capacitor C OLED and the capacitance value C ST1 and C OLED1 is related, thereby reducing the influence of the variation of the threshold voltage on the current flowing through the light-emitting element.
  • the 4T1C structure of the present invention has a significantly lower current variation under the same threshold voltage VTH as compared with the conventional 2T1C structure, thereby improving the uniformity of the brightness of the display panel 8.
  • C OLED1 ' is the parallel capacitance value of the sensing capacitor C OLED and the capacitor C D .
  • the calculation principle is similar to the above, and its working principle is similar to the above, and will not be described in the beginning.
  • FIG. 10a is a timing diagram of a second embodiment of the pixel circuit 70 of the present invention, which differs from the first embodiment described above in that the emission control signal VEM remains high in the first to fourth stages.
  • the pixel circuit 70 described above is allowed to perform mobility compensation.
  • the working processes of the first and second phases are the same as those of the first embodiment, and are not described herein.
  • the operation of the pixel circuit 70 is as shown in Fig. 10b, the first and second transistors M1, M2 are turned on, and the third transistor M3 is turned off.
  • the first power source V DD is charged to the node N O through the driving transistor MD, and the charging efficiency is determined by the mobility of the driving transistor MD.
  • the charging efficiency is high, the node NO is charged to a higher voltage, and the voltage across the driving capacitor C ST is thus reduced; when the mobility of the driving transistor MD is low, the node N O It is charged to a lower voltage, thus achieving mobility compensation.
  • the length of the third stage also determines the degree of compensation.
  • the above dynamic compensation effect can be seen from FIG. 11 that the 4T1C structure can better compensate for the influence of the change of the mobility compared to the conventional 2T1C structure.
  • the pixel circuit 70' of the second embodiment described above is also applicable to the driving method in the timing chart.
  • first and second are used for descriptive purposes only, and cannot be ignored. The solution is to indicate or imply a relative importance or implicitly indicate the number of technical features indicated. Thus, features defining “first” or “second” may include one or more of the described features either explicitly or implicitly. In the description of the present invention, the meaning of "a plurality" is two or more unless specifically and specifically defined otherwise.
  • installation In the description of the present invention, “installation,” “connected,” and “connected” are to be understood broadly unless otherwise specifically defined and defined. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be directly connected or indirectly connected through an intermediate medium, and may be an internal connection of two elements or an interaction relationship of two elements.
  • installation In the description of the present invention, the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素电路、驱动方法及显示面板，像素电路包括驱动晶体管（MD）；第一晶体管（M1），其控制极（G）连接至一个第一扫描线并且其两个受控极（D，S）分别连接至一个数据线及驱动晶体管（MD）的控制极（G）；第二晶体管（M2），其控制极（G）连接至一个控制线并且其两个受控极（D，S）分别连接至一个第一电源线及驱动晶体管（MD）的一个受控极（D）；第三晶体管（M3），其控制极（G）连接至一个第二扫描线并且其两受控极（S，D）分别连接至一个第二电源线及驱动晶体管（MD）的另一受控极（S）；驱动电容（C ST），其两端分别连接至驱动晶体管（MD）的控制极（G）及所述另一受控极（S）；及发光元件，其包括并联在一个第三电源线及驱动晶体管（MD）所述另一受控极（S）之间的发光二极管（D OLED）以及一个其自身的感应电容（C OLED）。上述结构消除了驱动晶体管（MD）的阈值电压对显示效果的影响。

Description

像素电路及其驱动方法、显示面板 技术领域
本发明涉及有机发光显示面板，尤其涉及有机发光显示面板的能够补偿阈值电压的像素驱动电路及驱动方法。
背景技术
有机电致发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件已越来越多地被应用于高性能有机发光显示面板中。请结合图1，现有的OLED显示面板像素电路包括驱动晶体管(TransiSTor)MD、起开关作用的晶体管M1、一个电容CST以及一个有机发光器件，即2T1C。其中，有机发光器件包括一个有机发光二极管DOLED以及一个其自身的感应电容COLED。晶体管M1连接至数据信号VDATA并受扫描信号VSCAN控制，驱动晶体管MD连接至像素电源VDD并通过晶体管M1也连接至数据信号VDATA，电容CST两端分别连接像素电源VDD以及晶体管M1及驱动晶体管MD之间的节点A，有机发光二极管DOLED以及感应电容COLED并联在晶体管MD与外部电源VSS之间。其中，外部电源VSS的电压低于像素电源VDD的电压，例如可以是地电压。当晶体管M1的栅极响应到扫描信号VSCAN开启晶体管M1时，数据信号VDATA就开始对电容CST进行充电，随后电容CST中的电压施加到驱动晶体管MD的栅极，从而打开驱动晶体管MD，使得电流流过有机发光器件进行发光。
通过驱动晶体管MD向有机发光器件提供的电流通过以下公式计算：
IOLED＝1/2*β(VGS-VTH)2---公式1
其中，IOLED是流过有机发光器件的电流，VGS是驱动晶体管MD的栅 极和源极之间施加的电压，VGS由CST两端电压决定，VTH是驱动晶体管MD的阈值电压，β是驱动晶体管MD的增益因子，由器件尺寸及半导体载流子迁移率决定。从公式1可以看出，流过有机发光器件的电流会受到驱动晶体管MD的阈值电压的影响。由于生产过程中有机发光显示面板中的每一个晶体管的阈值电压和电子迁移率均不相同，这就导致了即使给予相同的VGS，电路中产生的电流IOLED也仍然会有差异，从而造成亮度不均。
发明内容
有鉴于此，本发明旨在提供一种可消除阈值不均匀或漂移导致的电流变化对显示效果的影响的像素电路及其驱动方法，以及显示面板。
本发明一种实施方式提供了一种像素电路，包括驱动晶体管；第一晶体管，其控制极连接至一个第一扫描线并且其两个受控极分别连接至一个数据线及该驱动晶体管的控制极；第二晶体管，其控制极连接至一个控制线并且其两个受控极分别连接至一个第一电源线及该驱动晶体管的一个受控极；第三晶体管，其控制极连接至一个第二扫描线并且其两个受控极分别连接至一个第二电源线及该驱动晶体管的另一受控极；驱动电容，其两端分别连接至该驱动晶体管的控制极及所述另一受控极；及发光元件，其包括并联在一个第三电源线及该驱动晶体管所述另一受控极之间的发光二极管以及一个其自身的感应电容。
本发明另一实施方式提供了一种像素电路，包括驱动晶体管，具有一个栅极；第一晶体管，其连接在一个数据线及该驱动晶体管的栅极之间，并具有一个连接至一个第一扫描线的栅极；第二晶体管，其连接在一个第一电源线及该驱动晶体管之间，并具有一个连接至一个控制线的栅极；第三晶体管，其连接在一个第二电源线及该驱动晶体管之间，并具有一个连接至一个第二扫描线的栅极；发光元件，其连接在一个第三电源线及该驱 动晶体管之间；驱动电容，其连接在该驱动晶体管的栅极及该发光元件之间；及附加电容，其并联至该发光元件。
本发明另一实施方式还提供了一种显示面板，包括多个阵列排布的如上所述的像素电路；扫描驱动单元，用于分别向该第一及第二扫描线提供扫描信号；发射控制驱动单元，用于向该控制线提供发射控制信号；数据驱动单元，用于向该数据线提供数据信号；第一电源，用于向该第一电源线提供第一电压；第二电源，用于向该第二电源线提供第二电压；及第三电源，用于向该第三电源线提供第三电压。
本发明另一实施方式还提供了一种像素电路的驱动方法，应用于如上所述的像素电路，该驱动晶体管具有一个阈值电压，该驱动方法包括：使该第一至第三晶体管导通，该驱动电容存储的电荷分别通过该第一晶体管及第三晶体管向该数据线及第二电源线释放；使该第一及第二晶体管导通，第三晶体管截止，该数据线通过该第一晶体管向该驱动晶体管输出一个参考电压，该第一电源线提供的第一电压通过该第二晶体管及驱动晶体管向该驱动电容充电，直到该驱动晶体管控制极与一个受控极两端电压为该阈值电压；使该第一晶体管导通，而第二及第三晶体管截止，该数据线输出一个高于该参考电压的数据电压，该驱动电容两端电压被充电至该阈值电压与另一电压值之和，该另一电压值与该数据电压与参考电压的差相关；及使该第一及第三晶体管截止，而第二晶体管导通，该驱动电容驱动该驱动晶体管导通进而使该第一电压驱动该发光元件发光。
本发明另一实施方式还提供了一种像素电路的驱动方法，应用于如上所述的像素电路，该驱动晶体管具有一个阈值电压，该驱动方法包括：使该第一至第三晶体管导通，从而使驱动晶体管导通并且该驱动电容及该发光元件各自两端的电压被重置；使该第一及第二晶体管导通，而第三晶体 管截止，使该数据线输出一个参考电压从而使该驱动电容、驱动晶体管、发光元件相互连接的第一节点的电压为该参考电压与该阈值电压之差；使该第一及第二晶体管导通，而第三晶体管截止，使该数据线输出一个高于该参考电压的数据电压，从而使该驱动电容两端电压为该阈值电压与另一电压值之和，所述另一电压值与该数据电压与该参考电压的差相关；及使该第一及第三晶体管截止，而第二晶体管导通，从而利用该驱动电容驱动该驱动晶体管导通进而使该第一电压驱动该发光元件发光。
在本发明中，流过发光元件的电流只与数据信号前后的两个电压有关，从而减小了阈值电压的变化对流过发光元件的电流影响。与传统的2T1C结构相比，在相同的阈值电压的变化下，电流变化明显降低，进而很好的改善显示效果。
附图说明
下列附图用于结合具体实施方式详细说明本发明的各个实施方式。应当理解，附图中示意出的各元件并不代表实际的大小及比例关系，仅是为了清楚说明而示意出来的示意图，不应理解成对本发明的限制。
图1是现有像素电路的示意图。
图2是本发明的显示面板的框架示意图。
图3是图1的显示面板的第一实施方式的像素电路的示意图。
图4a、4b分别是本发明第一实施方式提供的时序图及图3的像素电路在该时序图的第一阶段的工作示意图。
图5a、5b分别是时序图及图3的像素电路在该时序图的第二阶段的工作示意图。
图6a、6b分别是时序图及图3的像素电路在该时序图的第三阶段的工作示意图。
图7a、7b分别是时序图及图3的像素电路在该时序图的第四阶段的工作示意图。
图8是图3的像素电路的驱动晶体管的阀值与通过发光二极管的电流变化关系图。
图9是图1的显示面板的第二实施方式的像素电路的示意图。
图10a及10b分别是图3的像素电路的第二实施方式的时序图以及该像素电路在该时序图的第三阶段的工作示意图。
图11是在图10b的时序下像素电路的驱动晶体管的载流子迁移率与发光二极管的电流变化关系示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合多个实施方式及附图，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施方式仅仅用以解释本发明，并不用于限定本发明。
请参照图2，显示面板8包括扫描驱动单元10、数据驱动单元20、发射控制驱动单元30、显示单元40、第一电源50、第二电源60及第三电源65，显示单元40包含多个矩阵排列的像素电路70。扫描驱动单元10、数据驱动单元20、发射控制驱动单元30分别用以向各像素电路70提供扫描信号VSCAN(包括第一扫描信号VSCAN1及第二扫描信号VSCAN2)、数据信号VDATA和发射控制信号VEM。第一电源50、第二电源60及第三电源65分别用以向各像素电路70提供第一电压VDD、第二电压VRST及第三电压VSS。
请再参照图3，本发明第一实施方式的像素电路70具有用于传输第一扫描信号VSCAN1的第一扫描线、用于传输第二扫描信号VSCAN2的第二扫描 线、用于传输第一电源50的第一电源线、用于传输第二电源60的第二电源线、用于传输第三电源65的第三电源线、用于传输数据信号VDATA的数据线、用于传输发射控制信号VEM的控制线。像素电路70还包括：
驱动晶体管MD；
第一晶体管M1，其控制极连接至该第一扫描线并且其两个受控极分别连接至该数据线及该驱动晶体管MD的控制极；
第二晶体管M2，其控制极连接至该控制线并且其两个受控极分别连接至该第一电源线及该驱动晶体管MD的一个受控极；
第三晶体管M3，其控制极连接至该第二扫描线并且其两个受控极分别连接至该第二电源线及该驱动晶体管MD的另一受控极；
驱动电容CST，其两端分别连接至该驱动晶体管MD的控制极及所述另一受控极；及
发光元件，其包括并联在该第三电源线及该驱动晶体管MD所述另一受控极之间的发光二极管DOLED以及一个其自身的感应电容COLED。
具体地，在下述实施例中，发光元件以有机发光二极管(OLED)为例，但应当理解，本发明并不以此为限，比如，此发光元件也可以是无机发光二极管；且下述实施例中的驱动晶体管MD、第一晶体管M1、第二晶体管M2和第三晶体管M3优选是薄膜场效应晶体管，具体都是N型薄膜场效应晶体管，但也不以此为限，也可以是P型或者其它能够实现开关功能的电子器件，比如三极管，本领域技术人员根据下述实施方式的描述可得知其它类型的晶体管是如何工作，因此本发明将不赘述其它类型的晶体管。此时，第二电压VRST的电压值低于第一电压VDD的电压值，第三电压VSS可以是地电压。
驱动晶体管MD包括一个控制极及两个受该控制极控制而相互导通 或不导通的受控极，其中，控制极即为驱动晶体管MD的栅极G，两个受控极即为其漏极D及源极S，第一至第三晶体管M1、M2、M3同理。第一晶体管M1的漏极D及源极S分别连接至该数据线及驱动晶体管MD的栅极G，而栅极G连接至第一扫描线。第二晶体管M2的漏极D及源极S分别连接第一电源线及驱动晶体管MD的漏极D，而栅极G则连接至该控制线。第三晶体管M3的漏极D及源极S分别连接驱动晶体管MD的源极S及第二电源线，而栅极G则连接该第二扫描线。驱动电容CST两端分别连接驱动晶体管MD的栅极G及源极S。发光元件的发光二极管DOLED以及其自身的感应电容COLED并联于驱动晶体管MD的源极S及该第三电源线，并且发光二极管DOLED的阴极连接至该第三电源线。在本实施方式中，记第一晶体管M1、驱动电容CST及驱动晶体管MD相互连接的节点为NG，记驱动电容CST、驱动晶体管MD、发光元件及第三晶体管M3相互连接的节点为NO。
请结合图4a及4b，图3的像素电路70根据图4a所示的一种实施方式的时序图运行。在图4a所示的时序图中，像素电路70的每个运行周期可分为四个阶段，在第一阶段，像素电路70的运行情况如图4b所示。在第一阶段中，驱动电容CST及感应电容COLED被重置。具体地，发射控制信号VEM、第一扫描信号VSCAN1及第二扫描信号VSCAN2为高电平，此时第一晶体管M1、第二晶体管M2及第三晶体管M3导通，驱动电容CST两端，即节点NG及NO分别通过第一晶体管M1及第三晶体管M3被充电至该数据线此时写入的参考电压VREF及第二电压VRST，并且参考电压VREF与第二电压VRST的压差大于驱动晶体管MD的阈值电压VTH，即VREF-VRST>VTH，同时第二电压VRST与第三电压Vss的电压的压差小于发光二极管DOLED阈值电压。此时驱动晶体管MD处于导通状态并且发光元 件不发光，驱动电容CST被重置至一个预设电压VREF-VREF2，感应电容COLED被重置至一个预设第二电压VREF2-Vss。其中VREF2为该阶段NO节点的电压，由于VSCAN2的偏压设置使得M3的驱动电压较大，漏源电压因此较小，NO节点电压VREF2与VRST接近。
在本实施方式中，设置第二电压VRST与第三电压VSS不同可配合不同阈值电压的晶体管，提高在第一阶段对各电容/各节点的预充电的灵活性。然而可以理解，第二电压VRST也可与第三电压VSS为相同电位，只要电压差关系满足以上便可，即是说，此时第三电源65可以省略，发光二极管DOLED及感应电容COLED从而可直接连接至第二电源线，第二电源60此时可输出地电压。因此，在本说明书及权利要求书中，第三电源65可与第二电源60所提供的电压一致；更进一步讲，第三电源65与第二电源60可以是指同一个电源，即第二电源线与第三电源线可以是同一根线，对其分开描述不应理解为一定是分开的两个电源而构成对本发明所要保护的范围的限缩。
请结合图5a及5b，在第二阶段，像素电路70的运行情况如图5b所示。在第二阶段中，使节点NO，即驱动电容CST与驱动晶体管MD的源极S连接的一端被充电至参考电压VREF与驱动晶体管MD的阈值电压VTH之差。具体地，发射控制信号VEM、第一扫描信号VSCAN1、第二扫描信号VSCAN2分别为高电平、高电平、低电平，此时第一晶体管M1导通，第二晶体管M2导通，第三晶体管M3截止。此时驱动晶体管MD仍处于导通状态，并且该数据线写入的仍为参考电压VREF，节点NG的电压Vg因此保持在参考电压VREF。由于驱动晶体管MD导通，第一电压VDD通过驱动晶体管MD逐渐向驱动电容CST充电，直至节点NO的电压Vo被充电至参考电压VREF与驱动晶体管MD的阈值电压VTH之差(VREF-VTH)，此时驱 动晶体管MD的栅极G与源极S的压差VGS为VTH。若节点NO电压Vo再增大，驱动晶体管MD将截止，因此节点NO的电压VO保持在(VREF-VTH)。此阶段中驱动晶体管MD处于导通及最后的截止状态，发光元件仍不发光。
不同于将第三晶体管M3采用二极管连接方式，即将第三晶体管M3的漏极和栅极连接在一起，只能补偿VTH为正的驱动晶体管MD，本实施方式中，两个节点NG及NO可分别充电不同的电位，且漏极和栅极无需连接在一起，所以可以补偿阈值为负的驱动晶体管。因此，上述第二阶段的补偿过程对驱动晶体管MD的阈值电压VTH的数值没有额外要求，VTH可为正值也可为负值。
请结合图6a及6b，在第三阶段，像素电路70的运行情况如图6b所示。在第三阶段中，使第二晶体管M2截止从而切断第一电源VDD与驱动晶体管MD的连接，并且将数据电压输入至驱动晶体管MD的栅极。具体地，发射控制信号VEM、第一扫描信号VSCAN1、第二扫描信号VSCAN2分别为低电平、高电平、低电平，此时第一晶体管M1导通，第二及第三晶体管M2、M3截止，因此没有电流流过驱动晶体管MD。此时数据线输出的电压变为比参考电压VREF高的数据电压VDATA，节点NG的电压也因此升高为VDATA。节点NG的电压变化被驱动电容CST及感应电容COLED所分担，此时节点NO上的电压变化值ΔV为：
(VDATA-VREF)*[1/COLED1/(1/CST1+1/COLED1)]
＝(VDATA-VREF)*CST1/(COLED1+CST1)
其中，CST1及COLED1为驱动电容CST及感应电容COLED的电容值。此时，节点NO的电压为(VREF-VTH)+ΔV。驱动电容CST两端的电压VST则为：
VDATA-[(VREF-VTH)+ΔV]
＝VDATA-[(VREF-VTH)+(VDATA-VREF)*CST1/(COLED1+CST1)]
＝VTH+(VDATA-VREF)*COLED1/(COLED1+CST1)
请结合图7a及7b，在第四阶段，像素电路70的运行情况如图7b所示。在第四阶段中，发射控制信号VEM、第一扫描信号VSCAN1、第二扫描信号VSCAN2分别为高电平、低电平、低电平，此时第一及第三晶体管M1、M3截止，第二晶体管M2导通，在驱动电容CST所存储的能量的作用下，VGS大于VTH，驱动晶体管MD因此导通。此时第一电源VDD所产生的电流流过发光二极管DOLED以使其发光及电容COLED。在第四阶段的开始阶段，Vo电位较低，发光二极管DOLED处于关闭状态，因此电流大部分流过COLED，对COLED充电，使得NO电位VO提升。驱动晶体管MD的栅极与源极的电压差VGS由CST两端的电压决定，由于M1晶体管在该阶段处于关闭状态，不导通电流，因此CST两端的电压保持恒定，NG节点的电位VG随VO的提升而升高。最终VO升高到一定的电位并达到稳定，从电源VDD流出的电流，全部流过发光二极管DOLED。通过背景技术里面提到的公式1可知，此时流过发光元件的电流：
IOLED＝1/2*β(VTH+(VDATA-VREF)*COLED1/(COLED1+CST1)-VTH)2
＝1/2*β((VDATA-VREF)*COLED1/(COLED1+CST1))2
从以上公式可看出，在第四阶段流过发光元件的电流只与数据信号VDATA前后的两个电压VREF及VDATA、以及驱动电容CST及感应电容COLED的电容值CST1及COLED1有关，从而减小了阈值电压的变化对流过发光元件的电流影响。如图8所示，本发明的4T1C结构与传统的2T1C结构相比，在相同的阈值电压VTH的变化下，电流变化明显降低，进而很好的改善显示面板8的亮度的均匀性。
请结合图9，其是本发明第二实施方式的像素电路70’的示意图。像 素电路70’的与第一实施方式的不同之处在于，还包括与发光元件并联的附加电容CD，附加电容CD用于在感应电容COLED的电容值COLED1较小的情况下，增加与感应电容COLED的并联电容值，并使该并联的电容值远大于驱动电容CST的电容值CST，从而使第三阶段数据线的电压自VREF变化至VDATA时，节点NO的电压变化可按照第一实施方式中描述的计算其上电压的方式来进行计算。节点NO此时电压变化值ΔV为：
(VDATA-VREF)*[1/COLED1’/(1/CST1+1/COLED1’)]
其中COLED1’为感应电容COLED与电容CD的并联电容值。其计算原理与上述相似，其工作原理也与上述相似，本初将不做赘述。
请结合图10a，其是本发明的像素电路70的第二实施方式的时序图，其与上述第一实施方式的区别在于，发射控制信号VEM在第一至第四阶段一直保持高电平，从而允许上述像素电路70进行迁移率补偿。具体地，在第二实施方式的时序图下，第一及第二阶段的工作过程与第一实施方式的相同，在此不做赘述。在第三阶段，像素电路70的工作情况如图10b所示，第一及第二晶体管M1、M2打开，第三晶体管M3关闭。第一电源VDD通过驱动晶体管MD向节点NO充电，充电效率由驱动晶体管MD的迁移率决定。当驱动晶体管MD的迁移率高时，充电效率高，节点NO被充至一个较高的电压，驱动电容CST两端的电压因此变小；当驱动晶体管MD的迁移率低时，节点NO被充至一个较低的电压，从而实现了迁移率的补偿。当然，第三阶段的长度也决定了补偿的程度。上述动态补偿效果可从图11中看出，相比传统的2T1C结构，4T1C结构可以对于迁移率的变化影响进行较好的补偿。可以理解，上述第二实施方式的像素电路70’也适用于该时序图下的驱动方式。
在本发明的描述中，“第一”、“第二”仅用于描述目的，而不能理 解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，除非另有明确的规定和限定，“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
以上所述仅为本发明的较佳实施方式而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (20)

  1. 一种像素电路，包括：
    驱动晶体管；
    第一晶体管，其控制极连接至一个第一扫描线并且其两个受控极分别连接至一个数据线及该驱动晶体管的控制极；
    第二晶体管，其控制极连接至一个控制线并且其两个受控极分别连接至一个第一电源线及该驱动晶体管的一个受控极；
    第三晶体管，其控制极连接至一个第二扫描线并且其两个受控极分别连接至一个第二电源线及该驱动晶体管的另一受控极；
    驱动电容，其两端分别连接至该驱动晶体管的控制极及所述另一受控极；及
    发光元件，其包括并联在一个第三电源线及该驱动晶体管所述另一受控极之间的发光二极管以及一个其自身的感应电容。
  2. 如权利要求1所述的像素电路，其特征在于，该驱动晶体管、第一至第三晶体管都为薄膜场效应晶体管。
  3. 如权利要求1所述的像素电路，其特征在于，该第一电源线提供的第一电压大于该第二电源线提供的第二电压。
  4. 如权利要求3所述的像素电路，其特征在于，该第一及第二电压之差大于该驱动晶体管的阈值电压，该第二电压与该第三电源线提供的第三电压之差小于该发光二极管的阈值电压。
  5. 如权利要求4所述的像素电路，其特征在于，该第三电压为地电压。
  6. 一种像素电路，包括：
    驱动晶体管，具有一个栅极；
    第一晶体管，其连接在一个数据线及该驱动晶体管的栅极之间，并具有一个连接至一个第一扫描线的栅极；
    第二晶体管，其连接在一个第一电源线及该驱动晶体管之间，并具有一个连接至一个控制线的栅极；
    第三晶体管，其连接在一个第二电源线及该驱动晶体管之间，并具有一个连接至一个第二扫描线的栅极；
    发光元件，其连接在一个第三电源线及该驱动晶体管之间；
    驱动电容，其连接在该驱动晶体管的栅极及该发光元件之间；及
    附加电容，其并联至该发光元件。
  7. 如权利要求6所述的像素电路，其特征在于，该驱动晶体管的漏极及源极分别连接该第二晶体管及该发光元件。
  8. 如权利要求6所述的像素电路，其特征在于，该第一晶体管的漏极及源极分别连接该数据线及该驱动晶体管的栅极。
  9. 如权利要求6所述的像素电路，其特征在于，该第二晶体管的漏极及源极分别该第一电源线及该驱动晶体管。
  10. 如权利要求6所述的像素电路，其特征在于，该第三晶体管的漏极及源极分别该驱动晶体管及该第二电源线。
  11. 如权利要求6所述的像素电路，其特征在于，该发光元件包括发光二极管，其阳极连接至该驱动晶体管并且其阴极连接至该第三电源线。
  12. 如权利要求11所述的像素电路，其特征在于，该第三电源线提供的电压为地电压。
  13. 如权利要求11所述的像素电路，其特征在于，该第一电源线提供的第一电压大于该第二电源线提供的第二电压。
  14. 如权利要求13所述的像素电路，其特征在于，该第一及第二电压之差大于该驱动晶体管的阈值电压，该第二电压与该第三电源线提供的第三电压之差小于该发光二极管的阈值电压。
  15. 一种显示面板，包括：
    多个阵列排布的如权利要求1或6所述的像素电路；
    扫描驱动单元，用于分别向该第一及第二扫描线提供扫描信号；
    发射控制驱动单元，用于向该控制线提供发射控制信号；
    数据驱动单元，用于向该数据线提供数据信号；
    第一电源，用于向该第一电源线提供第一电压；
    第二电源，用于向该第二电源线提供第二电压；及
    第三电源，用于向该第三电源线提供第三电压。
  16. 一种像素电路的驱动方法，应用于如权利要求1或6所述的像素电路，该驱动晶体管具有一个阈值电压，该驱动方法包括：
    使该第一至第三晶体管导通，该驱动电容存储的电荷分别通过该第一晶体管及第三晶体管向该数据线及第二电源线释放；
    使该第一及第二晶体管导通，第三晶体管截止，该数据线通过该第一晶体管向该驱动晶体管输出一个参考电压，该第一电源线提供的第一电压通过该第二晶体管及驱动晶体管向该驱动电容充电，直到该驱动晶体管控制极与一个受控极两端电压为该阈值电压；
    使该第一晶体管导通，而第二及第三晶体管截止，该数据线输出一个高于该参考电压的数据电压，该驱动电容两端电压被充电至该阈值电压与 另一电压值之和，该另一电压值与该数据电压与参考电压的差相关；及
    使该第一及第三晶体管截止，而第二晶体管导通，该驱动电容驱动该驱动晶体管导通进而使该第一电压驱动该发光元件发光。
  17. 如权利要求16所述的驱动方法，其特征在于，该驱动电容存储的电荷分别通过该第一晶体管及第三晶体管向该数据线及第二电源线释放的步骤还包括：使该数据线提供该参考电压，使该第二电源线提供一个第二电压，并且该第一及第二电压之差大于该阈值电压。
  18. 如权利要求17所述的驱动方法，其特征在于，该驱动电容存储的电荷分别通过该第一晶体管及第三晶体管向该数据线及第二电源线释放的步骤还包括：使该第二电压与该第三电源线提供的第三电压的压差小于该发光元件的阈值电压。
  19. 一种像素电路的驱动方法，应用于如权利要求1或6所述的像素电路，该驱动晶体管具有一个阈值电压，该驱动方法包括：
    使该第一至第三晶体管导通，从而使驱动晶体管导通并且该驱动电容及该发光元件各自两端的电压被重置；
    使该第一及第二晶体管导通，而第三晶体管截止，使该数据线输出一个参考电压从而使该驱动电容、驱动晶体管、发光元件相互连接的第一节点的电压为该参考电压与该阈值电压之差；
    使该第一及第二晶体管导通，而第三晶体管截止，使该数据线输出一个高于该参考电压的数据电压，从而使该驱动电容两端电压为该阈值电压与另一电压值之和，所述另一电压值与该数据电压与该参考电压的差相关；及
    使该第一及第三晶体管截止，而第二晶体管导通，从而利用该驱动电 容驱动该驱动晶体管导通进而使该第一电源线提供的第一电压驱动该发光元件发光。
  20. 如权利要求19所述的驱动方法，其特征在于，使该数据线提供该参考电压，使该第二电源线提供一个第二电压，并且该第一及第二电压之差大于该阈值电压，该第二电压与该第三电源线提供的第三电压的压差小于该发光元件的阈值电压。
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