WO2014061196A1 - Soiウェーハの製造方法 - Google Patents
Soiウェーハの製造方法 Download PDFInfo
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- WO2014061196A1 WO2014061196A1 PCT/JP2013/005396 JP2013005396W WO2014061196A1 WO 2014061196 A1 WO2014061196 A1 WO 2014061196A1 JP 2013005396 W JP2013005396 W JP 2013005396W WO 2014061196 A1 WO2014061196 A1 WO 2014061196A1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
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- C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
- C30B31/20—Doping by irradiation with electromagnetic waves or by particle radiation
- C30B31/22—Doping by irradiation with electromagnetic waves or by particle radiation by ion-implantation
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/06—Joining of crystals
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
Definitions
- the present invention manufactures an SOI wafer by a so-called ion implantation separation method (also called a Smart Cut (registered trademark) method) in which an ion-implanted wafer is bonded and then peeled to produce an SOI (Silicon on Insulator) wafer. Regarding the method.
- ion implantation separation method also called a Smart Cut (registered trademark) method
- an ion implantation separation method As a typical method for manufacturing an SOI wafer, there is an ion implantation separation method. Briefly describing this ion implantation separation method, first, two silicon wafers are prepared as a bond wafer and a base wafer, and at least one silicon wafer, for example, an oxide film to be a buried oxide film of an SOI wafer is formed on the bond wafer.
- ion implantation is performed through the oxide film from the surface to be a bonding surface of the silicon wafer on which the oxide film is formed, an ion implantation layer is formed in the silicon wafer, and the silicon on which the ion implantation layer is formed
- the silicon wafer is peeled off by the ion-implanted layer and separated into a peeled wafer and an SOI wafer by bonding and heat-treating the wafer and the base wafer.
- an SOI wafer is manufactured.
- Patent Document 5 a method of heat-treating the bond wafer in a non-oxidizing atmosphere or the like is also performed before manufacturing the SOI wafer.
- Patent Document 5 a method of heat-treating the bond wafer in a non-oxidizing atmosphere or the like is also performed before manufacturing the SOI wafer.
- the present invention has been made in view of the above problems, and in the manufacture of an SOI wafer, an SOI wafer capable of sufficiently eliminating defects of a bond wafer and manufacturing an SOI wafer having almost no defects such as defects.
- An object is to provide a manufacturing method. It is another object of the present invention to provide a method for manufacturing an SOI wafer in which a separation wafer generated as a by-product in the ion implantation separation method can be reused many times as a bond wafer.
- a step of preparing a silicon wafer cut from a silicon single crystal ingot grown by the Czochralski method as a bond wafer, and a step of forming an oxide film on the prepared silicon wafer A step of forming an ion implantation layer in the silicon wafer by performing ion implantation through the oxide film from a surface to be a bonding surface of the silicon wafer on which the oxide film is formed, and silicon on which the ion implantation layer is formed
- a method of manufacturing an SOI wafer comprising: bonding a wafer and a base wafer; separating the silicon wafer with the ion implantation layer and separating the wafer into a separation wafer and an SOI wafer; Before the oxide film forming step, the prepared silicon wafer is subjected to a heat treatment at a temperature of 1100 ° C. to 1250 ° C. for 30 minutes to 120 minutes in an oxidizing atmosphere, and the bonded surface of the silicon wafer after the heat
- an SOI wafer having almost no defects such as defects can be manufactured by sufficiently eliminating the defects of the bond wafer in manufacturing the SOI wafer. Further, a separation wafer generated as a by-product in the ion implantation separation method can be reused many times as a bond wafer.
- the polishing step after removing the oxide film formed on the silicon wafer after the heat treatment, it is preferable to polish the surface to be a bonding surface by 0.1 to 0.2 ⁇ m.
- the peeled wafer is reused as a bond wafer when manufacturing an SOI wafer.
- the exfoliated wafer produced as a by-product in the production method of the present invention has defects sufficiently eliminated by heat treatment and surface polishing under an oxidizing atmosphere in the present invention.
- a high-quality SOI wafer can be manufactured at a low cost.
- NPC N region
- a nitrogen-doped wafer having a nitrogen concentration of 1 ⁇ 10 13 to 1 ⁇ 10 15 atoms / cm 3 is preferable to use as the nitrogen-doped wafer.
- oxygen precipitation nuclei and oxygen precipitates that cause HF defects are completely extinguished into the bulk by heat treatment and surface polishing in an oxidizing atmosphere in the present invention. be able to.
- the defects related to oxygen precipitation in the bond wafer can be sufficiently eliminated, the generation of HF defects can be suppressed. Therefore, even if a heat treatment during the manufacturing process of the SOI wafer (heat treatment for forming an oxide film to be a buried oxide film of the SOI wafer) is performed, a bond wafer in which HF defects are not generated and grow can be obtained. Therefore, it is possible to efficiently manufacture a high-quality SOI wafer having almost no defects such as defects and excellent electrical characteristics. Further, since a separation wafer generated as a by-product in the ion implantation separation method can be reused many times as a bond wafer, the cost can be reduced and it is economical.
- an HF defect may be detected at the center by the oxidation heat treatment in the SOI wafer manufacturing process. Further, when the peeled wafer is reused as a bond wafer, it is necessary to perform a heat treatment each time or at least when a defect is confirmed to eliminate the surface layer defect.
- the present inventors can manufacture an SOI wafer having almost no defects such as defects, and the surface layer of the separation wafer is reused when the separation wafer generated as a by-product in the ion implantation separation method is reused as a bond wafer.
- the conditions under which HF defects were not formed even if the heat treatment for eliminating the crystal defects was not frequently performed were examined.
- the HF defect is a general term for crystal defects in the SOI layer detected by immersing the SOI wafer in the HF solution, and the HF solution etches the buried oxide film layer through the defect portion penetrating the SOI layer. The detected cavity is detected.
- a silicon wafer prepared as a bond wafer is subjected to a heat treatment in an oxygen atmosphere at a temperature of 1100 ° C. to 1250 ° C. for 30 minutes to 120 minutes as a pretreatment before the step of forming an oxide film to be a buried oxide film,
- heat treatment of the present invention for convenience
- FIG. 1 is a flowchart showing an example of an embodiment of a method for manufacturing an SOI wafer according to the present invention.
- a silicon wafer cut out from a silicon single crystal ingot grown by the Czochralski method is prepared as the bond wafer 1 (FIG. 1A).
- Examples of the silicon wafer to be prepared include a silicon wafer having at least one surface mirror-polished.
- the initial oxygen concentration is 14 ppma (JEIDA (Japan Electronics Industry Promotion Association)
- JEIDA is currently renamed as JEITA (Japan Electronics and Information Technology Industries Association) N region (NPC) wafer below or nitrogen with initial oxygen concentration below 7 ppma (JEIDA) It is particularly preferable to use a doped wafer.
- the initial oxygen concentration of the N region (NPC) wafer is 14 ppma (JEIDA) or less, and the nitrogen-doped wafer is not an N region wafer, the initial oxygen concentration is 7 ppma (JEIDA) or less. Even if the oxidation heat treatment of the process is repeated, HF defects are hardly formed by initially performing the heat treatment of the present invention.
- the defect size is reduced in a low oxygen concentration wafer, and even if it is not an N region wafer, the oxygen precipitation nuclei and oxygen precipitates that cause HF defects are completely extinguished by the above heat treatment to the bulk. be able to.
- a nitrogen-doped wafer it is more preferable to use a nitrogen-doped wafer having a nitrogen concentration of 1 ⁇ 10 13 to 1 ⁇ 10 15 atoms / cm 3 .
- the prepared silicon wafer is heat-treated at a temperature of 1100 ° C. to 1250 ° C. for 30 minutes to 120 minutes in an oxidizing atmosphere (FIG. 1B).
- an oxygen atmosphere or a mixed gas such as an oxygen gas and a rare gas (in this case, the oxygen gas content exceeds 50%) can be used.
- the atmosphere in which the heat treatment is performed may be appropriately selected according to the characteristics of the bond wafer to be used, but an oxygen atmosphere (oxygen gas 100%) is particularly preferable because defects can be eliminated efficiently.
- Such heat treatment can be performed, for example, in a resistance heating heat treatment furnace.
- the temperature during the heat treatment is 1100 ° C. to 1250 ° C., and the time is 30 minutes to 120 minutes.
- heat treatment exceeding 1250 ° C. imposes a burden on the bond wafer, and causes slip dislocation and impurity contamination. Further, since the defects in the bulk can be eliminated by performing the heat treatment for about 120 minutes, the heat treatment is performed at 1250 ° C. or less and 120 minutes or less from the viewpoint of the effect and efficiency of the heat treatment. Preferably, they are 1170 ° C. to 1200 ° C. and 60 minutes to 120 minutes.
- the polishing allowance of the surface to be the bonding surface of the silicon wafer can be determined as appropriate, but it is usually sufficient to carry out about 0.2 ⁇ m from the surface, and the polishing allowance of 0.1 to 0.2 ⁇ m is sufficient. More preferred.
- the oxide film 2 may be formed by the heat treatment of the present invention.
- Polishing shown in FIG. 1 (d) may be performed.
- the oxide film 2 can be removed by etching or the like. In the above polishing, the oxide film may be removed by polishing first, and then the bonded surface of the silicon wafer (bond wafer 1) may be continuously polished.
- an oxide film 3 to be a buried oxide film 8 of the SOI wafer is formed on the silicon wafer (bond wafer 1) (FIG. 1E).
- the oxide film 3 can be formed by performing a heat treatment at a temperature of about 900 to 1200 ° C. for 5 to 6 hours, for example.
- the oxide film 3 is formed on the entire surface of the silicon wafer (bond wafer 1), but the oxide film 3 may be formed only on the bonding surface.
- ion implantation is performed through the oxide film 3 from the surface to be a bonding surface of the silicon wafer on which the oxide film 3 is formed, thereby forming an ion implantation layer 4 in the silicon wafer (FIG. 1F).
- the depth of the ion implantation layer 4 is determined by the ion implantation energy. Therefore, a large implantation energy is required for deep implantation, but in a normal case, the implantation is performed at a depth of about 2 ⁇ m or less at a depth of 1 ⁇ m or less even when deep from the surface of the oxide film 3.
- the silicon wafer (bond wafer 1) on which the ion-implanted layer 4 is formed and the base wafer 5 are formed on the oxide film 3
- the ion-implanted layer 4 side is bonded through (FIG. 1 (g)).
- the silicon wafer (bond wafer 1) is peeled off by the ion implantation layer 4 and separated into the peeling wafer 6 and the SOI wafer 7 (FIG. 1 (h)).
- the bonding surface of one or both wafers is subjected to plasma treatment to increase the bonding strength, thereby eliminating the peeling heat treatment and mechanically peeling. It can also be made.
- an SOI wafer having a defect-free SOI layer can be obtained by bonding heat treatment for increasing the bonding strength or polishing the surface of the separated SOI wafer 7 (FIG. 1 (j )).
- the peeled wafer 6 by-produced by the manufacturing method of the present invention as described above is reused as a bond wafer in the manufacture of other SOI wafers.
- the bonded wafer subjected to the heat treatment and surface polishing of the present invention has almost no oxygen precipitation nuclei or oxygen precipitates, that is, a peeled wafer after the SOI layer of about 1 ⁇ m is peeled off. Even so, there are almost no oxygen precipitation nuclei and oxygen precipitates. Accordingly, since the peeled wafer 6 can be used again as a bond wafer only by polishing with a small polishing allowance (FIG. 1 (i)), an SOI wafer can be manufactured with high productivity and low cost.
- the polishing allowance of the release surface is not particularly limited, but in order to surely remove the step formed on the periphery of the release surface and the distortion of the ion implantation layer and sufficiently suppress the occurrence of bonding failure.
- the polishing allowance is 3 ⁇ m or more, preferably more than 5 ⁇ m.
- Example 1 Comparative Examples 1 to 3
- An oxidation heat treatment at 900 ° C./6 hrs is performed, (2) the oxide film is removed with HF (pseudo-peeling), and (3) SP1 manufactured by KLA Tencor is used.
- the “pseudo-peeling” in (2) refers to the peeling process (bonding with the base wafer + peeling at the ion-implanted layer) performed in the SOI wafer manufacturing process, and the bond wafer after the oxidation heat treatment in (1). It is known that the same tendency as the result of measuring the HF defect density of an actual SOI wafer can be obtained even if the oxide film is replaced with a step of removing the oxide film with HF and evaluated in this way. .
- Condition 1 NPC + no heat treatment
- Condition 2 NPC + RTA (Ar atmosphere, heating rate 50 ° C./second, maximum temperature 1250 ° C., holding time 10 seconds)
- Condition 3 NPC + resistance heating (Ar atmosphere, 1200 ° C., 60 minutes)
- Condition 4 NPC + resistance heating (oxygen atmosphere, 1200 ° C., 60 minutes) +0.1 ⁇ m surface polishing
- Example 2 Verification of effect due to difference in initial oxygen concentration between nitrogen-doped wafer and NPC wafer Diameter 200 mm, nitrogen concentration 5 ⁇ 10 13 atoms / cm 3 , initial oxygen concentration 3 to 17 ppma wafer, diameter 200 mm, N region (NPC), initial A wafer having an oxygen concentration of 3 to 17 ppma was subjected to a heat treatment at 1200 ° C. for 60 minutes in an oxygen atmosphere, and then the pseudo regeneration method was repeated five times in the same manner as in Example 1 to measure the HF defect density. The results are shown in FIG.
- Example 3 Manufacturing of SOI wafers 1
- a bond wafer a mirror-polished silicon wafer having a diameter of 200 mm, an N region (NPC), and an initial oxygen concentration of 12 ppma was prepared, and heat treatment for eliminating defects of the bond wafer was performed at 1200 ° C. for 60 minutes in an oxygen atmosphere. Then, after removing the oxide film by etching with HF, the surface to be the bonded surface was polished by 0.1 ⁇ m. Then, (i) after performing an oxidation heat treatment at 900 ° C./6 hrs to form an oxide film, (ii) hydrogen ions are implanted through this oxide film (implantation conditions are acceleration energy 70 keV, implantation amount 6 ⁇ 10 16 / cm 2.
- the obtained SOI wafer was a high-quality one having no defects such as defects in the SOI layer and excellent electrical characteristics.
- Example 4 Manufacturing of SOI wafers 2 An SOI wafer was prepared in the same manner as in Example 3 except that a bonded wafer was prepared as a mirror-polished silicon wafer having a diameter of 200 mm, nitrogen dope (nitrogen concentration 5 ⁇ 10 13 atoms / cm 3 ), and initial oxygen concentration 6 ppma. Produced.
- the HF defect was at a level with no problem.
- the obtained SOI wafer was a high-quality one having no defects such as defects in the SOI layer and excellent electrical characteristics.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.
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Abstract
Description
このイオン注入剥離法を簡単に説明すると、まず、ボンドウェーハ及びベースウェーハとして、2枚のシリコンウェーハを準備し、少なくとも一方のシリコンウェーハ、例えばボンドウェーハにSOIウェーハの埋め込み酸化膜となる酸化膜を形成した後に、該酸化膜を形成したシリコンウェーハの貼り合わせ面となる表面から前記酸化膜を通してイオン注入を行って、前記シリコンウェーハ中にイオン注入層を形成し、該イオン注入層を形成したシリコンウェーハとベースウェーハを貼り合わせて熱処理することによって、前記シリコンウェーハを前記イオン注入層で剥離して剥離ウェーハとSOIウェーハとに分離させ、その後更に必要に応じて、結合熱処理を加えて強固に結合して、SOIウェーハを製造する方法である。
しかし、このようなRTA処理はその都度行わなければならず、また何度もRTA処理を繰り返すとボンドウェーハが破損しやすくなるという問題があった。
しかし、このような方法であっても、再利用する前の検査で欠陥が確認された場合には、再度熱処理を行う必要があった。
また、SOIウェーハのコスト低減を実現するため、ボンドウェーハの再利用を考えると、バルクまで完全に無欠陥となるウェーハの作製技術の開発が必要である。
前記酸化膜形成工程の前に、前記準備したシリコンウェーハに酸化性雰囲気下で1100℃~1250℃の温度で30分~120分間の熱処理を施す工程、及び該熱処理後のシリコンウェーハの貼り合わせ面となる表面を研磨する工程を行うことを特徴とするSOIウェーハの製造方法を提供する。
前述のように、従来SOIウェーハの製造においては、SOIウェーハ製造工程の酸化熱処理により中心部にHF欠陥が検出されることがあった。また、剥離したウェーハをボンドウェーハとして再利用する際には、その都度、又は少なくとも欠陥が確認された場合には熱処理を行い、表層の欠陥を消滅させる必要があった。
図1は、本発明のSOIウェーハの製造方法の実施態様の一例を示すフロー図である。
まず、本発明の製造方法では、ボンドウェーハ1として、チョクラルスキー法により育成されたシリコン単結晶インゴットから切り出されたシリコンウェーハを準備する(図1(a))。
窒素ドープウェーハを用いる場合には、窒素濃度が1×1013~1×1015atoms/cm3の窒素ドープウェーハを用いることがより好ましい。
酸化性雰囲気としては、酸素雰囲気や、酸素ガスと希ガス等の混合ガス(この場合、酸素ガスの含有率は50%を超えるものとする)を用いることができる。どのような雰囲気で熱処理するかは使用するボンドウェーハの特性に従い適宜選択すればよいが、効率よく欠陥を消滅させることができることから、酸素雰囲気(酸素ガス100%)が特に好ましい。
熱処理の際の温度は1100℃~1250℃、時間は30分~120分間である。
好ましくは、1170℃~1200℃、60分~120分である。
酸化膜2の除去は、エッチング等により行うことができる。また、上述の研磨の際、先に酸化膜を研磨により除去してから、シリコンウェーハ(ボンドウェーハ1)の貼り合わせ面の研磨を連続して行っても良い。
イオン注入層4の深さは、イオン注入エネルギーにより決定される。従って、深く注入するためには大きな注入エネルギーが必要とされるが、通常の場合、酸化膜3表面から深くても2μm程度であり、1μm以下の深さに注入することが多い。
(実施例1、比較例1~3)
抵抗加熱処理の効果の証明
直径200mm、N領域(NPC)、初期酸素濃度12ppmaのシリコンウェーハに、前処理なし(条件1)、RTA(条件2)、抵抗加熱処理(条件3)、又は抵抗加熱処理+研磨(条件4)を行った後、(1)900℃/6hrsの酸化熱処理を行い、(2)HFで酸化膜を除去(擬似剥離)した後に、(3)KLAテンコール社製SP1で65nm以上の表面のHF欠陥密度を測定し、(4)その後5μm研磨して、これを再生回数0回目とし、更に(1)~(4)を繰り返すことで擬似的にボンドウェーハの再利用工程を行い再生回数別のHF欠陥密度を比較した。結果を図2に示す。
条件1:NPC+熱処理なし
(比較例2)
条件2:NPC+RTA(Ar雰囲気、昇温速度50℃/秒、最高温度1250℃、保持時間10秒)
(比較例3)
条件3:NPC+抵抗加熱(Ar雰囲気、1200℃、60分)
(実施例1)
条件4:NPC+抵抗加熱(酸素雰囲気、1200℃、60分)+0.1μm表面研磨
窒素ドープウェーハ及びNPCウェーハの初期酸素濃度の違いによる効果の検証
直径200mm、窒素濃度5×1013atoms/cm3、初期酸素濃度3~17ppmaのウェーハ、及び直径200mm、N領域(NPC)、初期酸素濃度3~17ppmaのウェーハに、酸素雰囲気下で1200℃、60分間の熱処理を行い、その後、実施例1と同様に擬似的な再生方法を5回繰り返し、HF欠陥密度を測定した。結果を図3に示す。
SOIウェーハの製造1
ボンドウェーハとして、直径200mm、N領域(NPC)、初期酸素濃度12ppmaの鏡面研磨されたシリコンウェーハを準備し、ボンドウェーハの欠陥消滅のための熱処理を、酸素雰囲気で1200℃、60分行った後、HFでエッチングして酸化膜を除去してから貼り合わせ面となる表面を0.1μm研磨した。そして、(i)900℃/6hrsの酸化熱処理を行って酸化膜を形成した後、(ii)この酸化膜を通して水素イオンを注入(注入条件は、加速エネルギー70keV、注入量6×1016/cm2である)し、(iii)イオン注入したボンドウェーハを、ベースウェーハ(シリコンウェーハ)と室温で貼り合わせた後、500℃、30分の剥離熱処理を加えることにより、イオン注入層で剥離し、SOIウェーハを作製した。
再生回数5回目のHF欠陥を測定した結果、HF欠陥は問題のないレベルであった。
SOIウェーハの製造2
ボンドウェーハとして、直径200mm、窒素ドープ(窒素濃度5×1013atoms/cm3)、初期酸素濃度6ppmaの鏡面研磨されたシリコンウェーハを準備した以外は、実施例3と同様にして、SOIウェーハを作製した。
また、得られたSOIウェーハは、SOI層に欠陥等の不良がなく、電気特性に優れた高品質のものであった。
Claims (5)
- チョクラルスキー法により育成されたシリコン単結晶インゴットから切り出されたシリコンウェーハをボンドウェーハとして準備する工程と、該準備したシリコンウェーハに酸化膜を形成する工程と、該酸化膜を形成したシリコンウェーハの貼り合わせ面となる表面から前記酸化膜を通してイオン注入を行って、前記シリコンウェーハ中にイオン注入層を形成する工程と、該イオン注入層を形成したシリコンウェーハとベースウェーハを貼り合わせて、前記シリコンウェーハを前記イオン注入層で剥離して剥離ウェーハとSOIウェーハとに分離させる工程とを含むSOIウェーハを製造する方法であって、
前記酸化膜形成工程の前に、前記準備したシリコンウェーハに酸化性雰囲気下で1100℃~1250℃の温度で30分~120分間の熱処理を施す工程、及び該熱処理後のシリコンウェーハの貼り合わせ面となる表面を研磨する工程を行うことを特徴とするSOIウェーハの製造方法。 - 前記研磨工程において、前記熱処理後のシリコンウェーハに形成された酸化膜を除去した後、貼り合わせ面となる表面を0.1~0.2μm研磨することを特徴とする請求項1に記載のSOIウェーハの製造方法。
- 前記剥離ウェーハを、SOIウェーハの製造の際にボンドウェーハとして再利用することを特徴とする請求項1又は請求項2に記載のSOIウェーハの製造方法。
- 前記準備するシリコンウェーハとして、初期酸素濃度が14ppma以下のN領域(NPC)のウェーハ又は初期酸素濃度が7ppma以下の窒素ドープウェーハを用いることを特徴とする請求項1乃至請求項3のいずれか1項に記載のSOIウェーハの製造方法。
- 前記窒素ドープウェーハとして、窒素濃度が1×1013~1×1015atoms/cm3の窒素ドープウェーハを用いることを特徴とする請求項4に記載のSOIウェーハの製造方法。
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US14/426,582 US20150287630A1 (en) | 2012-10-16 | 2013-09-12 | Method of manufacturing soi wafer |
KR1020157005883A KR20150070096A (ko) | 2012-10-16 | 2013-09-12 | Soi 웨이퍼의 제조방법 |
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WO2004073057A1 (ja) * | 2003-02-14 | 2004-08-26 | Sumitomo Mitsubishi Silicon Corporation | シリコンウェーハの製造方法 |
JP2006294737A (ja) | 2005-04-07 | 2006-10-26 | Sumco Corp | Soi基板の製造方法及びその製造における剥離ウェーハの再生処理方法。 |
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JP2012153548A (ja) * | 2011-01-24 | 2012-08-16 | Shin Etsu Handotai Co Ltd | シリコン単結晶ウェーハの製造方法及びアニールウェーハ |
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