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WO2013133015A1 - 半導体装置の製造方法および半導体装置の製造装置 - Google Patents

半導体装置の製造方法および半導体装置の製造装置 Download PDF

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Publication number
WO2013133015A1
WO2013133015A1 PCT/JP2013/054096 JP2013054096W WO2013133015A1 WO 2013133015 A1 WO2013133015 A1 WO 2013133015A1 JP 2013054096 W JP2013054096 W JP 2013054096W WO 2013133015 A1 WO2013133015 A1 WO 2013133015A1
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WIPO (PCT)
Prior art keywords
semiconductor chip
thermosetting adhesive
adhesive layer
substrate
semiconductor
Prior art date
Application number
PCT/JP2013/054096
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English (en)
French (fr)
Inventor
朝日昇
野中敏央
新関彰一
Original Assignee
東レ株式会社
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Filing date
Publication date
Application filed by 東レ株式会社 filed Critical 東レ株式会社
Priority to SG11201405431TA priority Critical patent/SG11201405431TA/en
Priority to KR1020147026562A priority patent/KR20140140042A/ko
Priority to CN201380012563.6A priority patent/CN104145328A/zh
Priority to US14/383,494 priority patent/US20150050778A1/en
Publication of WO2013133015A1 publication Critical patent/WO2013133015A1/ja
Priority to PH12014501961A priority patent/PH12014501961A1/en

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    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/0046—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by constructional aspects of the apparatus
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B32B38/00—Ancillary operations in connection with laminating processes
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    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Definitions

  • the present invention relates to a manufacturing method and a manufacturing apparatus of a semiconductor device used for a personal computer or a portable terminal. More specifically, the present invention relates to a semiconductor device in which a semiconductor chip such as an IC or LSI is solder-connected to a circuit board such as a flexible substrate, a glass epoxy substrate, a glass substrate, a ceramic substrate, a silicon interposer, or a silicon substrate, or a semiconductor The present invention relates to a manufacturing method and a manufacturing apparatus of a semiconductor device such as a semiconductor chip laminated body in which chips are solder-connected.
  • JP 2001-237268 A (Claims 1, pages 3 to 4) JP 2004-315688 A (Claims) JP 2004-319823 A (Claims) JP 2006-229124 A (Claims) JP 2009-116326 A (Claims) JP 2010-226098 A (Claims)
  • a semiconductor device manufacturing method and a manufacturing apparatus in which a good solder connection can be obtained without the resin of the adhesive film being sandwiched between the bump and the electrode pad and without contaminating the heat tool.
  • a first method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a semiconductor chip having a bump is solder-connected to a substrate having an electrode corresponding to the bump via a thermosetting adhesive layer. : (A) A step of forming a thermosetting adhesive layer in advance on the surface of the semiconductor chip having bumps; (B) A step of combining the surface on the thermosetting adhesive layer side of the semiconductor chip on which the thermosetting adhesive layer is formed and the substrate, and temporarily pressing using a heat tool to obtain a temporary pressing laminate, (C) A protective film having a thermal conductivity of 100 W / mK or more is interposed between the heat tool and the surface on the semiconductor chip side of the temporary pressure-bonded laminate, and the heat tool is used between the semiconductor chip and the substrate. A step of melting the solder of the thermosetting adhesive layer at the same time, In this order.
  • thermosetting adhesive layer a semiconductor device in which a plurality of semiconductor chips having bumps and through electrodes and a substrate having electrodes corresponding to the bumps are solder-connected via a thermosetting adhesive layer.
  • Manufacturing method (A ′) a step of forming a plurality of semiconductor chips each having a thermosetting adhesive layer by forming a thermosetting adhesive layer in advance on a surface having a bump of each of the plurality of semiconductor chips; (B ′) a step of combining the surface of the thermosetting adhesive layer side of one semiconductor chip on which the thermosetting adhesive layer is formed and the substrate, and temporarily pressing using a heat tool, and at least once
  • the step of joining the surface of the semiconductor chip of the semiconductor chip to the surface of the thermosetting adhesive layer of another semiconductor chip on which the thermosetting adhesive layer is formed is subjected to a temporary pressure bonding using a heat tool.
  • a protective film having a thermal conductivity of 100 W / mK or more is interposed between the heat tool and the semiconductor chip side surface of the multistage temporary press-bonded laminate. Melting the solder between the semiconductor chip and the semiconductor chip and the substrate and simultaneously curing the thermosetting adhesive layer;
  • the semiconductor device manufacturing apparatus of the present invention is an apparatus for manufacturing a semiconductor device by bonding a substrate and a semiconductor chip, A stage for installing a substrate, a bonding apparatus provided with a heat tool having a mechanism for heating and pressurizing a semiconductor chip, a supply reel for supplying a protective film having a thermal conductivity of 100 W / mK or more, and the protective film A take-up reel that winds up,
  • This is a semiconductor device manufacturing apparatus in which a protective film supplied from a supply reel passes between a heat tool and a stage and is wound around a take-up reel.
  • the bump and the electrode pad can be easily soldered via the thermosetting adhesive layer, and the semiconductor device can be manufactured with a high yield.
  • the semiconductor device in the present invention refers to all devices that can function by utilizing the characteristics of semiconductor elements.
  • An electro-optical device in which a semiconductor chip is connected to a substrate, a semiconductor circuit substrate, and an electronic component including these are all included in the semiconductor device.
  • a semiconductor device in which a semiconductor chip having connection terminals such as electrode pads and bumps formed on both sides of a silicon chip having through electrodes TSV (through silicon vias) and a plurality of such silicon chips are three-dimensionally stacked is also used in a semiconductor device. included.
  • Examples of the semiconductor chip include, but are not limited to, an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, and a diode.
  • a semiconductor such as silicon (Si) or germanium (Ge) or a compound semiconductor such as gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), or silicon carbide (SiC) is used.
  • Si silicon
  • germanium germanium
  • a compound semiconductor such as gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), or silicon carbide (SiC) is used.
  • GaAs gallium arsenide
  • GaP gallium phosphide
  • InP indium phosphide
  • SiC silicon carbide
  • bumps are formed on the semiconductor chip from the viewpoint of connection reliability and the like.
  • the material of the bump there is no particular limitation on the material of the bump, and metals that can be generally used in semiconductor devices such as aluminum, copper, titanium, tungsten, chromium, nickel, gold, solder, and alloys using them can be used.
  • the material of either the bumps or the electrode pads is solder.
  • a bump since it heats from the semiconductor chip side with a heat tool, it is more preferable to use a bump as a solder bump because heat is easily transmitted to the solder.
  • the material of the solder is not particularly limited, but it is preferable to use a lead-free solder such as SnAgCu-based, SnCu-based, SnAg-based, SnAgCuBi-based, SnZnBi-based, SnAgInBi-based from the viewpoint of influence on the human body and the environment.
  • the solder bump is preferably formed on a metal pillar, particularly a copper pillar.
  • a barrier metal layer for suppressing metal diffusion can also be provided between the solder and the metal pillar.
  • the shape of a solder bump is hemispherical from a viewpoint that resin or a filler is hard to be pinched
  • the bumps on the semiconductor chip are all evenly arranged.
  • the bump height variation is preferably 0.5 ⁇ m or less. If the variation is 0.5 ⁇ m or less, the semiconductor chip can be mounted without poor connection when the bumps are crimped. More preferably, the variation in bump height is 0.2 ⁇ m or less. In order to reduce the variation in bump height, it is possible to perform grinding on the bump.
  • the substrate examples include a semiconductor substrate such as a silicon substrate, a ceramic substrate, a compound semiconductor substrate, an organic circuit substrate, an inorganic circuit substrate, and a substrate in which circuit constituent materials are arranged.
  • a semiconductor substrate such as a silicon substrate, a ceramic substrate, a compound semiconductor substrate, an organic circuit substrate, an inorganic circuit substrate, and a substrate in which circuit constituent materials are arranged.
  • the silicon substrate the above-described semiconductor chip, particularly a semiconductor chip having a TSV structure can also be used. In this case, a plurality of semiconductor chips are bonded to each other.
  • the semiconductor chip regardless of the type of member used, the one that is in contact with the heat seal through the protective film is called a “semiconductor chip”.
  • a device placed on a stage described later is called a “substrate”.
  • organic circuit boards include: glass substrate copper-clad laminates such as glass cloth and epoxy copper-clad laminates; composite copper-clad laminates such as glass nonwoven fabrics and epoxy copper-clad laminates; polyetherimide resin substrates, poly Heat-resistant / thermoplastic substrates such as ether ketone resin substrates and polysulfone-based resin substrates; polyester copper-clad film substrates; flexible substrates such as polyimide copper-clad film substrates.
  • the inorganic circuit board include ceramic substrates such as an alumina substrate, an aluminum nitride substrate, and a silicon carbide substrate; and metal substrates such as an aluminum base substrate and an iron base substrate.
  • the present invention works effectively when using a silicon substrate, particularly a semiconductor chip having a TSV structure, used for a multilayer substrate having a high thermal conductivity and a thin film.
  • constituent materials of circuits on the substrate are conductors containing metals such as silver, gold, copper and aluminum; resistors containing inorganic oxides; low dielectrics containing glass materials and / or resins, etc. Body; high dielectric containing resin, high dielectric constant inorganic particles, etc .; insulator containing glass-based material and the like.
  • the substrate has electrode pads corresponding to the bump positions of the semiconductor chip.
  • the electrode pad may be flat or may be a so-called pillar-shaped (columnar) protrusion.
  • the shape of the electrode pad may be a circle or a polygon such as a rectangle or an octagon.
  • metals that can be generally used in semiconductor devices, such as aluminum, copper, titanium, tungsten, chromium, nickel, gold, solder, and alloys using them, can be used. These metals can also be laminated.
  • the electrode pad preferably has a height variation of 0.5 ⁇ m or less, and can be ground.
  • a first method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a semiconductor chip having a bump is solder-connected to a substrate having an electrode corresponding to the bump via a thermosetting adhesive layer. : (A) A step of forming a thermosetting adhesive layer in advance on the surface of the semiconductor chip having bumps; (B) A step of combining the surface on the thermosetting adhesive layer side of the semiconductor chip on which the thermosetting adhesive layer is formed and the substrate, and temporarily pressing using a heat tool to obtain a temporary pressing laminate, (C) A protective film having a thermal conductivity of 100 W / mK or more is interposed between the heat tool and the surface on the semiconductor chip side of the temporary pressure-bonded laminate, and the heat tool is used between the semiconductor chip and the substrate. A step of melting the solder of the thermosetting adhesive layer at the same time, In this order.
  • thermosetting adhesive layer is formed in advance on the surface of the semiconductor chip having the bumps.
  • the surface of the thermosetting adhesive layer of the thermosetting adhesive film in which the thermosetting adhesive layer is formed on the releasable plastic film is overlaid on the surface of the bump side of the semiconductor chip with bumps.
  • the method of heating lamination or vacuum heating lamination while applying pressure is preferable because the operation is simple and the adhesive does not protrude from the semiconductor chip.
  • the temperature at the time of laminating is preferably 60 ° C. or higher from the viewpoint of following the unevenness of the thermosetting adhesive layer.
  • it is preferable that temperature is 100 degrees C or less.
  • the dynamic viscosity of the thermosetting adhesive layer is preferably 50 to 5000 Pa ⁇ s.
  • the dynamic viscosity of the thermosetting adhesive layer is 50 Pa ⁇ s or more, handling is easy, and when it is 5000 Pa ⁇ s or less, the bumps are easily embedded in the thermosetting adhesive layer, so that lamination at a low pressure is possible. It becomes possible.
  • the releasable plastic film of the thermosetting adhesive film is peeled off and the thermosetting adhesive layer is exposed.
  • the dynamic viscosity of the thermosetting adhesive layer can be measured by a dynamic viscoelasticity method using, for example, a rheometer (manufactured by Seiko Instruments Inc., DMS6100).
  • thermosetting adhesive layer can be formed by applying a liquid thermosetting adhesive to the surface of the semiconductor chip having bumps.
  • the coating method is not particularly limited, and a spinner, screen printing, blade coater, die coater or the like can be used. In this case, it is preferable to dry the thermosetting adhesive layer from the viewpoint of handling of the semiconductor chip up to the bonding step.
  • thermosetting adhesive layer on the surface of the semiconductor wafer on which a large number of semiconductor chips are formed, on which bumps are formed
  • a semiconductor chip with a thermosetting adhesive layer can be made by dicing the semiconductor wafer together with the thermosetting adhesive layer. This method is preferable because the thermosetting adhesive layer and the semiconductor chip can be formed in the same shape, and the protrusion of the thermosetting adhesive layer during bonding can be minimized.
  • the thermosetting adhesive layer may be made of only an insulating resin, or may contain other components in the insulating resin.
  • a plurality of types of insulating resins may be mixed.
  • the insulating resin a polyimide resin, an epoxy resin, an acrylic resin, a phenoxy resin, a polyethersulfone resin, or the like can be used, but the insulating resin is not limited thereto.
  • You may further contain a hardening
  • the thermosetting adhesive layer preferably contains an insulating inorganic filler from the viewpoint of insulation reliability and reliability against temperature cycles.
  • an insulating inorganic filler silica, silicon nitride, alumina, aluminum nitride, titanium oxide, titanium nitride, barium titanate, or the like can be used. Since the insulating inorganic filler may be sandwiched between the bump and the electrode pad in the same manner as the resin, it can be preferably manufactured by using the method for manufacturing a semiconductor device of the present invention.
  • thermosetting adhesive layer may have photosensitivity.
  • photosensitivity after forming a film or attaching a sheet, pattern processing can be performed by exposure and development to open a necessary portion such as a bump forming portion.
  • thermosetting adhesive used in the present invention examples include resin compositions disclosed in Japanese Patent Application Laid-Open No. 2004-319823, Japanese Patent Application Laid-Open No. 2008-94870, Japanese Patent No. 3995022, Japanese Patent Application Laid-Open No. 2009-262227, and the like. Can be used.
  • the thickness of the thermosetting adhesive layer is preferably equal to or greater than the average height of the bumps. More preferably, it is not less than the average height of the bumps and not more than 1.5 times the total thickness of the average height of the bumps and the average height of the electrode pads on the substrate. Even more preferably, it is not less than the average height of the bumps and not more than the sum of the average height of the bumps and the average height of the electrode pads on the substrate.
  • the height of the bump and the height of the electrode pad can be obtained by measuring the shape of the surface of the semiconductor chip and the substrate, respectively, and measuring the peak value of the height with the lowest height as a reference (0 ⁇ m). Can do.
  • the average height of the bumps and the average height of the electrode pads are the average values of the heights of all the bumps on the semiconductor chip and all the electrode pads on the substrate, for example, a confocal microscope (H1200 manufactured by Lasertec Corporation). Can be measured. If the thickness of the thermosetting adhesive layer is equal to or greater than the average height of the bumps, voids are unlikely to occur between the thermosetting adhesive layer after bonding and the substrate, and the adhesive strength may be reduced. Less likely to affect reliability.
  • thermosetting adhesive layer is 1.5 times or less the sum of the average height of the bump and the average height of the electrode pad on the substrate, not only is it excellent in economic efficiency, As the amount of protrusion of the curable adhesive layer is reduced, the mounting area is reduced, or the protruding thermosetting adhesive layer wraps around the top of the semiconductor chip and contaminates the heat tool of the bonding device. Less sticking.
  • step (B) temporary pressure bonding is performed.
  • the temporary press bonding step is a step of applying heat and pressure so that the semiconductor chip and the substrate are fixed using a heat tool, but the curing of the thermosetting adhesive does not proceed.
  • the pre-bonding step the surface of the semiconductor chip on which the thermosetting adhesive layer is formed and the substrate side are aligned and pre-bonded using the heat tool of the bonding apparatus, and the pre-bonded laminate Form.
  • thermosetting adhesive layer is preferably transparent so that the alignment mark can be recognized.
  • the temperature of the heat tool at the time of pre-bonding is lower than the melting point of the solder, lowering the viscosity of the thermosetting adhesive layer to increase the stickiness, so that the semiconductor chip is fixed in place, and the thermosetting adhesive A temperature range of 60 to 120 ° C. is preferable so that curing of the resin does not proceed.
  • the pressure at the time of temporary pressure bonding is preferably in the range of 0.01 to 0.5 MPa. If the pressure is 0.01 MPa or more, the purpose of the temporary pressure bonding can be sufficiently achieved, and if it is 0.5 MPa or less, the pressure bonding can be performed without significant deformation of the bumps.
  • Temporary pressure bonding may be performed under normal pressure, or may be performed in a vacuum in order to prevent entrapment of bubbles.
  • the temperature is the temperature in the thermosetting adhesive layer, and can be determined by connecting a thermocouple to a temperature recorder (manufactured by Keyence Corporation, NR100), for example.
  • a protective film having a thermal conductivity of 100 W / mK or more can be attached to the surface of the heat tool that contacts the semiconductor chip.
  • the main press-bonding process described later can be performed continuously without once separating the heat tool from the semiconductor chip.
  • a protective film can be attached on the stage on which the substrate is placed so as not to contaminate the stage.
  • step (C) the main press bonding is performed.
  • the main pressure bonding step is a step of applying heat and pressure so as to melt the solder between the semiconductor chip and the substrate and cure the thermosetting adhesive layer using a heat tool.
  • a protective film having a thermal conductivity of 100 W / mK or more is interposed between the heat tool and the surface of the temporary pressure-bonded laminate on the semiconductor chip side, and the heat tool is used between the semiconductor chip and the substrate.
  • the thermosetting adhesive layer is cured.
  • the temperature of the heat tool at the time of final pressing is preferably in the temperature range of 220 to 300 ° C. so that the solder melts.
  • This heat treatment may be performed by raising the temperature stepwise or continuously.
  • the heating time is preferably 1 second to several minutes.
  • the temperature rise time at that time is preferably 1 second or less from the viewpoint of the fluidity of the adhesive and the timing of solder melting.
  • the rise time is a time during which the surface temperature of the heat tool changes by 90% or more from the current temperature toward the set temperature.
  • the pressure during the main press-bonding is preferably in the range of 0.01 to 1 MPa from the viewpoint of the solder push-in amount.
  • the pressure at this time can also be changed over time. It is also possible to perform height control for fixing the position of the heat tool when the solder is melted.
  • the heat treatment may be performed under normal pressure or in a vacuum. Moreover, in order to prevent the oxidative deterioration by air, you may implement in nitrogen atmosphere.
  • the protective film used in the present invention is a film having a thermal conductivity of 100 W / mK or more, and preferably 200 W / mK or more.
  • the heat tool can be prevented from being contaminated by the thermosetting adhesive.
  • the flatness of the heat tool is impaired, the thermocompression bonding state of the semiconductor chip during bonding becomes uneven, and bonding failure occurs.
  • Such a problem can be prevented by using a protective film.
  • the thermal conductivity of the protective film is 100 W / mK or more, heat can be transferred from the heat tool to the solder bumps of the semiconductor chip or the solder electrode pads of the substrate in a short time.
  • thermosetting adhesive layer As a result, it is possible to melt the solder in a state where there is fluidity before the thermosetting adhesive layer is cured.
  • the bump and the electrode pad can be joined without sandwiching the resin contained in the thermosetting adhesive layer.
  • thermosetting Curing of the adhesive layer proceeds. In that case, when bonding a bump and an electrode pad, the thermosetting adhesive which lost fluidity will be pinched
  • the thickness of the protective film is preferably 5 ⁇ m or more and 20 ⁇ m or less. If thickness is 5 micrometers or more, since the intensity
  • the material of the protective film various materials having a thermal conductivity of 100 W / mK or more can be used. Of these, copper foil and aluminum foil with high thermal conductivity and excellent workability are desirable.
  • the copper foil may contain impurities other than copper, but the amount of impurities is preferably 10% by weight or less, more preferably 1% by weight or less, based on the total weight of the copper foil.
  • the aluminum foil may also contain impurities other than aluminum, but the amount of impurities is preferably 10% by weight or less, more preferably 1% by weight or less, based on the total weight of the aluminum foil.
  • the protective film may have a structure in which two or more kinds of metal foils and an anti-sticking film are laminated.
  • the thermal conductivity is a value of the entire laminated structure.
  • the thermal conductivity of the protective film can be measured using, for example, a thermal diffusivity measuring system (manufactured by Eye Phase Co., Ltd., 1 ⁇ m).
  • Additional curing may be performed after the main crimping step.
  • the conditions for the additional curing can be arbitrarily set according to the characteristics of the thermosetting adhesive used.
  • thermosetting adhesive film in which the thermosetting adhesive layer 4 is formed on the plastic film 10 is laminated on the surface of the semiconductor chip 3 on which the solder bumps 8 are formed.
  • the surface of the thermosetting adhesive film on the side of the thermosetting adhesive layer 4 is laminated with the surface of the semiconductor chip 3 on which the solder bumps 8 are formed, and is laminated by applying pressure while heating.
  • thermosetting adhesive layer 4 since it is preferable to laminate so that there is no void between the thermosetting adhesive layer 4 and the semiconductor chip 3, it is preferable to laminate in a vacuum.
  • a vacuum pressurization laminator manufactured by Meiki Seisakusho, MVLP500 / 600.
  • the heating method may be from the semiconductor chip side, the plastic film side, or both sides.
  • the laminating pressure is preferably 0.1 MPa to 1 MPa so that the thermosetting adhesive layer 4 can follow the unevenness of the solder bumps 8 and the solder bumps 8 are not crushed.
  • the semiconductor film (FIG. 2B) on which the thermosetting adhesive layer 4 is formed can be obtained by peeling the plastic film 10 from the thermosetting adhesive layer 4.
  • FIG. 2 (c) shows an example of the temporary press bonding step of step (B).
  • a flip chip bonder for example, a bonding apparatus FC3000S (manufactured by Toray Engineering Co., Ltd.) is used.
  • the substrate 5 is arranged on the stage 6 of the bonding apparatus, and the semiconductor chip on which the thermosetting adhesive layer 4 is formed is transported upward using the heat tool 1, and the bump forming surface of the substrate 5 and the semiconductor chip
  • the surface of the thermosetting adhesive layer 4 side is made to face each other.
  • the protective film 2 may be interposed between the heat tool 1 and the semiconductor chip 3 in advance. It is desirable to keep the stage 6 at a constant temperature of 40 ° C. or more and 100 ° C.
  • the heat tool 1 is provided with a mechanism for heating and pressurizing the semiconductor chip 3 and presses the semiconductor chip 3 against the substrate 5 while heating it (FIG. 2D). At this time, the heat passes through the semiconductor chip 3 and is transferred to the thermosetting adhesive layer 4. Accordingly, since the temperature of the thermosetting adhesive layer 4 is increased and the fluidity is increased, the semiconductor chip 3 and the substrate 5 are bonded to each other, and a temporary press-bonded laminate is obtained.
  • the semiconductor chip 3 is pressed against the substrate while being heated using the heat tool 1.
  • the temperature of the heat tool 1 cures the thermosetting adhesive layer 4 and solders.
  • the temperature is controlled so that the solder of the bump 8 is melted.
  • a protective film 2 having a thermal conductivity of 100 W / mK or more is interposed between the heat tool 1 and the semiconductor chip 3.
  • the protective film 2 having high thermal conductivity since the protective film 2 having high thermal conductivity is used, the thermal conduction from the heat tool 1 is fast, and the solder is melted before the thermosetting adhesive layer 4 is cured. Therefore, since the thermosetting adhesive layer 4 remains fluid when the solder is melted, the solder bumps 8 and the electrode pads 9 can be joined well. Even if the adhesive protrudes, the protective film 2 is present between the heat tool 1 and the semiconductor chip 3, so that the heat tool 1 can be bonded without being contaminated by the adhesive. In order to advance hardening of the thermosetting adhesive layer 4, you may heat further after this press-fit process.
  • the protective film 2 may be attached in advance to the heat tool 1 or may be inserted between the semiconductor chip 3 and the heat tool 1 during bonding. As shown in FIG. 3, it is preferable to supply the protective film 2 on a reel-to-reel basis because a new surface of the protective film 2 can be easily supplied between the semiconductor chip 3 and the heat tool 1.
  • the protective film 2 is supplied from the supply reel 12, and is installed so as to pass between the heat tool 1 and the semiconductor chip 3 and be taken up by the take-up reel 13 in the bonding apparatus.
  • the supply reel 12 and the take-up reel 13 are driven in accordance with the operation of the bonding apparatus, and the supply reel 12 and the take-up reel 13 are driven every time bonding is performed, so that the heat tool 1 is driven.
  • the new surface of the protective film 2 is supplied between the semiconductor chip 3 and the semiconductor chip 3.
  • the reel may be driven once every several times of bonding, instead of driving the reel every time of bonding.
  • the reel may be continuously driven at a constant speed so that new surfaces of the protective film 2 are continuously supplied little by little.
  • thermosetting adhesive layer a semiconductor device in which a plurality of semiconductor chips having bumps and through electrodes and a substrate having electrodes corresponding to the bumps are solder-connected via a thermosetting adhesive layer.
  • Manufacturing method (A ′) a step of forming a plurality of semiconductor chips each having a thermosetting adhesive layer by forming a thermosetting adhesive layer in advance on a surface having a bump of each of the plurality of semiconductor chips; (B ′) a step of combining the surface of the thermosetting adhesive layer side of one semiconductor chip on which the thermosetting adhesive layer is formed and the substrate, and temporarily pressing using a heat tool, and at least once
  • the step of joining the surface of the semiconductor chip of the semiconductor chip to the surface of the thermosetting adhesive layer of another semiconductor chip on which the thermosetting adhesive layer is formed is subjected to a temporary pressure bonding using a heat tool.
  • C ′ A protective film having a thermal conductivity of 100 W / mK or more is interposed between the heat tool and the semiconductor chip side surface of the multistage temporary press-bonded laminate. Melting the solder between the semiconductor chip and the semiconductor chip and the substrate and simultaneously curing the thermosetting adhesive layer; In this order.
  • thermosetting adhesive layer is formed in advance on the surface of the semiconductor chip having the bumps.
  • the method similar to the 1st manufacturing method can be used for the method of forming a thermosetting adhesive bond layer.
  • a stack of chips is formed in multiple stages. Therefore, it is possible to form a thermosetting adhesive layer on a semiconductor wafer and use a chip obtained by dicing the thermosetting adhesive layer and the semiconductor wafer at the same time. This is particularly preferable because the protrusion of the layer can be minimized.
  • step (B ′) temporary pressure bonding is performed.
  • the pre-bonding step first, as in the first manufacturing method, the surface of the thermosetting adhesive layer side of one semiconductor chip on which the thermosetting adhesive layer is formed and the substrate are aligned, and the heat tool of the bonding apparatus Temporary pressure bonding is carried out by heating and pressing using Further, the semiconductor chip side surface of the temporarily bonded semiconductor chip and the surface of the other semiconductor chip on which the thermosetting adhesive layer is formed are temporarily bonded together. This step is repeated to form a multistage temporary press-bonded laminate in which a plurality of semiconductor chips are stacked and temporarily press-bonded.
  • the preferable temperature condition of the heat-bonding heat tool is the same as in the first manufacturing method. However, since the heat transfer from the heat tool changes as the number of layers increases, the temperature can be changed for each number of layers.
  • a protective film having a thermal conductivity of 100 W / mK or more can be attached to the surface of the heat tool that contacts the semiconductor chip.
  • the main press-bonding step (C ′) described later can be continuously performed without once removing the heat tool from the semiconductor chip.
  • a protective film having a thermal conductivity of 100 W / mK or more is interposed between the heat tool and the semiconductor chip side surface of the multistage temporary crimped laminate.
  • the solder between the plurality of semiconductor chips and between the semiconductor chips and the substrate is melted, and at the same time, the thermosetting adhesive layer is cured.
  • a multi-stage temporary pressure-bonded laminate is formed by the step (B ′) by combining the surfaces of the other semiconductor chips on which the thermosetting adhesive layer is further formed on the thermosetting adhesive layer side, and then performing the main bonding. It is also possible to perform a process (C ').
  • FIG. 4A shows an example of the step (A ′).
  • a semiconductor chip 3 having a through electrode (TSV) 11 is used.
  • a copper pillar 7 is provided on the TSV 11 on one side of the semiconductor chip 3 having the TSV 11, and a hemispherical solder bump 8 is formed on the copper pillar 7.
  • An electrode pad 9 is formed on the TSV 11 on the opposite surface.
  • thermosetting adhesive layer 4 is formed on the surface having the bumps 8 of the plurality of semiconductor chips 3 according to the step (A ′), and a plurality of semiconductor chips formed with the thermosetting adhesive layer are obtained (FIG. 4B). .
  • thermosetting adhesive layer side of one semiconductor chip on which the thermosetting adhesive layer 4 is formed and the substrate 5 are put together and temporarily pressed in the same manner as in the first manufacturing method. Further, as shown in FIG. 4 (c), the surface of the temporarily bonded semiconductor chip on the semiconductor chip side and the thermosetting adhesive layer side 4 of the other semiconductor chip 3 on which the thermosetting adhesive layer 4 is formed. Align the surfaces of and temporarily crimp. This step is repeated to form a multi-stage temporary press-bonded laminate in which a plurality of semiconductor chips are stacked and temporarily press-bonded (FIG. 4D).
  • a protective film 2 having a thermal conductivity of 100 W / mK or more is interposed between the heat tool 1 and the surface on the semiconductor chip side of the multistage temporary press-bonded laminate.
  • a main press-bonding step of melting the solder between the semiconductor chips and between the semiconductor chip and the substrate and simultaneously curing the thermosetting adhesive layer is performed (FIG. 4E).
  • ⁇ Semiconductor chip structure An aluminum wiring having a thickness of 1 ⁇ m was formed on the oxide film of the silicon wafer, and a silicon nitride insulating film having a thickness of 1 ⁇ m was further formed thereon. An opening is formed in the silicon nitride insulating film so as to be electrically connected to the silicon wafer, a chromium layer is formed in the opening, a copper post having a height of 10 ⁇ m, and a solder (SnAg) having a height of 5 ⁇ m is formed on the chromium layer. A hemispherical bump was formed to produce a semiconductor chip.
  • bumps having four types of bump diameters of 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, and 40 ⁇ m were provided.
  • Four types of bump pitches of 75 ⁇ m, 80 ⁇ m, 85 ⁇ m and 90 ⁇ m were formed for each bump diameter.
  • the number of bumps provided was 174, 162, 150 and 138 for each pitch.
  • Aluminum wiring is patterned on the semiconductor chip so that the connection resistance can be measured for each bump structure after mounting on the substrate.
  • a large number of semiconductor chips are formed on one silicon wafer.
  • Each semiconductor chip has a chip size of 7 mm ⁇ 7 mm and a chip thickness of 100 ⁇ m.
  • Each semiconductor chip is formed with an alignment mark for positioning.
  • a 1 ⁇ m thick aluminum wiring was formed on an oxide film on a silicon substrate (100 ⁇ m thick), and a 1 ⁇ m thick silicon nitride insulating film was further formed thereon.
  • An opening is formed in the silicon nitride insulating film so as to be electrically connected to the silicon substrate, a chromium layer is formed thereon, and an electrode pad made of copper having a thickness of 5 ⁇ m and nickel / gold having a thickness of 1 ⁇ m is formed on the chromium layer.
  • a substrate was produced by forming. The positions and diameters of the electrode pads are all formed so as to correspond to the bumps of the semiconductor chip.
  • the substrate size is 12 mm ⁇ 12 mm, the substrate thickness is 100 ⁇ m, and a 2 mm square lead electrode pad is formed in a region on the substrate where no chip is mounted.
  • a daisy chain is formed, and the junction resistance between the bump and the electrode pad can be measured through the extraction electrode.
  • An alignment mark for positioning is formed on the substrate.
  • Aluminum foil and copper foil were used as a protective film having a thermal conductivity of 100 W / mK or more.
  • a fluororesin film and iron foil were used as a protective film having a thermal conductivity of less than 100 W / mK.
  • the thermal conductivities measured using a thermal diffusivity measurement system are 230 W / mK for aluminum foil, 400 W / mK for copper foil, 0.25 W / mK for fluororesin film, and iron.
  • the foil was 70 W / mK.
  • the film thickness of the aluminum foil is 6 ⁇ m, 12 ⁇ m and 18 ⁇ m
  • the film thickness of the copper foil is 3 ⁇ m, 5 ⁇ m, 18 ⁇ m and 30 ⁇ m
  • the film thickness of the fluororesin film is 12 ⁇ m and 30 ⁇ m
  • the film thickness of the iron foil is 20 ⁇ m.
  • thermosetting adhesive film The following (a) polyimide, (b) epoxy resin and (c) curing accelerator are mixed, and (d) a solvent is added while adjusting the coating thickness to be uniform, and thermosetting adhesion is performed. An agent was obtained.
  • the thermosetting adhesive film 1 in which a thermosetting adhesive layer is formed on a plastic film by applying and drying the thermosetting adhesive on a releasable plastic film (polyethylene terephthalate film). Produced. Mixing was performed so that the ratio of (a) polyimide, (b) epoxy resin, and (c) curing accelerator was 50:20:50 by weight. The thickness of the thermosetting adhesive layer was 25 ⁇ m.
  • thermosetting adhesive was obtained.
  • the thermosetting adhesive film 2 in which a thermosetting adhesive layer is formed on a plastic film by applying and drying the thermosetting adhesive on a releasable plastic film (polyethylene terephthalate film). Produced. Mixing was performed so that the ratio of (a) polyimide, (b) epoxy resin, (c) curing accelerator, and (e) insulating filler was 25: 10: 25: 50 by weight. The thickness of the thermosetting adhesive layer was 25 ⁇ m.
  • the ratio of (c) curing accelerator is calculated on the basis of the amount of (c) the entire curing accelerator.
  • the ratio of (b) epoxy resin does not include (c) epoxy resin in the curing accelerator.
  • (A) Polyimide An organic solvent-soluble polyimide synthesized by the following process was used. First, 24.54 g (0.067 mol) of 2,2-bis (3-amino-4-hydroxyphenyl) hexafluoropropane and 1,3-bis (3-aminopropyl) tetramethyldisiloxane in a dry nitrogen stream As a terminal blocking agent, 4.97 g (0.02 mol) and 2.18 g (0.02 mol) of 3-aminophenol were dissolved in 80 g of NMP. To this was added 31.02 g (0.1 mol) of bis (3,4-dicarboxyphenyl) ether dianhydride together with 20 g of NMP, reacted at 20 ° C.
  • Epoxy resin A solid epoxy compound (manufactured by Mitsubishi Chemical Corporation, epoxy resin 157S70) was used.
  • C Curing accelerator A microcapsule-type curing accelerator (manufactured by Asahi Kasei Chemicals Corporation, NovaCure (registered trademark) HX-3941HP) was used.
  • Insulating inorganic filler SO-E2 (trade name, manufactured by Admatechs Co., Ltd., spherical silica particles, average particle size 0.5 ⁇ m) was used.
  • thermosetting adhesive layer ⁇ Preparation of semiconductor chip with thermosetting adhesive material film>
  • the embedding of the thermosetting adhesive layer into the bumps of the semiconductor chip was performed using a vacuum pressure laminator (MVLP500 / 600, manufactured by Meiki Seisakusho Co., Ltd.). While pressing the surface of the thermosetting adhesive layer side of the thermosetting adhesive film produced as described above against the bump forming surface of the silicon wafer on which a large number of the semiconductor chips are formed, the temperature is 80 ° C. in vacuum. Lamination was performed for 20 seconds under a pressure of 0.7 MPa. Excess thermosetting adhesive film around the silicon wafer was cut with a cutter. The silicon wafer used here is 8 inches in size.
  • thermosetting adhesive layer is stretched on a tape frame using a wafer mounter device (FM-1146-DF, manufactured by Technovision Co., Ltd.).
  • a dicing tape (D-650, manufactured by Lintec Corporation) was attached.
  • dicing was performed under the following cutting conditions.
  • Blade NBC-ZH 127F-SE 27HCCC Spindle speed: 25000rpm Cutting speed: 50 mm / s Cutting depth: Cut to 20 ⁇ m depth of dicing tape Cut: One-pass full cut Cut mode: Down cut Cutting water amount: 3.7 L / min Cutting water and cooling water: Temperature 23 ° C., electric conductivity 0.5 M ⁇ ⁇ cm (extra Carbon dioxide gas is injected into pure water).
  • thermosetting adhesive layer For semiconductor chips made into individual chips by dicing, adhesion of cutting powder to the surface of the thermosetting adhesive layer, cracking or chipping of the surface of the thermosetting adhesive layer, and of the thermosetting adhesive film from the wafer No peeling was seen.
  • thermosetting adhesive material film produced as described above is housed in a chip tray with the surface on which the thermosetting adhesive layer is formed facing upward, and is bonded to a bonding apparatus (Toray Engineering Co., Ltd.). , FC3000S).
  • a bonding apparatus Toray Engineering Co., Ltd.
  • FC3000S FC3000S
  • the substrate was placed on a stage maintained at 60 ° C. in a bonding apparatus.
  • the semiconductor chip stored in the chip tray was picked up by a pick-up tool, and the chip surface was inverted.
  • the surface of the semiconductor chip on the semiconductor chip side was vacuum-sucked by the transfer device, and the semiconductor chip was transferred to above the substrate placed on the stage.
  • the alignment recognition camera entered between the semiconductor chip and the substrate so that the bumps of the semiconductor chip and the electrode pads on the substrate overlapped at predetermined positions, and the respective alignment marks were detected.
  • the semiconductor chip is pressed at a pressure of 15 N and a temperature of 100 ° C. for 10 seconds.
  • temporary pressing was performed to prepare a temporary pressing laminate.
  • the surface temperature of the attachment of the heat tool was calibrated in advance using a temperature recorder (manufactured by Keyence Corporation, NR100) and a K thermocouple.
  • a protective film having a thermal conductivity of 100 W / mK or more is interposed between the heat tool and the surface on the side of the semiconductor chip in the temporary pressure-bonded laminate, and main bonding is performed to solder between the semiconductor chip and the substrate. While being melted, the thermosetting adhesive layer was cured.
  • the main press-bonding was first held at a pressure of 40 N and a temperature of 100 ° C. for 10 seconds, and then processed at a pressure of 40 N and a temperature of 250 ° C. for 20 seconds.
  • ⁇ Mountability evaluation> The mountability was evaluated by measuring the conduction resistance (conduction evaluation) of the daisy chain formed after mounting and observing the cross section of the bump connection portion (cross section observation evaluation).
  • the semiconductor chip and the substrate used in the evaluation of each example are designed to be electrically connected to each bump pitch via connecting portions of 138, 150, 162, and 174, respectively. Yes. If there is a portion where even one bump and electrode pad are not in contact with each other, connection failure occurs.
  • a measurement terminal of DIGITAL VOLMETER HWLETT PACKARD, 3455A was connected, and the resistance value was measured.
  • the resistance value includes not only the connection portion between the bump and the electrode pad but also the resistance inside the semiconductor chip and the value of the lead electrode. It was determined whether or not all measured resistance values were less than 100 k ⁇ for each bump pitch daisy chain. Of the three samples that were mounted, all three samples had a measured daisy chain resistance value of less than 100 k ⁇ . A, one sample or two samples had a daisy chain resistance value of 100 k ⁇ or more. In the case of B, the case where there was a sample in which the resistance value of the daisy chain was 100 k ⁇ or more was determined as C.
  • Examples 1 to 3 The mountability was evaluated by the above method using aluminum foils having a thickness of 6 ⁇ m, 12 ⁇ m and 20 ⁇ m as the protective film, and using the thermosetting adhesive film 2 as the thermosetting adhesive film. In Examples 1 to 3, there was no sticking of the thermosetting adhesive film protruding to the pickup tool, and the continuity evaluation and the cross-sectional observation evaluation were both A. The results are shown in Table 1.
  • Example 4 to Example 6 Evaluations were made in the same manner as in Examples 1 to 3 except that the thermosetting adhesive film 1 was used as the thermosetting adhesive film.
  • the continuity evaluation and the cross-section observation evaluation were both A. The results are shown in Table 1.
  • Example 7 Evaluation was performed in the same manner as in Example 1 except that copper foils having thicknesses of 3 ⁇ m, 5 ⁇ m, 18 ⁇ m, and 30 ⁇ m were used as protective films, respectively.
  • a copper foil having a film thickness of 30 ⁇ m was used (Example 10)
  • the results are shown in Table 1.
  • thermosetting adhesive film 1 was used as the thermosetting adhesive film.
  • the continuity evaluation and the cross-section observation evaluation were both A. The results are shown in Table 1.
  • Example 15 As a semiconductor chip, a silicon substrate on which copper TSV with a diameter of 50 ⁇ m and a pitch of 200 ⁇ m was formed was used. A large number of semiconductor chips are formed on one silicon wafer, and the chip size of each semiconductor chip is 7 mm ⁇ 7 mm. 26 ⁇ 27 TSVs are formed on a 7 mm square chip. A 1 ⁇ m thick copper wiring was formed on the TSV on one side of the semiconductor chip via a 1 ⁇ m thick polyimide passivation film, and a 1 ⁇ m thick polyimide insulating film was further formed thereon.
  • a chromium layer is formed in the polyimide insulating film in an opening provided to be electrically connected to the TSV, and the opening is made of a copper post having a height of 10 ⁇ m and a solder (SnAg) hemisphere having a height of 5 ⁇ m.
  • Bumps were formed to produce a semiconductor chip.
  • the bump diameter is 30 ⁇ m.
  • the copper wiring is patterned so that the connection resistance can be measured for each bump after mounting on the substrate.
  • the chip thickness is 100 ⁇ m.
  • a chromium layer is formed in an opening provided on the surface opposite to the bump of the semiconductor chip so as to be electrically connected to the TSV in a polyimide insulating film having a thickness of 1 ⁇ m.
  • An aluminum wiring having a thickness of 1 ⁇ m was formed on an oxide film of a silicon substrate (film thickness 100 ⁇ m), and a silicon nitride insulating film having a thickness of 1 ⁇ m was further formed thereon.
  • a chromium layer is formed in an opening provided in the silicon nitride insulating film so as to be electrically connected to the silicon substrate, and an electrode pad made of copper having a thickness of 5 ⁇ m and nickel / gold having a thickness of 1 ⁇ m is formed in the opening.
  • a substrate was prepared. The positions and diameters of the electrode pads are all formed so as to correspond to the bumps of the semiconductor chip.
  • the substrate size is 12 mm ⁇ 12 mm, the substrate thickness is 100 ⁇ m, and a 2 mm square lead electrode pad is formed in a region on the substrate where no chip is mounted.
  • a daisy chain is formed, and the junction resistance between the bump and the electrode pad can be measured through the extraction electrode.
  • thermosetting adhesive material film> Except for using the silicon wafer on which the above TSV was formed instead of the silicon wafer used in the above-mentioned ⁇ Preparation of semiconductor chip with thermosetting adhesive material film> step Production of Semiconductor Chip> A semiconductor chip with a thermosetting adhesive layer was obtained in the same manner as in the step.
  • a temporary press-bonded laminate in which one semiconductor chip was stacked on the substrate was formed in the same manner as in the pre-bonding step in the ⁇ bonding> step. Further, the same process was repeated three times to form a four-stage temporary press-bonded laminated body in which four stages of semiconductor chips were laminated on the substrate. Next, an aluminum foil protective film having a thickness of 12 ⁇ m is interposed between the heat tool and the surface on the semiconductor chip side of the four-stage temporary pressure-bonded laminate, and the same method as the main pressure-bonding step in the ⁇ bonding> step. The main press bonding was performed.
  • Example 1 The mountability evaluation was performed in the same manner as in Example 1.
  • the semiconductor device obtained in Example 1 has one stage of semiconductor chip, and in this example, there are four stages of semiconductor chips. The device was cut off. The results are shown in Table 1.
  • Comparative Examples 1 and 2 Evaluation was performed in the same manner as in Example 1 except that a fluororesin film having a thickness of 12 ⁇ m and 30 ⁇ m was used as the protective film, respectively. Although there was no sticking of the thermosetting adhesive layer protruding to the pickup tool, the conduction evaluation and the cross-sectional observation evaluation were both C. The results are shown in Table 1.
  • Comparative Examples 3 and 4 Evaluation was performed in the same manner as in Comparative Examples 1 and 2, respectively, except that the thermosetting adhesive film 1 was used as the thermosetting adhesive film.
  • a protective film having a thickness of 12 ⁇ m was used (Comparative Example 3)
  • only one sample had a daisy chain resistance value of less than 100 k ⁇ in B, and was B.
  • the cross-sectional observation evaluation was C. The results are shown in Table 1.
  • Comparative Example 5 Evaluation was performed in the same manner as in Example 1 except that an iron foil having a thickness of 20 ⁇ m was used as the protective film. Although there was no sticking of the thermosetting adhesive layer protruding to the pickup tool, the conduction evaluation and the cross-sectional observation evaluation were both C. The results are shown in Table 1.
  • Comparative Example 7 Evaluation was performed in the same manner as in Example 15 except that a fluororesin film having a thickness of 30 ⁇ m was used as the protective film. The results are shown in Table 1.
  • bumps and electrode pads can be easily soldered via an adhesive film, and a semiconductor device can be manufactured with a high yield.
  • the present invention relates to a semiconductor device in which a semiconductor chip such as an IC or LSI is solder-connected to a circuit board such as a flexible substrate, a glass epoxy substrate, a glass substrate, a ceramic substrate, a silicon interposer, or a silicon substrate, or the semiconductor chips are soldered together. Suitable for manufacturing semiconductor devices such as connected semiconductor chip stacks.

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Abstract

　バンプを有する半導体チップを、該バンプに対応した電極を有する基板に、熱硬化性接着剤層を介してはんだ接続する半導体装置の製造方法であって：（Ａ）半導体チップのバンプを有する面に、あらかじめ熱硬化性接着剤層を形成する工程、（Ｂ）熱硬化性接着剤層が形成された半導体チップの熱硬化性接着剤層側の面と基板とを合わせて、ヒートツールを用いて仮圧着し、仮圧着積層体を得る工程、（Ｃ）該ヒートツールと該仮圧着積層体の半導体チップ側の面との間に、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを介在させ、ヒートツールを用いて、半導体チップと基板との間のはんだを溶融させると同時に熱硬化性接着剤層を硬化させる工程、をこの順に有する半導体装置の製造方法。樹脂がはんだバンプと電極パッドとの間に挟まることなく、良好な接続が得られる半導体装置の製造方法を提供する。

Description

半導体装置の製造方法および半導体装置の製造装置
　本発明は、パソコンや携帯端末に使用される半導体装置の製造方法および製造装置に関する。より詳しくは、本発明は、ＩＣ、ＬＳＩ等の半導体チップを、フレキシブル基板、ガラスエポキシ基板、ガラス基板、セラミックス基板、シリコンインターポーザー、シリコン基板などの回路基板にはんだ接続した半導体装置、あるいは、半導体チップ同士をはんだ接続した半導体チップ積層体などの半導体装置の製造方法および製造装置に関する。
　近年、半導体装置の小型化と高密度化に伴い、半導体チップを回路基板に実装する方法としてフリップチップ実装、さらにはチップを貫通する貫通電極によって半導体チップを３次元的に積層する３次元積層実装が急速に広まってきている。半導体チップと基板の接合部分の接続信頼性を確保するための方法としては、半導体チップ上に形成されたバンプと基板の電極パッドを接合した後に、半導体チップと回路基板との隙間に液状封止接着剤を注入し、硬化させることが一般的な方法として採られていた。
　最近では、バンプ付き半導体ウェハに樹脂フィルムを仮接着した後、ダイシングにより半導体ウェハを個別半導体チップとし、次に、半導体チップを回路基板にフリップチップ接続し、電気的接合と樹脂封止を同時に行う方法およびそれに使用する接着剤フィルムが提案されている（例えば、特許文献１～３参照）。これらの方法によれば、接着剤フィルムと半導体チップの接着面積をほぼ同じにすることができ、液状封止接着剤を用いた場合に比べ、半導体チップに対する接着剤のはみ出しが非常に少ない。このような接着フィルムを介して薄い半導体チップを基板上に接合する場合、半導体チップとボンディング装置のヒートツールの間にテフロン（登録商標）やシリコン等の樹脂フィルムを挟み、はみ出した接着剤がヒートツールに付着しないよう対策を施すことが考えられている。また、それらの保護フィルムとして、半導体チップの反りを抑制するため弾性率の大きい保護フィルムを用いることが考えられている（特許文献４～５参照）。さらには、熱圧着の際に、接着剤フィルムの大きさを規定することにより、接着剤のはみ出しと、半導体チップのバンプと基板上の電極パッドとの間に接着剤フィルムに含まれる絶縁性無機フィラーや樹脂が噛み込むことを防ぐ方法も考えられている（特許文献６参照）。
特開２００１－２３７２６８号公報（請求項１、３～４頁） 特開２００４－３１５６８８号公報（特許請求の範囲） 特開２００４－３１９８２３号公報（特許請求の範囲） 特開２００６－２２９１２４号公報（特許請求の範囲） 特開２００９－１１６３２６号公報（特許請求の範囲） 特開２０１０－２２６０９８号公報（特許請求の範囲）
　しかしながら、それらの保護フィルムを使い、接着剤フィルムを介してはんだ接続を行った場合、バンプと電極パッドの間に接着剤フィルムの樹脂が挟まって導通不良が発生する等の課題があった。
　本発明では、接着剤フィルムの樹脂がバンプと電極パッドとの間に挟まることなく、またヒートツールを汚染することなく、良好なはんだ接続が得られる半導体装置の製造方法および製造装置を提供することを目的とする。
　本発明の第１の半導体装置の製造方法は、バンプを有する半導体チップを、該バンプに対応した電極を有する基板に、熱硬化性接着剤層を介してはんだ接続する半導体装置の製造方法であって：
（Ａ）半導体チップのバンプを有する面に、あらかじめ熱硬化性接着剤層を形成する工程、
（Ｂ）熱硬化性接着剤層が形成された半導体チップの熱硬化性接着剤層側の面と基板とを合わせて、ヒートツールを用いて仮圧着し、仮圧着積層体を得る工程、
（Ｃ）該ヒートツールと該仮圧着積層体の半導体チップ側の面との間に、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを介在させ、ヒートツールを用いて、半導体チップと基板との間のはんだを溶融させると同時に熱硬化性接着剤層を硬化させる工程、
をこの順に有する半導体装置の製造方法である。
　本発明の第２の半導体装置の製造方法は、バンプおよび貫通電極を有する複数の半導体チップならびに該バンプに対応した電極を有する基板を、熱硬化性接着剤層を介してはんだ接続する半導体装置の製造方法であって：
（Ａ’）複数の半導体チップそれぞれのバンプを有する面に、あらかじめ熱硬化性接着剤層を形成して、熱硬化性接着剤層が形成された半導体チップを複数得る工程、
（Ｂ’）熱硬化性接着剤層が形成された１つの半導体チップの熱硬化性接着剤層側の面と基板とを合わせて、ヒートツールを用いて仮圧着する工程、および、１回以上の該半導体チップの半導体チップ側の面と熱硬化性接着剤層が形成された他の半導体チップの熱硬化性接着剤層側の面を合わせて、ヒートツールを用いて仮圧着する工程を経て多段仮圧着積層体を得る工程、
（Ｃ’）該ヒートツールと該多段仮圧着積層体における半導体チップ側の面との間に、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを介在させ、ヒートツールを用いて、複数の半導体チップの間および半導体チップと基板との間のはんだを溶融させると同時に熱硬化性接着剤層を硬化させる工程、
をこの順に有する請求項１に記載の半導体装置の製造方法である。
　本発明の半導体装置の製造装置は、基板と半導体チップとをボンディングして半導体装置を製造するための装置であって、
基板を設置するためのステージ、および、半導体チップを加熱・加圧する機構を有するヒートツールを備えたボンディング装置と、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを供給する供給リールと、該保護フィルムを巻き取る巻き取りリールとを備え、
供給リールから供給された保護フィルムが、ヒートツールとステージの間を通過して、巻き取りリールに巻き取られるように配置された半導体装置の製造装置である。
　本発明の製造方法によれば、熱硬化性接着剤層を介してバンプと電極パッドとを容易にはんだ接続でき、高い歩留りで半導体装置を製造することが可能となる。
本発明による保護フィルムを用いた半導体装置の実装工程を示す断面図である。 本発明による半導体装置の製造方法の説明図である。 本発明による半導体装置の製造方法の説明図である。 本発明による３次元積層実装を行う半導体装置の製造方法の説明図である。
　本発明でいう半導体装置とは、半導体素子の特性を利用することで機能し得る装置全般を指す。半導体チップを基板に接続した電気光学装置、半導体回路基板およびこれらを含む電子部品は、全て半導体装置に含まれる。また、貫通電極ＴＳＶ（スルーシリコンビア）を有するシリコンチップの両面に電極パッドやバンプ等の接続端子を形成した半導体チップを用い、このようなシリコンチップの複数を３次元積層したものも半導体装置に含まれる。
　半導体チップとしては、例えば、集積回路、大規模集積回路、トランジスタ、サイリスタ、ダイオード等が挙げられ、特に限定されるものではない。半導体チップの材料としては、シリコン（Ｓｉ）、ゲルマニウム（Ｇｅ）といった半導体や、ガリウム砒素（ＧａＡｓ）、ガリウム燐（ＧａＰ）、インジウム燐（ＩｎＰ）、炭化珪素（ＳｉＣ）等の化合物半導体を用いることができる。
　また、半導体チップには、接続信頼性等の観点からバンプが形成されている。バンプの材質に特に制限は無く、アルミニウム、銅、チタン、タングステン、クロム、ニッケル、金、はんだ、それらを用いた合金など、半導体装置において一般的に用い得る金属を使用することができる。半導体チップのバンプと基板の電極パッドをはんだ接続する必要性から、バンプおよび電極パッドのいずれかの材質がはんだであることが好ましい。本発明においては、ヒートツールによって、半導体チップ側から加熱されるため、バンプをはんだバンプとする方が、はんだに熱が伝わりやすいため好ましい。
　はんだの材質としては、特に限定されないが、人体や環境への影響の観点から、ＳｎＡｇＣｕ系、ＳｎＣｕ系、ＳｎＡｇ系、ＳｎＡｇＣｕＢｉ系、ＳｎＺｎＢｉ系、ＳｎＡｇＩｎＢｉ系などの鉛フリーはんだを用いることが好ましい。さらには、狭ピッチのバンプに対応するため、はんだバンプは金属のピラー、特に銅ピラー上に形成されていることが好ましい。はんだと金属ピラーとの間に金属の拡散を抑制するためのバリアメタル層を設けることもできる。また、樹脂やフィラーがバンプと電極パッドの間に挟まり難いという観点から、はんだバンプの形状は半球状であることが好ましい。
　半導体チップにあるバンプの高さはすべて均等に揃っていることが好ましい。具体的には、バンプ高さのバラツキは０．５μｍ以下であることが好ましい。バラツキが０．５μｍ以下であれば、バンプの圧着の際に接続不良なく半導体チップを搭載することができる。より好ましくはバンプ高さのバラツキが０．２μｍ以下である。バンプ高さのバラツキを小さくするため、バンプに研削加工を施すことも可能である。
　基板としては、シリコン基板等の半導体基板、セラミックス基板、化合物半導体基板、有機系回路基板、無機系回路基板、およびこれらの基板に回路の構成材料が配置されたものが挙げられる。シリコン基板としては、前記の半導体チップ、特にＴＳＶ構造を有する半導体チップも用いることができる。この場合、複数の半導体チップ同士を接合することになるが、本発明の方法においては、用いる部材の種類にかかわらず、保護フィルムを介してヒートシールに接しているものを「半導体チップ」と呼び、後述のステージに設置したものを「基板」と呼ぶ。有機系回路基板の例としては、ガラス布・エポキシ銅張積層板などのガラス基材銅張積層板；ガラス不織布・エポキシ銅張積層板などのコンポジット銅張積層板；ポリエーテルイミド樹脂基板、ポリエーテルケトン樹脂基板、ポリサルフォン系樹脂基板などの耐熱・熱可塑性基板；ポリエステル銅張フィルム基板；ポリイミド銅張フィルム基板などのフレキシブル基板が挙げられる。無機系回路基板としては、アルミナ基板、窒化アルミニウム基板、炭化ケイ素基板などのセラミック基板；アルミニウムベース基板、鉄ベース基板などの金属系基板が例として挙げられる。なかでも、本発明は、熱伝導性が高く薄膜化した多層基板に用いられるシリコン基板、特にＴＳＶ構造を有する半導体チップ、を使用する場合に有効に作用する。
　基板上の回路の構成材料の例は、銀、金、銅、アルミニウムなどの金属を含有する導体；無機系酸化物などを含有する抵抗体；ガラス系材料および／または樹脂などを含有する低誘電体；樹脂や高誘電率無機粒子などを含有する高誘電体；ガラス系材料などを含有する絶縁体などが挙げられる。
　基板には、半導体チップのバンプの位置に対応した電極パッドを有する。電極パッドは、平坦な形状でもよいし、いわゆるピラー形状（柱状）の突起であってもよい。また、電極パッドの形状は、円形でもよいし、四角形、八角形などの多角形でもよい。電極パッドの材質に特に制限は無く、アルミニウム、銅、チタン、タングステン、クロム、ニッケル、金、はんだ、それらを用いた合金など、半導体装置において一般的に用い得る金属を使用することができ、複数の金属を積層することもできる。電極パッドもバンプと同様、高さのバラツキは０．５μｍ以下であることが好ましく、研削加工を施すことも可能である。
　本発明の第１の半導体装置の製造方法は、バンプを有する半導体チップを、該バンプに対応した電極を有する基板に、熱硬化性接着剤層を介してはんだ接続する半導体装置の製造方法であって：
（Ａ）半導体チップのバンプを有する面に、あらかじめ熱硬化性接着剤層を形成する工程、
（Ｂ）熱硬化性接着剤層が形成された半導体チップの熱硬化性接着剤層側の面と基板とを合わせて、ヒートツールを用いて仮圧着し、仮圧着積層体を得る工程、
（Ｃ）該ヒートツールと該仮圧着積層体の半導体チップ側の面との間に、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを介在させ、ヒートツールを用いて、半導体チップと基板との間のはんだを溶融させると同時に熱硬化性接着剤層を硬化させる工程、
をこの順に有する半導体装置の製造方法である。
　工程（Ａ）では、半導体チップのバンプを有する面にあらかじめ熱硬化性接着剤層が形成される。特に、離型性のプラスチックフィルム上に熱硬化性接着剤層を形成した熱硬化性接着剤フィルムの熱硬化性接着剤層側の面を、バンプ付き半導体チップのバンプ側の面に重ねて、加圧しながら加熱ラミネートまたは真空加熱ラミネートする方法は、操作が簡便であり、かつ、半導体チップに対する接着剤のはみ出しが少ないので好ましい。ラミネート時の温度は、熱硬化性接着剤層の凹凸への追従性の点から６０℃以上が好ましい。また、ラミネート時の熱硬化性接着剤の硬化を防ぐために、温度は１００℃以下とすることが好ましい。この温度範囲において熱硬化性接着剤層の動的粘度は、５０～５０００Ｐａ・ｓであることが好ましい。熱硬化性接着剤層の動的粘度が５０Ｐａ・ｓ以上であると取り扱いが容易であり、５０００Ｐａ・ｓ以下であるとバンプが熱硬化性接着剤層中に埋まりやすく、低圧力でのラミネートが可能となる。この場合、ラミネート工程後、ボンディング工程までの間に、熱硬化性接着剤フィルムの離型性プラスチックフィルムは剥離され、熱硬化性接着剤層がむき出しにされる。
　熱硬化性接着剤層の動的粘度は、動的粘弾性法により例えばレオメータ（セイコーインスツルメンツ製、ＤＭＳ６１００）を用いて測定することができる。
　また、他の方法として、半導体チップのバンプを有する面に、液状の熱硬化性接着剤を塗布することにより、熱硬化性接着剤層を形成することもできる。塗布方法は特に限定されないが、スピンナー、スクリーン印刷、ブレードコーター、ダイコーター等を用いることができる。この場合、ボンディング工程までの半導体チップの取り扱い性の観点から、熱硬化性接着剤層を乾燥させておくことが好ましい。
　また、個別の半導体チップに対して、それぞれ上記の工程（Ａ）を実施する代わりに、半導体チップが多数形成された半導体ウェハのバンプが形成された面に熱硬化性接着剤層を形成した後、熱硬化性接着剤層ごと半導体ウェハをダイシングすることで、熱硬化性接着剤層付き半導体チップを作ることができる。この方法は、熱硬化性接着剤層と半導体チップを同じ形に形成することができ、ボンディング中の熱硬化性接着剤層のはみ出しを極小にすることができるため、好ましい。
　熱硬化性接着剤層は、絶縁性樹脂のみからなるものであってもよいし、絶縁性樹脂に他の成分が含まれているものであってもよい。また、複数の種類の絶縁性樹脂を混合してもよい。絶縁性樹脂としては、ポリイミド樹脂、エポキシ樹脂、アクリル樹脂、フェノキシ樹脂、ポリエーテルスルホン樹脂などを用いることができるが、これらに限定されない。硬化剤、硬化促進剤などをさらに含有していてもよい。硬化剤および硬化促進剤としては公知のものを用いることができる。
　熱硬化性接着剤層は、絶縁信頼性や温度サイクルに対する信頼性の観点から絶縁性無機フィラーを含むものが好ましい。絶縁性無機フィラーとしては、シリカ、窒化ケイ素、アルミナ、窒化アルミ、酸化チタン、窒化チタン、チタン酸バリウムなどを用いることができる。また絶縁性無機フィラーは樹脂と同様にバンプと電極パッドとの間に挟まることがあるため、本発明の半導体装置の製造方法を用いることにより、好ましく製造することができる。
　また、必要に応じ架橋剤、界面活性剤、分散剤などが熱硬化性接着剤層に含まれていてもよい。熱硬化性接着剤層は感光性を有していてもよい。感光性を有する場合は、被膜の形成後またはシートの貼り付け後に露光、現像によりパターン加工を行い、バンプ形成部等の必要な部分を開口させることができる。
　本発明で用いられる熱硬化性接着剤としては、例えば特開２００４－３１９８２３号公報、特開２００８－９４８７０号公報、特許３９９５０２２号公報、特開２００９－２６２２２７号公報などに開示されている樹脂組成物を用いることができる。
　熱硬化性接着剤層の厚さは、バンプの平均高さ以上であることが好ましい。より好ましくはバンプの平均高さ以上かつバンプの平均高さと基板上の電極パッド平均高さを足し合わせた厚さの１．５倍以下である。さらにより好ましくは、バンプの平均高さ以上かつバンプの平均高さと基板上の電極パッド平均高さを足し合わせた厚さ以下である。なお、バンプの高さや電極パッドの高さは、それぞれ半導体チップや基板の表面の形状を測定し、その一番低い高さを基準（０μｍ）として高さのピーク値を測定することにより得ることができる。バンプの平均高さおよび電極パッド平均高さは、それぞれ半導体チップの全てのバンプや基板上の全ての電極パッドの高さの平均値であり、例えばコンフォーカル顕微鏡（レーザーテック（株）製、Ｈ１２００）で測定することができる。熱硬化性接着剤層の厚さがバンプの平均高さ以上であると、ボンディング後の熱硬化性接着剤層と基板との間にボイドが発生しにくく、接着力が低下したりする場合や信頼性に影響する場合が少なくなる。また、熱硬化性接着剤層の厚さがバンプの平均高さと基板上の電極パッド平均高さを足し合わせた厚さの１．５倍以下であれば、経済性に優れるだけでなく、熱硬化性接着剤層のはみ出し量が少なくなるため実装面積が少なくなり、またはみ出した熱硬化性接着剤層が半導体チップ上部にまで回り込み、ボンディング装置のヒートツールを汚染し、ヒートツールと半導体チップが接着してしまうことが少なくなる。
　工程（Ｂ）では、仮圧着を行う。ここで、仮圧着工程とは、ヒートツールを用いて、半導体チップと基板とが固定されるが、熱硬化性接着剤の硬化は進行しないように、熱および圧力を加える工程である。仮圧着工程では、熱硬化性接着剤層が形成された半導体チップの熱硬化性接着剤層側の面と基板とを合わせて、ボンディング装置のヒートツールを用いて仮圧着し、仮圧着積層体を形成する。
　その際、半導体チップに形成されたアライメントマークおよび基板上のアライメントマークに基づいて、半導体チップのバンプと基板の電極パッドの接続位置が一致するように、位置を補正した後、仮圧着を行う。位置精度の観点から、熱硬化性接着剤層は、アライメントマークが認識できるよう透明であることが好ましい。
　仮圧着時のヒートツールの温度は、はんだ融点以下の温度で熱硬化性接着剤層の粘度を下げて粘着性を上げ、所定の位置に半導体チップが固定されるよう、また熱硬化性接着剤の硬化が進まないよう、６０～１２０℃の温度範囲が好ましい。また仮圧着時の圧力は０．０１～０．５ＭＰａの範囲が好ましい。０．０１ＭＰａ以上であれば十分に仮圧着の目的を達成することができ、０．５ＭＰａ以下であれば、バンプが大きく変形することなく仮圧着できる。仮圧着は、常圧下で行っても良いし、気泡の噛み込みなどを防ぐため真空中で実施しても良い。なお、ここでの温度とは、熱硬化性接着剤層中の温度であり、例えば、温度レコーダ（（株）キーエンス製、ＮＲ１００）に熱電対を接続して求めることができる。
　仮圧着の際、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムをヒートツールの半導体チップと接する面に貼り付けておくこともできる。この場合、一旦半導体チップからヒートツールを離すことなく、連続で後述の本圧着工程を行うことができる。また、ステージを汚さないよう基板を設置するステージ上に保護フィルムを貼り付けておくこともできる。
　工程（Ｃ）では、本圧着を行う。ここで、本圧着工程とは、ヒートツールを用いて、半導体チップと基板との間のはんだを溶融させ、かつ、熱硬化性接着剤層を硬化させるように、熱および圧力を加える工程である。本圧着工程では、ヒートツールと仮圧着積層体の半導体チップ側の面との間に、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを介在させ、ヒートツールを用いて、半導体チップと基板との間のはんだを溶融させると同時に熱硬化性接着剤層を硬化させる。
　本圧着時のヒートツールの温度は、はんだが溶融するよう、２２０～３００℃の温度範囲が好ましい。この加熱処理は、段階的に昇温して行っても、連続的に昇温して行っても良い。加熱時間は、１秒から数分が好ましい。一例としては、熱硬化性接着剤層を軟化させるため１００℃で１０秒間保持した後、はんだ溶融のため２５０℃で２０秒間熱処理する。そのときの温度の立ち上がり時間は、接着剤の流動性とはんだ溶融のタイミングの観点から１秒以下であることが好ましい。立ち上がり時間とは、ヒートツールの表面温度が現在の温度から設定温度へ向けて９０％以上変化する時間のことである。また本圧着時の圧力は、はんだ押し込み量の観点から０．０１～１ＭＰａの範囲が好ましい。この時の圧力も時間的に変化させることができる。はんだの溶融時に、ヒートツールの位置を固定する高さ制御を行うこともできる。該加熱処理は、常圧下で行ってもよいし、真空中で実施してもよい。また、空気による酸化劣化を防ぐため、窒素雰囲気下で実施してもよい。
　本発明に用いられる保護フィルムは、熱伝導率１００Ｗ／ｍＫ以上のフィルムであり、２００Ｗ／ｍＫ以上であることが好ましい。保護フィルムを用いることで、ヒートツールが熱硬化性接着剤によって汚染されることを防ぐことができる。ヒートツールが汚染されると、ヒートツールの平坦性が損なわれ、ボンディング時の半導体チップの熱圧着状態が不均一となり、ボンディング不良が発生する。保護フィルムを用いることで、そのような問題を防ぐことができる。また、保護フィルムの熱伝導率が１００Ｗ／ｍＫ以上あれば、ヒートツールから短時間に半導体チップのはんだバンプもしくは基板のはんだ電極パッドに熱を伝達することが可能になる。その結果、熱硬化性接着剤層が硬化する前の流動性がある状態で、はんだを溶融することが可能となる。熱硬化性接着剤層に含まれる樹脂を挟み込むことなく、バンプと電極パッドを接合させることができる。また熱伝導率の上限については特に制限はないが、保護フィルムの入手のしやすさの点から５００Ｗ／ｍＫ以下であることが好ましく、４００Ｗ／ｍＫ以下であることがより好ましい。
　保護フィルムの熱伝導率が１００Ｗ／ｍＫ未満である場合は、ヒートツールからの熱がはんだバンプ、もしくは、はんだ電極パッドに伝達されるのに時間がかかり、はんだが溶融する前に、熱硬化性接着剤層の硬化が進行してしまう。その場合、バンプと電極パッドを接合させる際に、流動性を失った熱硬化性接着剤が、バンプと電極パッドの間に挟み込まれてしまう。
　保護フィルムの厚さは、５μｍ以上２０μｍ以下であることが好ましい。厚さが５μｍ以上あれば、保護フィルムの強度が高くなるので好ましい。厚さが２０μｍ以下であれば、はんだ溶融時の熱の伝達時間が短くなり、熱硬化性接着剤層を硬化させることなく熱を伝達しやすい。
　保護フィルムの材質としては、各種の熱伝導率１００Ｗ／ｍＫ以上の材料を使用できる。中でも熱伝導率が高く加工性に優れた銅箔やアルミニウム箔が望ましい。銅箔は、銅以外の不純物が含まれていてもよいが、不純物の量が銅箔の全重量中１０重量％以下であることが好ましく、１重量％以下であることがより好ましい。またアルミニウム箔もアルミニウム以外の不純物が含まれていてもよいが、不純物の量がアルミニウム箔の全重量中１０重量％以下であることが好ましく、１重量％以下であることがより好ましい。また、保護フィルムとしては、２種類以上の金属箔や貼り付き防止のフィルムが積層された構造でも良い。さらには、フッ素コート（離型剤）を塗布したものも使用できる。これらの場合、熱伝導率は、積層構造全体としての値である。保護フィルムの熱伝導率は、例えば、熱拡散率測定システム（株式会社アイフェイズ製、１μ）を用いて測定することができる。
　上記の本圧着工程の後、追加キュアを行ってもよい。追加キュアの条件は、用いる熱硬化性接着剤の特性に応じて任意に設定することができる。
　以下に、本発明の半導体装置の製造方法の各工程について例を挙げて説明するが、本発明は下記の例に限定されない。
　まず、図２（ａ）に工程（Ａ）の例を示す。図２（ａ）に示す例では、半導体チップ３の片方の面に、銅ピラー７が設けられ、銅ピラー７の上に半球状のはんだバンプ８が形成されている。半導体チップ３のはんだバンプ８が形成されている面に、プラスチックフィルム１０上に熱硬化性接着剤層４が形成された熱硬化性接着剤フィルムをラミネートする。熱硬化性接着剤フィルムの、熱硬化性接着剤層４側の面を半導体チップ３のはんだバンプ８が形成されている面と重ね合わせて、加熱しながら圧力をかけることにより、ラミネートする。この際、熱硬化性接着剤層４と半導体チップ３の間にボイドがないようラミネートされることが好ましいため、真空中でラミネートすることが好ましい。真空中でラミネートできる装置としては、例えば、真空加圧ラミネーター（（株）名機製作所製、ＭＶＬＰ５００／６００）がある。このとき、加熱する方法は、半導体チップ側からでもプラスチックフィルム側からでも両側からでもかまわない。ラミネート時の圧力は、熱硬化性接着剤層４がはんだバンプ８の凹凸に追従でき、かつ、はんだバンプ８が潰れないよう０．１ＭＰａ以上１ＭＰａ以下で行うことが好ましい。ラミネート後に、熱硬化性接着剤層４からプラスチックフィルム１０を剥がすことにより、熱硬化性接着剤層４が形成された半導体チップ（図２（ｂ））を得ることができる。
　次に、図２（ｃ）に工程（Ｂ）の仮圧着工程の例を示す。仮圧着には、フリップチップボンダー、例えば、ボンディング装置ＦＣ３０００Ｓ（東レエンジニアリング（株）製）、を用いる。ボンディング装置のステージ６上に基板５を配置し、ヒートツール１を用いて、熱硬化性接着剤層４を形成した半導体チップを基板上方向に搬送し、基板５のバンプ形成面と、半導体チップの熱硬化性接着剤層４側の面とが向かい合うようにする。この際、予めヒートツール１と半導体チップ３の間に保護フィルム２を介在させていても良い。ステージ６は、周囲の温度環境条件に左右されないよう、また、樹脂の硬化が進行しないようあらかじめ４０℃以上１００℃以下の一定の温度に保っておくことが望ましい。次に半導体チップ３および基板５それぞれのアライメントマークを検出して、半導体チップのはんだバンプ８と基板の電極パッド９の接続位置が一致するよう、位置決めを行う。ヒートツール１には半導体チップ３を加熱・加圧する機構が設けられており、半導体チップ３を加熱しながら基板５に押し付ける（図２（ｄ））。このとき、熱は半導体チップ３を通り、熱硬化性接着剤層４に伝わる。したがって熱硬化性接着剤層４は温度が高くなり、流動性が高まるため、半導体チップ３と基板５が接着され、仮圧着積層体が得られる。
　次に、図２（ｅ）に示す本圧着工程を行う。本圧着工程においては、仮圧着の場合と同様、ヒートツール１を用いて半導体チップ３を加熱しながら基板に押し付けるが、ヒートツール１の温度は、熱硬化性接着剤層４を硬化させるとともにはんだバンプ８のはんだが溶融するよう、温度がコントロールされる。ヒートツール１と半導体チップ３との間には、熱伝導率１００Ｗ／ｍＫ以上の保護フィルム２を介在させる。
　本発明では、熱伝導性の高い保護フィルム２を用いているので、ヒートツール１からの熱伝導が速く、熱硬化性接着剤層４が硬化する前に、はんだが溶融する。そのため、はんだの溶融時に熱硬化性接着剤層４が流動性を保ったままであるので、はんだバンプ８と電極パッド９との接合を良好に行うことができる。また、接着剤がはみ出してもヒートツール１と半導体チップ３との間に保護フィルム２があるので、ヒートツール１が接着剤により汚染されることなくボンディングを行うことができる。熱硬化性接着剤層４の硬化を進めるため、本圧着工程の後にさらに加熱を行ってもよい。
　保護フィルム２は、ヒートツール１に予め貼り付けられても、ボンディング時に半導体チップ３とヒートツール１との間に挿入されても良い。図３に示すように、保護フィルム２をリール・トゥ・リールで供給すると、半導体チップ３とヒートツール１との間に、保護フィルム２の新しい面を供給することが容易になるので好ましい。図３の装置において、保護フィルム２は、供給リール１２から供給され、ボンディング装置内において、ヒートツール１と半導体チップ３の間を通過し、巻き取りリール１３に巻き取られるように設置される。好ましい態様の一つは、供給リール１２および巻き取りリール１３が、ボンディング装置の動作に合わせて駆動され、１回のボンディング毎に、供給リール１２および巻き取りリール１３が駆動して、ヒートツール１と半導体チップ３の間に、保護フィルム２の新しい面が供給されるようにすることである。また、１回のボンディング毎に、リールを駆動させるのではなく、数回のボンディング毎に１回リールを駆動させてもよい。また、リールを一定速度で連続的に駆動させ、保護フィルム２の新しい面が、少しずつ連続的に供給されるようにしても良い。
　本発明の第２の半導体装置の製造方法は、バンプおよび貫通電極を有する複数の半導体チップならびに該バンプに対応した電極を有する基板を、熱硬化性接着剤層を介してはんだ接続する半導体装置の製造方法であって：
（Ａ’）複数の半導体チップそれぞれのバンプを有する面に、あらかじめ熱硬化性接着剤層を形成して、熱硬化性接着剤層が形成された半導体チップを複数得る工程、
（Ｂ’）熱硬化性接着剤層が形成された１つの半導体チップの熱硬化性接着剤層側の面と基板とを合わせて、ヒートツールを用いて仮圧着する工程、および、１回以上の該半導体チップの半導体チップ側の面と熱硬化性接着剤層が形成された他の半導体チップの熱硬化性接着剤層側の面を合わせて、ヒートツールを用いて仮圧着する工程を経て多段仮圧着積層体を得る工程、
（Ｃ’）該ヒートツールと該多段仮圧着積層体における半導体チップ側の面との間に、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを介在させ、ヒートツールを用いて、複数の半導体チップの間および半導体チップと基板との間のはんだを溶融させると同時に熱硬化性接着剤層を硬化させる工程、
をこの順に有する。
　まず、工程（Ａ’）では、半導体チップのバンプを有する面にあらかじめ熱硬化性接着剤層が形成される。熱硬化性接着剤層を形成する方法は、第１の製造方法と同様の方法を用いることができる。本製造方法では、多段にチップの積層体を形成する。そのため、半導体ウェハ上に熱硬化性接着剤層を形成し、熱硬化性接着剤層と半導体ウェハを同時にダイシングして得られたチップを用いることが、得られる積層体からの熱硬化性接着剤層のはみ出しを極小にすることができるため、特に好ましい。
　次に工程（Ｂ’）では、仮圧着を行う。仮圧着工程では、まず、第１の製造方法と同様に、熱硬化性接着剤層が形成された１つの半導体チップの熱硬化性接着剤層側の面と基板を合わせ、ボンディング装置のヒートツールを用いて加熱・加圧することにより仮圧着する。さらに仮圧着された半導体チップの半導体チップ側の面と熱硬化性接着剤層が形成された他の半導体チップの熱硬化性接着剤層側の面を合わせて仮圧着する。この工程を繰り返して、複数の半導体チップが積層されて仮圧着された、多段仮圧着積層体を形成する。
　仮圧着のヒートツールの好ましい温度条件は、第１の製造方法と同様だが、積層の段数が増えるとヒートツールからの熱伝達が変化するため、積層の段数ごとに温度を変化させることもできる。
　仮圧着の際、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムをヒートツールの半導体チップと接する面に貼り付けておくこともできる。この場合、一旦半導体チップからヒートツールを離すことなく、連続で後述の本圧着工程（Ｃ’）を行うことができる。
　本圧着工程（Ｃ’）では、第１の製造方法と同様に、ヒートツールと多段仮圧着積層体の半導体チップ側の面との間に、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを介在させ、複数の半導体チップの間および半導体チップと基板との間のはんだを溶融させると同時に熱硬化性接着剤層を硬化させる。この上にさらに熱硬化性接着剤層が形成された他の半導体チップの熱硬化性接着剤層側の面を合わせて工程（Ｂ’）により多段仮圧着積層体を形成し、その後で本圧着工程（Ｃ’）を行うことも可能である。
　以下に、第２の製造方法の各工程について例を挙げて説明するが、本発明は下記の例に限定されない。
　まず、図４（ａ）に工程（Ａ’）の例を示す。この例では、貫通電極（ＴＳＶ）１１を有する半導体チップ３を用いる。ＴＳＶ１１を有する半導体チップ３の片方の面のＴＳＶ１１上に、銅ピラー７が設けられ、銅ピラー７の上に半球状のはんだバンプ８が形成されている。反対側の面のＴＳＶ１１上には、電極パッド９が形成されている。第１の製造方法と同様に、半導体チップ３のはんだバンプ８が形成されている面に、プラスチックフィルム１０上に熱硬化性接着剤層４が形成された熱硬化性接着剤フィルムをラミネートした後、プラスチックフィルム１０を剥離することにより、半導体チップ３のはんだバンプ８が形成されている面に、熱硬化性接着剤層４を形成する。
　複数の半導体チップ３のバンプ８を有する面に、工程（Ａ’）に従って熱硬化性接着剤層４を形成し、熱硬化性接着剤層が形成半導体チップを複数得る（図４（ｂ））。
　次に、熱硬化性接着剤層４が形成された１つの半導体チップの熱硬化性接着剤層側の面と基板５を合わせて、第１の製造方法と同様に仮圧着する。さらに、図４（ｃ）に示すように、仮圧着された半導体チップの半導体チップ側の面と熱硬化性接着剤層４が形成された他の半導体チップ３の熱硬化性接着剤層側４の面を合わせて仮圧着する。この工程を繰り返して、複数の半導体チップが積層されて仮圧着された、多段仮圧着積層体を形成する（図４（ｄ））。
　最後に、第１の製造方法と同様に、ヒートツール１と前記多段仮圧着積層体における半導体チップ側の面との間に、熱伝導率１００Ｗ／ｍＫ以上の保護フィルム２を介在させ、複数の半導体チップの間および半導体チップと基板との間のはんだを溶融させると同時に熱硬化性接着剤層を硬化させる本圧着工程を実施する（図４（ｅ））。
　以下、本発明の半導体装置の製造方法についてより具体的に説明するが、本発明はこれらに限定されるものではない。
　以下実施例等をあげて本発明を説明するが、本発明はこれらの例によって限定されるものではない。実施例１～１４、比較例１～６に用いた材料と評価方法を下記に示す。
　＜半導体チップの構造＞
　シリコンウェハの酸化膜上に厚さ１μｍのアルミニウム配線を形成し、さらにその上に厚さ１μｍの窒化シリコン絶縁膜を形成した。該窒化シリコン絶縁膜に、シリコンウェハと導通するように開口部を設け、該開口部にクロム層を形成し、該クロム層上に、高さ１０μｍの銅ポストと高さ５μｍのはんだ（ＳｎＡｇ）半球からなるバンプを形成し、半導体チップを作製した。１つの半導体チップの中に、２５μｍ、３０μｍ、３５μｍおよび４０μｍの４種類のバンプ径を有するバンプを設けた。なお、バンプピッチは、それぞれのバンプ径に対して７５μｍ、８０μｍ、８５μｍおよび９０μｍの４種類のものが形成された。また、設けたバンプ数は、前記各ピッチに対して、それぞれ１７４個、１６２個、１５０個および１３８個であった。基板への実装後に、各バンプ構造に対して接続抵抗が測定できるように、半導体チップにはアルミニウム配線がパターニングされている。１枚のシリコンウェハに多数の半導体チップが形成され、それぞれの半導体チップのチップサイズは、７ｍｍ×７ｍｍ、チップ厚は１００μｍである。各半導体チップには位置決めのためのアライメントマークが形成されている。
　＜基板＞
　シリコン基板（膜厚１００μｍ）の酸化膜上に厚さ１μｍのアルミニウム配線を形成し、さらにその上に厚さ１μｍの窒化シリコン絶縁膜を形成した。該窒化シリコン絶縁膜に、シリコン基板と導通するように開口部を設け、該にクロム層を形成し、該クロム層上に膜厚５μｍの銅および膜厚１μｍのニッケル／金からなる電極パッドを形成して基板を作製した。電極パッドの位置および径は、全て前記半導体チップのバンプに対応するよう形成されている。基板サイズは、１２ｍｍ×１２ｍｍ、基板厚は１００μｍであり、基板上のチップが搭載されない領域に、２ｍｍ角の引き出し電極のパッドが形成されている。上記半導体チップを基板に実装することにより、ディジーチェーンが形成され、引き出し電極を通じてバンプと電極パッドとの接合抵抗が測定できる。基板には、位置決めのためのアライメントマークが形成されている。
　＜保護フィルム＞
　熱伝導率１００Ｗ／ｍＫ以上の保護フィルムとして、アルミニウム箔と銅箔を使用した。また熱伝導率１００Ｗ／ｍＫ未満の保護フィルムとして、フッ素樹脂フィルムと鉄箔を使用した。熱拡散率測定システム（株式会社アイフェイズ製、１μ）を用いて測定した熱伝導率は、それぞれアルミニウム箔が２３０Ｗ／ｍＫ、銅箔が４００Ｗ／ｍＫ、フッ素樹脂フィルムが０．２５Ｗ／ｍＫ、鉄箔が７０Ｗ／ｍＫであった。アルミニウム箔の膜厚は、６μｍ、１２μｍおよび１８μｍ、銅箔の膜厚は、３μｍ、５μｍ、１８μｍおよび３０μｍ、フッ素樹脂フィルムの膜厚は、１２μｍおよび３０μｍ、鉄箔の膜厚は２０μｍのものを用いた。
　＜熱硬化性接着剤フィルムの作製＞
　以下に記載した（ａ）ポリイミド、（ｂ）エポキシ樹脂および（ｃ）硬化促進剤を混合し、さらに（ｄ）溶剤を塗布膜厚が均一になるよう適宜調整しながら加えて、熱硬化性接着剤を得た。該熱硬化性接着剤を、離型性のプラスチックフィルム（ポリエチレンテレフタレートフィルム）上に塗布および乾燥することにより、プラスチックフィルム上に熱硬化性接着剤層が形成された熱硬化性接着剤フィルム１を作製した。（ａ）ポリイミド、（ｂ）エポキシ樹脂および（ｃ）硬化促進剤の比率が、重量比で５０：２０：５０となるよう混合した。熱硬化性接着剤層の厚さは２５μｍだった。
　また以下に記載した（ａ）ポリイミド、（ｂ）エポキシ樹脂、（ｃ）硬化促進剤および（ｅ）絶縁性フィラーを混合し、さらに（ｄ）溶剤を塗布膜厚が均一になるよう適宜調整しながら加えて、熱硬化性接着剤を得た。該熱硬化性接着剤を、離型性のプラスチックフィルム（ポリエチレンテレフタレートフィルム）上に塗布および乾燥することにより、プラスチックフィルム上に熱硬化性接着剤層が形成された熱硬化性接着剤フィルム２を作製した。（ａ）ポリイミド、（ｂ）エポキシ樹脂、（ｃ）硬化促進剤および（ｅ）絶縁性フィラーの比率が重量比で２５：１０：２５：５０となるよう混合した。熱硬化性接着剤層の厚さは２５μｍだった。
　なお、（ｃ）硬化促進剤は、マイクロカプセル型硬化促進剤がエポキシ樹脂に分散されたものであり、それらの重量比はマイクロカプセル型硬化促進剤／エポキシ樹脂＝３３／６７である。しかし、上記の混合割合においては（ｃ）硬化促進剤の割合は、（ｃ）硬化促進剤全体の量を基準に算出している。また、（ｂ）エポキシ樹脂の割合には（ｃ）硬化促進剤中のエポキシ樹脂は含めていない。
　（ａ）ポリイミド
　下記プロセスで合成した有機溶剤可溶性ポリイミドを用いた。まず、乾燥窒素気流下、２，２－ビス（３－アミノ－４－ヒドロキシフェニル）ヘキサフルオロプロパン２４．５４ｇ（０．０６７モル）、１，３－ビス（３－アミノプロピル）テトラメチルジシロキサン４．９７ｇ（０．０２モル）および末端封止剤として、３－アミノフェノール２．１８ｇ（０．０２モル）をＮＭＰ８０ｇに溶解させた。ここにビス（３，４－ジカルボキシフェニル）エーテル二無水物３１．０２ｇ（０．１モル）をＮＭＰ２０ｇとともに加えて、２０℃で１時間反応させ、次いで５０℃で４時間撹拌した。その後、キシレンを１５ｇ添加し、水をキシレンとともに共沸させながら、１８０℃で５時間攪拌した。攪拌終了後、溶液を水３Ｌに投入して白色沈殿したポリマーを得た。この沈殿をろ過して回収し、水で３回洗浄した後、真空乾燥機を用いて８０℃、２０時間乾燥した。
　（ｂ）エポキシ樹脂
　固形のエポキシ化合物（三菱化学（株）製、エポキシ樹脂１５７Ｓ７０）を使用した。
　（ｃ）硬化促進剤
　マイクロカプセル型硬化促進剤（旭化成ケミカルズ（株）製、ノバキュア（登録商標）ＨＸ－３９４１ＨＰ）を使用した。
　（ｄ）溶剤
　メチルエチルケトン／トルエン＝４／１（重量比）を使用した。
　（ｅ）絶縁性無機フィラー
　ＳＯ－Ｅ２（商品名、アドマテックス（株）製、球形シリカ粒子、平均粒子径０．５μｍ）を用いた。
　＜熱硬化性接着剤材フィルム付き半導体チップの作製＞
　熱硬化性接着剤層の半導体チップのバンプへの埋め込みは、真空加圧ラミネーター（（株）名機製作所製、ＭＶＬＰ５００／６００）を用いて行った。上記のようにして作製した熱硬化性接着剤フィルムの熱硬化性接着剤層側の面を、前記の半導体チップが多数形成されたシリコンウェハのバンプ形成面に押し付けながら、真空中で８０℃、２０秒間、加圧０．７ＭＰａの条件でラミネートした。シリコンウェハ周囲の余分な熱硬化性接着剤フィルムはカッターにて切断した。ここで使用したシリコンウェハは８インチサイズである。
　次に、ウェハマウンター装置（テクノビジョン（株）製、ＦＭ－１１４６－ＤＦ）を用い、熱硬化性接着剤層が形成された半導体ウェハ基板のバンプとは反対側の面をテープフレームに張られたダイシングテープ（リンテック（株）製、Ｄ－６５０）に貼り合わせた。熱硬化性接着剤層からポリエチレンテレフタレートフィルムを除去してから、ダイシング装置（ＤＩＳＣＯ（株）製、ＤＦＤ－６２４０）の切削ステージ上に、熱硬化性接着剤層面が上になるようテープフレームを固定した。次いで、以下のような切削条件でダイシングを行った。
ブレード：ＮＢＣ－ＺＨ　１２７Ｆ－ＳＥ　２７ＨＣＣＣ
スピンドル回転数：２５０００ｒｐｍ
切削速度：５０ｍｍ／ｓ
切削深さ：ダイシングテープの深さ２０μｍまで切り込む
カット：ワンパスフルカット
カットモード：ダウンカット
切削水量：３．７Ｌ／分
切削水および冷却水：温度２３℃、電気伝導度０．５ＭΩ・ｃｍ（超純水に炭酸ガスを注入）。
　ダイシングにより個片チップ化した半導体チップについて、熱硬化性接着剤層表面への切削粉の付着、熱硬化性接着剤層表面の割れや欠け、および、ウェハからの熱硬化性接着剤剤フィルムの剥がれは見られなかった。
　＜ボンディング＞
　上記のようにして作製された熱硬化性接着剤材フィルム付き半導体チップの、熱硬化性接着剤層が形成された面を上側にしてチップトレイに収納し、ボンディング装置（東レエンジニアリング（株）製、ＦＣ３０００Ｓ）に供給した。一方、上記の基板を、ボンディング装置の６０℃に保たれたステージ上に設置した。
　まず、チップトレイに収納された半導体チップをピックアップツールで取り上げ、チップの面を反転させた。次に、半導体チップの半導体チップ側の面を、搬送装置が真空吸着し、半導体チップをステージ上に置かれた基板の上方まで搬送した。次に半導体チップのバンプと基板上の電極パッドが所定の位置に重なるようにアライメント認識カメラが半導体チップと基板の間に入り、それぞれのアライメントマークの検出を行った。
　アライメントマークに基づいて、半導体チップのバンプと基板の電極パッドの接続位置が一致するよう、位置を調整した後、ボンディング装置のヒートツールを用いて、半導体チップに圧力１５Ｎ、温度１００℃で１０秒の加熱および加圧を行うことによって仮圧着を行い、仮圧着積層体を作製した。
　ヒートツールのアタッチメントの表面温度は、あらかじめ温度レコーダ（（株）キーエンス製、ＮＲ１００）とＫ熱電対を用いて校正を行った。
　次に、ヒートツールと仮圧着積層体における半導体チップ側の面との間に、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを介在させ、本圧着を行って半導体チップと基板との間のはんだを溶融させるとともに熱硬化性接着剤層を硬化させた。本圧着は、まず、圧力４０Ｎ、温度１００℃で１０秒間保持した後、圧力４０Ｎ、温度２５０℃で２０秒間処理した。
　＜実装性評価＞
　実装後に形成されたディジーチェーンの導通抵抗測定（導通評価）およびバンプ接続部分の断面観察（断面観察評価）により、実装性の評価を行った。
　各実施例の評価で用いた半導体チップと基板は、各バンプピッチに対して、それぞれ１３８個、１５０個、１６２個、１７４個形成の接続部分を介して電気的に接続されるよう設計されている。バンプと電極パッドが一つでも接触していない部分があれば、接続不良となる。ここでは、ＤＩＧＩＴＡＬ　ＶＯＬＴＭＥＴＥＲ（ＨＥＷＬＥＴＴ　ＰＡＣＫＡＲＤ社製、３４５５Ａ）の測定端子を接続し、その抵抗値を測定した。抵抗値はバンプと電極パッドの接続部分だけでなく、半導体チップ内部の抵抗やリード電極の値を含むものである。各バンプピッチのディジーチェーンに対して、それぞれ測定した抵抗値が全て１００ｋΩ未満であるか否かを判定した。３サンプルについて実装を行ったうち、３サンプルとも、測定したディジーチェーンの抵抗値が全て１００ｋΩ未満であった場合をＡ、１サンプルまたは２サンプルについてディジーチェーンの抵抗値が１００ｋΩ以上となるものがあった場合をＢ、３サンプルともディジーチェーンの抵抗値が１００ｋΩ以上となるものがあった場合をＣと判定した。
　断面観察評価については、任意の箇所で切断して顕微鏡観察したバンプについて、はんだバンプと基板上の銅パッドとの界面に樹脂やフィラーが、銅パッドの径に対して１０％以上噛み込んでいるか否かを判定した。３サンプルについて実装を行ったうち、３サンプルとも銅パッドの径に対して１０％以上の噛み込みが無い場合をＡ、１サンプルまたは２サンプル１０％以上の噛み込みがあった場合をＢ、３サンプルとも１０％以上の噛み込みがあった場合をＣと判定した。
　実施例１～実施例３
　保護フィルムとして、それぞれ厚さ６μｍ、１２μｍおよび２０μｍのアルミニウム箔を用い、また熱硬化性接着剤フィルムとして、熱硬化性接着剤フィルム２を用いて、上記の方法で実装性を評価した。実施例１～実施例３についてはピックアップツールへのはみ出した熱硬化性接着剤剤フィルムの貼り付きもなく、導通評価および断面観察評価は、いずれもＡだった。結果を表１に示す。
　実施例４～実施例６
　熱硬化性接着剤剤フィルムとして、熱硬化性接着剤フィルム１を用いた以外は、それぞれ実施例１～実施例３と同様に評価を行った。導通評価および断面観察評価は、いずれもＡだった。結果を表１に示す。
　実施例７～実施例１０
　保護フィルムとして、それぞれ厚さ３μｍ、５μｍ、１８μｍおよび３０μｍの銅箔を用いた以外は実施例１と同様に評価を行った。膜厚３０μｍの銅箔を用いた場合（実施例１０）は、１サンプルについて断面観察で１０％以上の噛み込みがあったが、他はピックアップツールへのはみ出した熱硬化性接着剤剤フィルムの貼り付きもなく、導通評価および断面観察評価は、いずれもＡであった。結果を表１に示す。
　実施例１１～実施例１４
　熱硬化性接着剤剤フィルムとして熱硬化性接着剤フィルム１を用いた以外は、それぞれ実施例７～実施例１０と同様に評価を行った。導通評価および断面観察評価は、いずれもＡだった。結果を表１に示す。
　実施例１５
　半導体チップとして、２００μｍピッチで直径５０μｍの銅のＴＳＶが形成されたシリコン基板を用いた。１枚のシリコンウェハに多数の半導体チップが形成され、それぞれの半導体チップのチップサイズは、７ｍｍ×７ｍｍである。ＴＳＶは、７ｍｍ角のチップに２６×２７個形成されている。半導体チップの一方の面のＴＳＶ上に１μｍの厚さのポリイミドパッシベーション膜を介して厚さ１μｍの銅配線を形成し、さらにその上に厚さ１μｍのポリイミド絶縁膜を形成した。該ポリイミド絶縁膜に、ＴＳＶと電気的に接続するように設けられた開口部にクロム層を形成し、該開口部に、高さ１０μｍの銅ポストと高さ５μｍのはんだ（ＳｎＡｇ）半球からなるバンプを形成し、半導体チップを作製した。バンプ径は３０μｍである。基板への実装後に、各バンプに対して接続抵抗が測定できるよう銅配線がパターニングされている。チップ厚は１００μｍである。また、半導体チップのバンプとは反対側の面には、１μｍの厚さのポリイミド絶縁膜にＴＳＶと電気的に接続されるよう設けられた開口部にクロム層を形成し、該開口部に、膜厚５μｍ銅および膜厚１μｍのニッケル／金からなる電極パッドを形成した。
　シリコン基板（膜厚１００μｍ）の酸化膜上に厚さ１μｍのアルミニウム配線を形成し、さらにその上に厚さ１μｍの窒化シリコン絶縁膜を形成した。該窒化シリコン絶縁膜に、シリコン基板と導通するように設けられた開口部にクロム層を形成し、該開口部に膜厚５μｍの銅および膜厚１μｍのニッケル／金からなる電極パッドを形成して基板を作製した。電極パッドの位置および径は全て前記半導体チップのバンプに対応するよう形成されている。基板サイズは、１２ｍｍ×１２ｍｍ、基板厚は１００μｍであり、基板上のチップが搭載されない領域に、２ｍｍ角の引き出し電極のパッドが形成されている。上記半導体チップを基板に実装することにより、ディジーチェーンが形成され、引き出し電極を通じてバンプと電極パッドとの接合抵抗が測定できる。
　前記＜熱硬化性接着剤材フィルム付き半導体チップの作製＞工程において用いたシリコンウェハの代わりに、上記のＴＳＶが形成されたシリコンウェハを用いた以外は、前記＜熱硬化性接着剤材フィルム付き半導体チップの作製＞工程と同様にして、熱硬化性接着剤層付き半導体チップを得た。
　この熱硬化性接着剤層付き半導体チップを用いた以外は、前記の＜ボンディング＞工程における仮圧着工程と同様にして、基板上に半導体チップが１段積層された仮圧着積層体を形成した。さらに同様の工程を３回繰り返して、基板上に半導体チップが４段積層された４段仮圧着積層体を形成した。次に、ヒートツールと４段仮圧着積層体における半導体チップ側の面との間に、厚さ１２μｍのアルミニウム箔の保護フィルムを介在させ、前記＜ボンディング＞工程における本圧着工程と同様の方法にて本圧着を行った。
　また実装性評価は、実施例１と同様にして行った。なお断面観察評価において、実施例１で得られた半導体装置は半導体チップが１段であり、本実施例では半導体チップは４段であるが、本実施例においては半導体チップ４段積層された半導体装置を切断して行った。結果を表１に示す。
　比較例１、２
　保護フィルムとして、それぞれ厚さ１２μｍおよび３０μｍのフッ素樹脂フィルムを用いた以外は実施例１と同様に評価を行った。ピックアップツールへのはみ出した熱硬化性接着剤層の貼り付きはなかったが、導通評価および断面観察評価は、いずれもＣだった。結果を表１に示す。
　比較例３、４
　熱硬化性接着剤フィルムとして熱硬化性接着剤フィルム１を用いた以外は、それぞれ比較例１、２と同様に評価を行った。厚さ１２μｍの保護フィルムを用いた場合（比較例３）は、１サンプルのみ、導通評価において、ディジーチェーンの抵抗値が全て１００ｋΩ未満となるものがありＢであった。また断面観察評価はＣだった。結果を表１に示す。
　比較例５
　保護フィルムとして、厚さ２０μｍの鉄箔を用いた以外は実施例１と同様に評価を行った。ピックアップツールへのはみ出した熱硬化性接着剤層の貼り付きはなかったが、導通評価および断面観察評価は、いずれもＣだった。結果を表１に示す。
　比較例６
　熱硬化性接着剤フィルムとして熱硬化性接着剤フィルム１を用いた以外は比較例５と同様に評価を行った。導通評価はＡとなったが、断面観察評価はＣだった。結果を表１に示す。
　比較例７
　保護フィルムに厚さ３０μｍのフッ素樹脂フィルムを使用した以外は実施例１５と同様に評価を行った。結果を表１に示す。
Figure JPOXMLDOC01-appb-T000001
１　ヒートツール
２　保護フィルム
３　半導体チップ
４　熱硬化性接着剤層
５　基板
６　ステージ
７　銅ピラー
８　はんだバンプ
９　電極パッド
１０　プラスチックフィルム
１１　貫通電極（ＴＳＶ）
１２　供給リール
１３　巻き取りリール
　本発明の製造方法によれば、接着剤フィルムを介してバンプと電極パッドとを容易にはんだ接続でき、高い歩留りで半導体装置を製造することが可能となる。
　本発明は、ＩＣ、ＬＳＩ等の半導体チップを、フレキシブル基板、ガラスエポキシ基板、ガラス基板、セラミックス基板、シリコンインターポーザー、シリコン基板などの回路基板にはんだ接続した半導体装置、あるいは、半導体チップ同士をはんだ接続した半導体チップ積層体などの半導体装置の製造に適している。

Claims (9)

  1. バンプを有する半導体チップを、該バンプに対応した電極を有する基板に、熱硬化性接着剤層を介してはんだ接続する半導体装置の製造方法であって：
    （Ａ）半導体チップのバンプを有する面に、あらかじめ熱硬化性接着剤層を形成する工程、
    （Ｂ）熱硬化性接着剤層が形成された半導体チップの熱硬化性接着剤層側の面と基板とを合わせて、ヒートツールを用いて仮圧着し、仮圧着積層体を得る工程、
    （Ｃ）該ヒートツールと該仮圧着積層体の半導体チップ側の面との間に、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを介在させ、ヒートツールを用いて、半導体チップと基板との間のはんだを溶融させると同時に熱硬化性接着剤層を硬化させる工程、
    をこの順に有する半導体装置の製造方法。
  2. バンプおよび貫通電極を有する複数の半導体チップならびに該バンプに対応した電極を有する基板を、熱硬化性接着剤層を介してはんだ接続する半導体装置の製造方法であって：
    （Ａ’）複数の半導体チップそれぞれのバンプを有する面に、あらかじめ熱硬化性接着剤層を形成して、熱硬化性接着剤層が形成された半導体チップを複数得る工程、
    （Ｂ’）熱硬化性接着剤層が形成された１つの半導体チップの熱硬化性接着剤層側の面と基板とを合わせて、ヒートツールを用いて仮圧着する工程、および、１回以上の該半導体チップの半導体チップ側の面と熱硬化性接着剤層が形成された他の半導体チップの熱硬化性接着剤層側の面を合わせて、ヒートツールを用いて仮圧着する工程を経て多段仮圧着積層体を得る工程、
    （Ｃ’）該ヒートツールと該多段仮圧着積層体における半導体チップ側の面との間に、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを介在させ、ヒートツールを用いて、複数の半導体チップの間および半導体チップと基板との間のはんだを溶融させると同時に熱硬化性接着剤層を硬化させる工程、
    をこの順に有する請求項１に記載の半導体装置の製造方法。
  3. （Ａ）工程において、半導体チップのバンプを有する面に、あらかじめ熱硬化性接着剤フィルムをラミネートすることにより熱硬化性接着剤層を形成する半導体装置の製造方法。
  4. （Ａ’）工程において、複数の半導体チップそれぞれのバンプを有する面に、あらかじめ熱硬化性接着剤フィルムをラミネートすることにより熱硬化性接着剤層を形成する請求項２に記載の半導体装置の製造方法。
  5. 前記熱硬化性接着剤層が、絶縁性無機フィラーを含有する請求項１～４いずれかに記載の半導体装置の製造方法。
  6. 前記保護フィルムがアルミニウム箔または銅箔である請求項１～５のいずれかに記載の半導体装置の製造方法。
  7. 前記基板がシリコン基板である請求項１～６のいずれかに記載の半導体装置の製造方法。
  8. 前記保護フィルムをリール・トゥ・リールで供給する請求項１～７のいずれかに記載の半導体装置の製造方法。
  9. 基板と半導体チップとをボンディングして半導体装置を製造するための装置であって、
    基板を設置するためのステージ、および、半導体チップを加熱・加圧する機構を有するヒートツールを備えたボンディング装置と、熱伝導率１００Ｗ／ｍＫ以上の保護フィルムを供給する供給リールと、該保護フィルムを巻き取る巻き取りリールとを備え、
    供給リールから供給された保護フィルムが、ヒートツールとステージの間を通過して、巻き取りリールに巻き取られるように配置された半導体装置の製造装置。
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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104701220A (zh) * 2013-12-09 2015-06-10 贝思瑞士股份公司 用于将基板的基板位置压紧的压紧器
WO2015199045A1 (ja) * 2014-06-26 2015-12-30 東レエンジニアリング株式会社 実装装置および実装方法
WO2016158960A1 (ja) * 2015-03-31 2016-10-06 デクセリアルズ株式会社 半導体装置の製造方法
WO2016158935A1 (ja) * 2015-03-30 2016-10-06 東レエンジニアリング株式会社 半導体装置の製造方法、半導体実装装置および半導体装置の製造方法で製造されたメモリデバイス
JP2016201418A (ja) * 2015-04-08 2016-12-01 積水化学工業株式会社 半導体接合用接着フィルム及び半導体装置の製造方法
JP2017045890A (ja) * 2015-08-27 2017-03-02 日立化成株式会社 半導体装置及びそれを製造する方法
JP2017045994A (ja) * 2015-08-28 2017-03-02 日立化成株式会社 電子部品装置の製造方法及び電子部品装置
JP2017162927A (ja) * 2016-03-08 2017-09-14 日立化成株式会社 半導体装置を製造する方法
JP2017183456A (ja) * 2016-03-30 2017-10-05 東レエンジニアリング株式会社 半導体装置の製造方法及び製造装置
WO2018061982A1 (ja) * 2016-09-30 2018-04-05 デクセリアルズ株式会社 半導体装置の製造方法
WO2019107395A1 (ja) * 2017-12-01 2019-06-06 株式会社新川 実装装置
JPWO2018143222A1 (ja) * 2017-01-31 2019-06-27 株式会社新川 半導体チップの実装装置および実装方法
JP2019110187A (ja) * 2017-12-18 2019-07-04 東レエンジニアリング株式会社 実装装置及び実装方法
JP2020074384A (ja) * 2019-10-08 2020-05-14 東レエンジニアリング株式会社 実装装置および実装方法
US10669454B2 (en) 2015-10-29 2020-06-02 Hitachi Chemical Company, Ltd. Method for manufacturing semiconductor device including heating and pressuring a laminate having an adhesive layer
US10734350B2 (en) 2016-05-09 2020-08-04 Hitachi Chemical Company, Ltd. Method for manufacturing semiconductor device
JP2020178139A (ja) * 2015-11-04 2020-10-29 リンテック株式会社 半導体装置の製造方法
TWI780805B (zh) * 2020-07-07 2022-10-11 南韓商普羅科技有限公司 加壓式銅柱基板結合方法
WO2024009498A1 (ja) * 2022-07-08 2024-01-11 株式会社レゾナック 半導体装置の製造方法、基板及び半導体素子

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5876000B2 (ja) * 2012-06-11 2016-03-02 株式会社新川 ボンディング装置およびボンディング方法
KR101435459B1 (ko) * 2014-03-26 2014-08-28 실리콘밸리(주) 접착제를 이용하여 금속 박판을 적층한 반도체 검사 패드 및 제조방법
JP2018515908A (ja) 2015-04-10 2018-06-14 エーファウ・グループ・エー・タルナー・ゲーエムベーハー ２つの基板をボンディングするための基板ホルダおよび方法
KR102341750B1 (ko) 2015-06-30 2021-12-23 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
CN105428263A (zh) * 2015-12-16 2016-03-23 南通富士通微电子股份有限公司 半导体封装方法
JP6688543B2 (ja) * 2016-03-30 2020-04-28 東レエンジニアリング株式会社 半導体装置の製造方法及び半導体装置の製造装置
JP6316873B2 (ja) * 2016-05-31 2018-04-25 株式会社新川 ダイの実装方法
KR102521881B1 (ko) * 2016-06-15 2023-04-18 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US20180005916A1 (en) * 2016-06-30 2018-01-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
SG11201901693YA (en) * 2016-09-09 2019-03-28 Toray Industries Resin composition
JP6789791B2 (ja) * 2016-12-13 2020-11-25 東レエンジニアリング株式会社 半導体装置の製造装置および製造方法
TWI692044B (zh) * 2017-05-29 2020-04-21 日商新川股份有限公司 封裝裝置以及半導體裝置的製造方法
KR102012237B1 (ko) * 2017-11-24 2019-08-21 한국기계연구원 마이크로 소자 어레이 전사방법
WO2019194208A1 (ja) * 2018-04-04 2019-10-10 住友電工プリントサーキット株式会社 フレキシブルプリント配線板用カバーフィルム及びフレキシブルプリント配線板
CN109003907B (zh) * 2018-08-06 2021-10-19 中芯集成电路（宁波）有限公司 封装方法
TWI669794B (zh) * 2018-09-27 2019-08-21 頎邦科技股份有限公司 基板與晶片之壓合步驟及其壓合裝置
US11309278B2 (en) 2018-10-29 2022-04-19 Applied Materials, Inc. Methods for bonding substrates
TWI774936B (zh) 2019-03-08 2022-08-21 台灣愛司帝科技股份有限公司 承載結構及承載設備
JP7259942B2 (ja) * 2019-03-29 2023-04-18 株式会社村田製作所 樹脂多層基板、および樹脂多層基板の製造方法
TWI743726B (zh) * 2019-04-15 2021-10-21 日商新川股份有限公司 封裝裝置
US10854530B1 (en) * 2019-07-31 2020-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Heat dissipation structures
CN114585684A (zh) * 2019-10-24 2022-06-03 松下知识产权经营株式会社 密封用树脂组合物及半导体装置
CN113556882B (zh) * 2020-04-23 2022-08-16 鹏鼎控股(深圳)股份有限公司 透明电路板的制作方法以及透明电路板
WO2022013995A1 (ja) * 2020-07-16 2022-01-20 株式会社新川 実装装置
US20240196530A1 (en) * 2021-03-30 2024-06-13 Mitsui Mining & Smelting Co., Ltd. Multilayer substrate manufacturing method and wiring substrate
CN113130336A (zh) * 2021-04-16 2021-07-16 中国电子科技集团公司第二十四研究所 一种基板预植Au凸点的倒装焊工艺方法
CN118136525B (zh) * 2024-05-08 2024-07-23 日月新半导体(威海)有限公司 一种半导体封装结构及其制备方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07230873A (ja) * 1994-02-17 1995-08-29 Hitachi Chem Co Ltd 異方導電フィルム圧着装置
JPH11274241A (ja) * 1998-03-26 1999-10-08 Matsushita Electron Corp 半導体装置の製造方法
JP2003100807A (ja) * 2001-09-27 2003-04-04 Nitto Denko Corp 導電接続方法及びそれに用いる離型シート
JP2004319823A (ja) * 2003-04-17 2004-11-11 Sumitomo Bakelite Co Ltd 半導体用接着フィルム、半導体装置、及び半導体装置の製造方法。
JP2004315688A (ja) * 2003-04-17 2004-11-11 Sumitomo Bakelite Co Ltd 半導体用接着フィルム、半導体装置、及び半導体装置の製造方法。
JP2006049417A (ja) * 2004-08-02 2006-02-16 Seiko Epson Corp 半導体装置の実装装置及び実装方法、並びに半導体装置、電子機器
JP2006066625A (ja) * 2004-08-26 2006-03-09 Nec Corp ベアチップ実装装置、ベアチップ実装方法及びシート
JP2006229124A (ja) * 2005-02-21 2006-08-31 Canon Inc Ｉｃチップの接続方法および接続構造
JP2009111326A (ja) * 2007-10-09 2009-05-21 Hitachi Chem Co Ltd 回路部材の実装方法
JP2012028594A (ja) * 2010-07-26 2012-02-09 Shinko Electric Ind Co Ltd 電子部品実装装置及び電子部品の実装方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001237268A (ja) * 2000-02-22 2001-08-31 Nec Corp 半導体素子の実装方法及び製造装置

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07230873A (ja) * 1994-02-17 1995-08-29 Hitachi Chem Co Ltd 異方導電フィルム圧着装置
JPH11274241A (ja) * 1998-03-26 1999-10-08 Matsushita Electron Corp 半導体装置の製造方法
JP2003100807A (ja) * 2001-09-27 2003-04-04 Nitto Denko Corp 導電接続方法及びそれに用いる離型シート
JP2004319823A (ja) * 2003-04-17 2004-11-11 Sumitomo Bakelite Co Ltd 半導体用接着フィルム、半導体装置、及び半導体装置の製造方法。
JP2004315688A (ja) * 2003-04-17 2004-11-11 Sumitomo Bakelite Co Ltd 半導体用接着フィルム、半導体装置、及び半導体装置の製造方法。
JP2006049417A (ja) * 2004-08-02 2006-02-16 Seiko Epson Corp 半導体装置の実装装置及び実装方法、並びに半導体装置、電子機器
JP2006066625A (ja) * 2004-08-26 2006-03-09 Nec Corp ベアチップ実装装置、ベアチップ実装方法及びシート
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JP2009111326A (ja) * 2007-10-09 2009-05-21 Hitachi Chem Co Ltd 回路部材の実装方法
JP2012028594A (ja) * 2010-07-26 2012-02-09 Shinko Electric Ind Co Ltd 電子部品実装装置及び電子部品の実装方法

Cited By (39)

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Publication number Priority date Publication date Assignee Title
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US10734350B2 (en) 2016-05-09 2020-08-04 Hitachi Chemical Company, Ltd. Method for manufacturing semiconductor device
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