WO2011039888A1 - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device, wherein, even if the semiconductor device is brought into avalanche operation, the deterioration of the characteristics can be suppressed. The semiconductor device is provided with a first conductivity-type drift region, a second conductivity-type body region which is provided on the surface side of the drift region, a gate trench which passes through the body region and extends to the drift region, a gate electrode which is arranged in the gate trench, an insulator which is arranged between the gate electrode and the wall surface of the gate trench, and a second conductivity-type diffusion region which surrounds the bottom of the gate trench. The impurity concentration and size of the diffusion region are adjusted in such a manner that breakdown is caused in the p-n junction of the diffusion region and the drift region during the avalanche operation.

Description

Semiconductor device

The present invention relates to a trench gate type semiconductor device.

Japanese Patent Publication No. 2007-317779 discloses an example of a trench gate type semiconductor device. This semiconductor device includes an n-type drift region and a p-type body region provided on the surface side of the drift region. In this semiconductor device, a gate trench extending through the body region to the drift region is formed. The gate electrode is disposed in the gate trench and faces the body region via an insulator. A p-type diffusion region is formed in a range surrounding the bottom of the gate trench.

In this type of semiconductor device, an avalanche test is usually performed to confirm the reliability of the semiconductor device. However, it has been found that when an avalanche operation is performed on a conventional semiconductor device, the characteristics of the semiconductor device deteriorate. An object of the present specification is to provide a semiconductor device capable of suppressing deterioration in characteristics even when the avalanche operation is performed on the semiconductor device.

The inventor has sought the cause of the deterioration of the characteristics of the semiconductor device due to the avalanche operation. As a result, it has been found that the behavior of carriers generated during the avalanche operation is a cause of deteriorating the characteristics of the semiconductor device. That is, in the conventional semiconductor device, breakdown occurs at the pn junction between the body region and the drift region during the avalanche operation. Carriers (holes) generated by breakdown are collected in the vicinity of the gate electrode, and a part thereof is accumulated in an insulator in the vicinity of the gate electrode. When carriers (holes) are accumulated in the insulator, the gate capacitance increases, which causes a decrease in characteristics (for example, switching characteristics) of the semiconductor device. In particular, when the avalanche operation is continuously performed on the semiconductor device as in the continuous avalanche test, the amount of carriers (holes) accumulated in the insulator is large, so the influence is great.

The semiconductor device provided in the present specification includes a first conductivity type drift region, a second conductivity type body region, a gate trench, a gate electrode, an insulator, and a second conductivity type diffusion region. The body region is provided on the surface side of the drift region. The gate trench extends through the body region to the drift region. The gate electrode is disposed in the gate trench and faces the body region. The insulator is disposed between the gate electrode and the wall surface of the gate trench. The diffusion region surrounds the bottom of the gate trench and is surrounded by a drift region. The impurity concentration in the diffusion region is made higher than the impurity concentration in the body region.

“First conductivity type” and “second conductivity type” mean either n-type or p-type. That is, when the “first conductivity type” is n-type, the “second conductivity type” is p-type, and when the “first conductivity type” is p-type, the “second conductivity type” is n-type. It is a type.

In this semiconductor device, the impurity concentration in the diffusion region surrounding the bottom of the gate trench is higher than the impurity concentration in the body region. Therefore, when an avalanche operation is performed on this semiconductor device, breakdown occurs not at the pn junction between the body region and the drift region but at the pn junction between the diffusion region and the drift region. Since breakdown occurs at a pn junction further away from the gate electrode (that is, a pn junction between the diffusion region and the drift region), the amount of carriers gathered in the vicinity of the gate electrode can be reduced and accumulated in an insulator near the gate electrode. Can reduce the amount of carriers played. As a result, an increase in gate capacitance is suppressed, and deterioration in characteristics of the semiconductor device can be suppressed.

In this semiconductor device, a plurality of gate trenches can be arranged in a certain direction at intervals. In this case, a gate electrode and an insulator are disposed inside each gate trench, and a diffusion region of the second conductivity type can be provided at the bottom of each gate trench so as to surround the bottom.

When the semiconductor device includes a plurality of gate trenches, the width of the diffusion region in the gate trench arrangement direction is longer than the width when the breakdown voltage of the semiconductor device is maximized when the width of the diffusion region is changed, And it is preferable that it is shorter than the width | variety when adjacent diffused regions contact. By increasing the width of the diffusion region, it is possible to suitably break down the pn junction between the diffusion region and the drift region.

In the drift region, the impurity concentration in the vicinity of the side wall surface in the gate trench arrangement direction of the gate trench may be made lower than the impurity concentration in the intermediate portion of the adjacent gate trench. Since the electrical resistance of the drift region in the vicinity of the side wall surface of the gate trench is increased, it is possible to suppress carriers from being collected in the vicinity of the gate electrode.

Further, a shielding region is further provided between the body region and the diffusion region, which protrudes from the side wall surface in the gate trench arrangement direction of the gate trench into the drift region, and shields the flow of carriers from the diffusion region to the gate electrode. Also good. By forming the shielding region, it is possible to suppress carriers from being collected toward the gate electrode.

The top view of the semiconductor device of the 1st example. FIG. 2 is a sectional view taken along line II-II in FIG. 1. The figure which shows the impurity concentration distribution in a diffusion region (impurity concentration distribution along the III-III line of FIG. 1). The figure which shows the relationship between the width | variety of the x direction of a diffusion region, and the proof pressure of a semiconductor device. The figure which shows the impurity concentration distribution of the depth direction in a body area | region (impurity concentration distribution along the VV line of FIG. 1). Sectional drawing which shows the structure of the semiconductor device of 2nd Example. The figure for demonstrating the manufacturing method of the semiconductor device of 2nd Example. Sectional drawing which shows the structure of the semiconductor device of 3rd Example. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Example. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Example. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Example. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Example. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Example. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Example. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Example. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Example. The figure for demonstrating the manufacturing method of the semiconductor device of 3rd Example.

First Example A semiconductor device 10 according to a first example will be described with reference to the drawings. As shown in FIG. 1, the semiconductor device 10 includes a cell region 90 in which a semiconductor element is formed and a termination region 92 that surrounds the cell region 90. In FIG. 1, illustration of electrodes and the like formed on the upper surface of the semiconductor substrate is omitted. A plurality of gate trenches 26 are formed in the cell region 90. The gate trenches 26 extend in the y direction of FIG. 1 and are arranged at intervals in the x direction of FIG. That is, the x direction in FIG. 1 is the arrangement direction of the gate trenches 26. A termination trench 94 is formed in the termination region 92. The termination trench 94 makes a round around the cell region 90. The cell region 90 and the termination region 92 are formed on the same semiconductor substrate. As the semiconductor substrate, a known substrate (for example, a silicon substrate (Si substrate), a silicon carbide substrate (SiC substrate), or the like) can be used.

As shown in FIG. 2, a vertical field effect transistor (MOSFET) is formed on the semiconductor substrate 11. A gate trench 26 is formed on the upper surface of the semiconductor substrate 11. The gate trench 26 penetrates the source region 24 and the body region 20 described later, and its lower end extends to the drift region 16. A gate electrode 30 is formed in the gate trench 26. The gate electrode 30 is formed so that the lower end of the gate electrode 30 is slightly deeper than the lower surface of the body region 20. An insulator 28 is filled between the wall surface of the gate trench 26 and the gate electrode 30 (that is, laterally and below the gate electrode 30). For this reason, the gate electrode 30 faces the body region 20 and the source region 24 with the insulator 28 interposed therebetween. A cap insulating film 32 is formed on the gate electrode 30.

In a region facing the upper surface of the semiconductor substrate 11, an n ⁺ type source region 24 and a p ⁺ type body contact region 22 are formed. The source region 24 is formed in contact with the insulator 28. Body contact region 22 is formed in contact with source region 24.

A p ⁻ -type body region 20 is formed below the source region 24 and the body contact region 22. The impurity concentration in the body region 20 is set lower than the impurity concentration in the body contact region 22. The impurity concentration of the body region 20 can be, for example, 0.5 to 5.0 × e ¹⁷ cm ⁻³ . The body region 20 is in contact with the source region 24 and the body contact region 22, and is in contact with the insulator 28 below the source region 24. For this reason, the source region 24 is surrounded by the body region 20 and the body contact region 22.

An n ⁻ type drift region 16 is formed below the body region 20. The impurity concentration of the drift region 16 can be set to, for example, 1.0 × e ¹⁵ to 1.0 × e ¹⁷ cm ⁻³ . The drift region 16 is in contact with the lower surface of the body region 20. The drift region 16 is separated from the source region 24 by the body region 20.

A p ⁻ -type diffusion region 18 is formed in the drift region 16 in a range surrounding the bottom of the gate trench 26. The diffusion region 18 is in contact with the insulator 28 below the gate electrode 30 (that is, at the bottom of the gate trench 26). The periphery of the diffusion region 18 is surrounded by the drift region 16. Thereby, the diffusion region 18 is separated from the body region 20. The impurity concentration and size of the diffusion region 18 will be described in detail later.

An n ⁺ type drain region 14 is formed in a region facing the lower surface of the semiconductor substrate 11. The impurity concentration of the drain region 14 can be set to 1.0 × e ¹⁸ to 5.0 × e ¹⁹ cm ⁻³ , for example. The drain region 14 is in contact with the lower surface of the drift region 20. The drain region 14 is separated from the body region 20 by the drift region 16.

A drain electrode 12 is formed on the lower surface of the semiconductor substrate 11. The drain electrode 12 is in ohmic contact with the drain region 14. A source electrode 34 is formed on the upper surface of the semiconductor substrate 11. The source electrode 34 is formed so as to cover the cap insulating film 32 and is insulated from the gate electrode 30. The source electrode 34 is in ohmic contact with the source region 24 and the body contact region 22.

When the semiconductor device 10 described above is used, the drain electrode 12 is connected to the power supply potential, and the source electrode 34 is connected to the ground potential. When the potential of the gate electrode 30 is less than the threshold potential, the semiconductor device 11 is off. When the potential of the gate electrode 30 becomes equal to or higher than the threshold potential, the semiconductor device 11 is turned on. That is, a channel is formed in the body region 20 in a range in contact with the gate insulator 28. As a result, electrons flow from the source electrode 34 to the drain electrode 12 through the source region 24, the channel of the body region 20, the drift region 16, and the drain region 14. That is, a current flows from the drain electrode 12 to the source electrode 34.

Next, the impurity concentration and dimensions of the diffusion region 18 will be described. The impurity concentration and size of the diffusion region 18 are adjusted so that breakdown occurs at the pn junction between the diffusion region 18 and the drift region 16 when the semiconductor device 10 is subjected to an avalanche operation. That is, in the semiconductor device in which the diffusion region in the floating state is formed below the gate trench as in this embodiment, the depletion layer is formed at the pn junction between the body region and the drift region and the pn junction between the diffusion region and the drift region. And the breakdown voltage between the drain and source is secured. For this reason, when the avalanche operation is performed on the semiconductor device 10, breakdown occurs in any one of the pn junction between the body region and the drift region and the pn junction between the diffusion region and the drift region. In this embodiment, by adjusting the impurity concentration and size of the diffusion region 18, breakdown occurs at the pn junction between the diffusion region 18 and the drift region 16 during the avalanche operation.

One method for causing breakdown at the pn junction between the diffusion region 18 and the drift region 16 during the avalanche operation is to make the impurity concentration of the diffusion region 18 higher than the impurity concentration of the body region 20. In this case, the dimensions (such as the width in the x direction) of the diffusion region 18 can be appropriately determined in consideration of other characteristics (breakdown voltage, on-resistance, etc.) required for the semiconductor device 10. For example, the p-type impurity concentration of the body region 20 is 1.0 to 4.0 × e ¹⁶ cm ^−3, and the p-type impurity concentration of the diffusion region 18 is 1.5 to 4.5 × e higher than this. ¹⁷ cm ⁻³ . Thereby, breakdown can be caused at the pn junction between the diffusion region 18 and the drift region 16 during the avalanche operation.

The diffusion region 18 and the body region 20 described above can be formed by a known method. For example, it can be formed by implanting p-type impurities into the semiconductor substrate 11 and thermally diffusing the implanted p-type impurities. At this time, the impurity concentration and size of the diffusion region 18 and the body region 20 can be controlled by adjusting the amount of the p-type impurity to be implanted and the thermal diffusion time.
When the diffusion region 18 and the body region 20 are formed by such a method, the impurity concentration in the diffusion region 18 is not constant, and the impurity concentration in the body region 20 is not constant. That is, as shown in FIG. 3, the impurity concentration in the diffusion region 18 has a peak value P ₁ (maximum value) at the center thereof, and decreases as it approaches the boundary with the drift region 16. On the other hand, the impurity concentration in the body region 20 changes in the depth direction as shown in FIG. 5, and reaches a peak value P ₂ (maximum value) at the depth z ₂ . In FIG. 5, the range with a depth of 0 to z ₁ corresponds to the body contact region 22, and the range with a depth of z ₁ to z ₃ corresponds to the body region 20.

In such a case, the peak value P ₁ of the impurity concentration of the diffusion region 18 and the peak value P ₂ of the impurity concentration of the body region 20 are, for example, (P ₁ / P ₂ ) of 1.1 to 10 The range can be adjusted. By setting the peak value ratio (P ₁ / P ₂ ) in the range of 1.1 to 10, a stable breakdown can be achieved at the pn junction between the diffusion region 18 and the drift region 16 during the avalanche operation.

As another method for causing breakdown at the pn junction between the diffusion region 18 and the drift region 16 during the avalanche operation, the dimension of the diffusion region 18 is made larger than that of the conventional method. Specifically, the width of the diffusion region 18 in the x direction (gate trench arrangement direction) is made longer than the conventional one. That is, when the width of the diffusion region 18 in the x direction is changed, the breakdown voltage of the semiconductor device 10 changes. As shown in FIG. 4, when the width of the diffusion region 18 in the x direction is d ₁ , the breakdown voltage of the semiconductor device 10 reaches the maximum value V _max , and when the width of the diffusion region 18 in the x direction exceeds d ₁ , The breakdown voltage of the semiconductor device 10 decreases. In the present embodiment, by making the width of the diffusion region 18 in the x direction longer than d ₁ , the pn junction between the diffusion region 18 and the drift region 16 can be suitably broken down.

The width of the diffusion region 18 in the x direction is set such that adjacent diffusion regions 18 do not contact each other. This is to ensure a space for the carrier to move when the semiconductor device 10 is turned on. Further, as shown in FIG. 4, the width in the x-direction diffusion region 18 exceeds d _1, the breakdown voltage of the semiconductor device 10 is lowered, the ON resistance of the semiconductor device 10 increases. For this reason, it is preferable that the width of the diffusion region 18 in the x direction is not more than “d ₂ ” shown in FIG. This “d ₂ ” is a width when the breakdown voltage of the semiconductor device 10 is 0.8 × V _max . By making the width of the diffusion region 18 in the x direction equal to or less than d ₂ , the breakdown voltage of the semiconductor device 10 and the increase in on-resistance are suppressed while the breakdown region is the pn junction between the diffusion region 18 and the drift region 16. can do. Therefore, it is preferable to determine the width of the diffusion region 18 in the x direction within the range of d ₁ to d ₂ . These d ₁ and d ₂ may be determined by experiment or may be determined by calculation using a device simulator.

When the width of the diffusion region 18 in the x direction is longer than d1, the p-type impurity concentration of the diffusion region 18 can be appropriately determined in consideration of other characteristics required for the semiconductor device 10. Of course, the p-type impurity concentration of the diffusion region 18 may be higher than the p-type impurity concentration of the body region 20. By doing so, breakdown can be more stably performed at the pn junction between the diffusion region 18 and the drift region 16 during the avalanche operation.

Next, the operation of the semiconductor device 10 when performing the avalanche test will be described. The avalanche test can be performed by a known method. That is, the drain electrode 12 of the semiconductor device 10 is connected to the power supply potential via the coil. Further, the source electrode 34 of the semiconductor device 10 is connected to the ground potential. In this state, a pulse voltage is applied to the gate electrode 30. When a pulse voltage is applied to the gate electrode, the semiconductor device 10 is turned on for a predetermined time and then turned off. When the semiconductor device 10 is turned on, a current flows through the semiconductor device 10 and energy is accumulated in the coil. When the semiconductor device 10 is turned off, a large counter electromotive force is generated in the coil due to the energy accumulated in the coil. When the back electromotive force generated in the coil acts on the semiconductor device 10, the semiconductor device 10 performs an avalanche operation.

When the semiconductor device 10 performs an avalanche operation, breakdown occurs at the pn junction between the diffusion region 18 and the drift region 16. When breakdown occurs at the pn junction between the diffusion region 18 and the drift region 16, most of the holes generated by the breakdown flow as indicated by arrows in FIG. 2 and flow to the source electrode 34 through the body region 20 and the body contact region 22. . For this reason, the holes generated by the breakdown are suppressed from being collected in the vicinity of the gate electrode 30, and the accumulation of holes in the insulator 28 in the vicinity of the gate electrode 30 is suppressed.

In the conventional semiconductor device, breakdown occurs at the pn junction between the body region 20 and the drift region 16. For this reason, breakdown occurs in the vicinity of the gate electrode 30, so that more holes gather near the gate electrode 30. As a result, a large amount of holes are accumulated in the insulator 28 (location indicated by reference numeral 36 in FIG. 2) in the vicinity of the gate electrode 30.

As is clear from the above, in the semiconductor device 10 of this embodiment, when an avalanche operation is performed, the collection of holes in the vicinity of the gate electrode 30 is suppressed, and the holes in the insulator 28 in the vicinity of the gate electrode 30 are suppressed. Is suppressed from being accumulated. For this reason, an increase in gate capacitance can be suppressed, and deterioration of characteristics (such as switching characteristics) of the semiconductor device 10 due to an avalanche operation can be suppressed. In addition, since accumulation of holes in the insulator 28 is suppressed as described above, deterioration in characteristics of the semiconductor device 10 can be effectively suppressed even when a continuous avalanche test is performed.

Second Embodiment A semiconductor device 40 according to a second embodiment will be described with reference to FIG. In FIG. 6, the same parts as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals as those of the first embodiment.

As shown in FIG. 6, in the semiconductor device 40 of the second embodiment, the n ⁻ type drift region 42 has a low concentration drift region 42a having a low impurity concentration and a high concentration having a higher impurity concentration than the low concentration drift region 42a. The difference from the first embodiment is that a drift region 42b is provided. The low concentration drift region 42 a is formed in the vicinity of the side wall surface of the gate trench 26 in the gate trench arrangement direction (that is, the x direction). The high concentration drift region 42b is formed in an intermediate portion of the adjacent gate trench 26 (between adjacent low concentration drift regions 42a). Since the low concentration drift region 42a has a lower impurity concentration than the high concentration drift region 42b, the electric resistance is higher than that of the high concentration drift region 42b.

In this semiconductor device 40, a low-concentration drift region 42a having a high resistance is formed in the vicinity of the side wall surface of the gate trench 26, and a low-concentration drift region 42b having a low electrical resistance is formed at a position away from the gate trench 26. For this reason, holes generated by breakdown at the pn junction between the diffusion region 18 and the drift region 16 are unlikely to flow through the low concentration drift region 42a and easily flow through the high concentration drift region 42b. As a result, the collection of holes in the vicinity of the gate electrode 30 can be further suppressed.

Here, an example of a method for forming the low concentration drift region 42a will be described. As shown in FIG. 7, in this formation method, the trench 44 (which then becomes the gate trench 26) is formed in a tapered shape. Next, a p-type impurity is implanted into the bottom of the trench 44 in order to form the diffusion region 18 at the bottom of the trench 44. At this time, the acceleration voltage of the p-type impurity to be implanted is set high. Since the trench 44 is formed in a tapered shape, a small amount of p-type impurity is also implanted into the side wall surface of the trench 44. As a result, the impurity concentration of the drift region 42 in the vicinity of the side wall surface of the trench 44 is reduced, and the low concentration drift region 42a is formed. In this method, since the trench 44 (gate trench 26) only needs to be tapered, the low concentration drift region 42a can be easily formed.

In the semiconductor device 40 shown in FIG. 6, the low concentration drift region 42 a is formed in the entire depth range from the body region 20 to the diffusion region 18, but the technique of this specification is in such a form. Not limited. A low concentration drift region may be formed in at least a part of the depth range from the body region 20 to the diffusion region 18.

Third Embodiment A semiconductor device 50 according to a third embodiment will be described with reference to FIG. Also in FIG. 8, the same parts as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals as those of the first embodiment.

The semiconductor device 50 of the third embodiment differs from the first embodiment in that a shielding region 52a is formed at a depth between the body region 20 and the diffusion region 18. The shielding region 52 a is formed of an insulating material and is integrated with the insulator 28 filled in the gate trench 26. The shielding region 52 a extends in the x direction from the side wall surface of the gate trench 26 and protrudes into the drift region 16.

In this semiconductor device 50, a shielding region 52a protruding in the x direction from the side wall surface of the gate trench 26 is formed. For this reason, the holes generated by the breakdown at the pn junction between the diffusion region 18 and the drift region 16 are prevented from moving toward the gate electrode 30 by the shielding region 52a. As a result, the collection of holes in the vicinity of the gate electrode 30 can be effectively suppressed.

Incidentally, the projecting length L ₁ from the gate trench side wall of the shielding region 52a may be appropriately determined according to the size of the property deterioration due to the avalanche operation. If the characteristics degradation due to avalanche behavior is small, it is preferably smaller than the projection length L ₂ from the gate trench side wall surface of the diffusion region 18. With this configuration, when the semiconductor device 50 is turned on, it is possible to secure a large space for current to flow to the side of the gate trench 26, and to suppress an increase in the on-resistance of the semiconductor device 50. it can. On the other hand, when the characteristic degradation due to avalanche behavior is large, it may be larger than the projection length L ₂ of the diffusion region 18 of the protruding length L ₁ of the shielding region 52a. As a result, deterioration of the characteristics of the semiconductor device 50 can be effectively suppressed.

Here, an example of a method for forming the shielding region 52a will be described. As shown in FIG. 9, first, a trench 62 is formed by dry etching the semiconductor substrate 60. Next, after forming a thin oxide film (insulator) (not shown) on the wall surface of the trench 62, a p-type impurity is implanted into the bottom of the trench 62 to form a diffusion region 64 at the bottom of the trench 62 (FIG. 10). reference). Next, an oxide film 66 is filled in the gate trench 62 by CVD (Chemical Vapor Deposition) (see FIG. 11). Next, the semiconductor substrate 60 is dry-etched to form an opening 68 for forming a shielding region (see FIG. 12). Next, the oxide film 70 is filled in the opening 68 by the CVD method (see FIG. 13). Next, the oxide film 70 is removed by etching, leaving the portion 72 to be a shielding region (see FIG. 14). Next, the semiconductor layer 74 is epitaxially grown in the opening 68 (see FIG. 15). Next, the semiconductor layer 74 is dry-etched to form a trench 76 (a portion that becomes the gate trench 26) (see FIG. 16). Next, after an insulator 76 is formed on the wall surface of the trench 76, a gate material 80 (polysilicon film) is buried. As a result, it is possible to form a shielding region that protrudes from the sidewall surface of the gate trench into the drift region.

Although the first to third embodiments have been described in detail above, the technology described in this specification is not limited to the above-described embodiments. For example, each of the embodiments described above is an example in which a MOSFET is formed on a semiconductor substrate, but the technique described in this specification can also be applied to other semiconductor devices such as an IGBT.

Further, the technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. For example, the technique of the second embodiment (a technique of forming a low concentration drift region in the vicinity of the gate trench side wall surface) can be used alone. That is, even when breakdown occurs at the pn junction between the body region and the drift region during avalanche operation, holes are collected in the vicinity of the gate electrode by forming the low concentration drift region in the vicinity of the gate trench sidewall surface. Can be suppressed.

Claims (6)

A drift region of a first conductivity type;
A second conductivity type body region provided on the surface side of the drift region;
A gate trench extending through the body region to the drift region;
A gate electrode disposed in the gate trench and facing the body region;
An insulator disposed between the gate electrode and the wall surface of the gate trench;
A second conductivity type diffusion region surrounding the bottom of the gate trench and surrounded by a drift region;
A semiconductor device in which the impurity concentration in the diffusion region is higher than the impurity concentration in the body region. A plurality of gate trenches are arranged in a certain direction at intervals,
Inside each gate trench, a gate electrode and an insulator are arranged,
The semiconductor device according to claim 1, wherein a diffusion region of a second conductivity type is provided at a bottom portion of each gate trench so as to surround the bottom portion. The width of the diffusion region in the gate trench arrangement direction is longer than the width when the breakdown voltage of the semiconductor device is maximized when the width of the diffusion region is changed, and adjacent diffusion regions are in contact with each other. The semiconductor device according to claim 2, wherein the width of the semiconductor device is shorter than the width at the time of occurrence. 4. The semiconductor device according to claim 2, wherein in the drift region, an impurity concentration in the vicinity of the side wall surface in the gate trench arrangement direction of the gate trench is lower than an impurity concentration in an intermediate portion between adjacent gate trenches. 3. A shielding region is further provided between the body region and the diffusion region, which projects into the drift region from a side wall surface in the gate trench arrangement direction of the gate trench and shields a carrier flow from the diffusion region toward the gate electrode. 5. The semiconductor device according to any one of items 1 to 4. A drift region of a first conductivity type;
A second conductivity type body region provided on the surface side of the drift region;
A gate trench extending through the body region to the drift region;
A gate electrode disposed in the gate trench and facing the body region;
An insulator disposed between the gate electrode and the wall surface of the gate trench;
A second conductivity type diffusion region surrounding the bottom of the gate trench and surrounded by a drift region;
A semiconductor device in which the impurity concentration and size of a diffusion region are adjusted so that breakdown occurs at a pn junction between the diffusion region and the drift region during an avalanche operation.

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