KR102330787B1 - SiC Trench Gate MOSFET Device and Manufacturing Method thereof - Google Patents

Abstract

The present invention relates to a trench gate-type SiC MOSFET device and a method for manufacturing the same, comprising: a gate oxide film covering a gate trench formed in a SiC substrate (eg, an n-type 4H-SiC substrate); In a gate trench region, a doped well (eg, BPW) formed under the gate oxide layer, a gate electrode formed inside the gate trench covered with the gate oxide layer, an interlayer insulating layer formed over the gate electrode, and the entire surface of the epitaxial layer of the substrate and a source electrode covering an upper surface of a doping layer for the formed source region and an upper surface of the interlayer insulating layer, and a drain electrode formed on a rear surface of the substrate.

Description

TECHNICAL FIELD [0001] A trench gate type SOC device and a manufacturing method thereof TECHNICAL FIELD

The present invention relates to a trench gate-type SiC MOSFET device, and more particularly, to a trench-gate-type SiC MOSFET device _{subjected to H 2} heat treatment and a sacrificial oxidation process (SOP) process after forming a gate oxide film, and a method for manufacturing the same.

SiC is being applied to MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices due to its excellent properties such as low intrinsic carrier concentration, high dielectric breakdown, high thermal conductivity and high electron flow rate. In particular, the use of SiC as a power device for realizing a high withstand voltage is being studied, and a trench gate structure MOSFET is mainly used for miniaturization of the device and reduction of on-resistance.

When the conventional trench gate MOSFET is turned off, a high potential difference is induced between the gate electrode located in the trench and the drain electrode under the epitaxial layer. As a result, the electric field is concentrated at the bottom of the gate trench, and dielectric breakdown due to the concentration of the electric field occurs at the bottom of the gate oxide layer. Due to this problem, attempts have been made to reduce the concentration of an electric field by making the thickness of the bottom of the gate oxide film larger than the thickness of the side. However, in the case of the thermal oxidation method, since the side portion exhibits a higher oxidation tendency than the bottom portion, when the oxidation time is increased to increase the thickness of the bottom portion, the thickness of the side gate oxide film becomes very thick.

In order to solve this problem, a method of forming a trench gate oxide film having a thick bottom portion by applying a blanket SiO2 film deposition, etch back, thermal oxidation method, etc. after formation of the gate trench is known, but with a simpler process There is a demand for a MOSFET device having a stable gate oxide film.

Accordingly, the present invention has been devised to solve the above problems, and an object of the present invention is a trench gate type having a high quality and stable gate oxide film by performing _{H 2 heat treatment and a sacrificial oxidation process (SOP) process after forming the gate oxide film.} To provide a SiC MOSFET device and a method for manufacturing the same.

First, to summarize the features of the present invention, a trench gate type SiC MOSFET device according to one aspect of the present invention for achieving the above object includes: a gate oxide film covering a gate trench formed in a SiC substrate (eg, 4H-SiC substrate); a doped well formed under the gate oxide layer in the gate trench region; a gate electrode formed inside the gate trench covered with the gate oxide layer; an interlayer insulating film formed on the gate electrode; a source electrode covering an upper surface of a doping layer for a source region formed on the entire surface of the epitaxial layer of the substrate and an upper surface of the interlayer insulating film; and a drain electrode formed on the rear surface of the substrate.

The gate oxide layer may be manufactured by heat-treating it in an _{H 2} atmosphere before forming the gate electrode.

Before the formation of the gate electrode, a carbon capping layer is formed on the gate oxide layer and the carbon capping layer is removed after heat treatment in an Ar atmosphere, and then the gate oxide layer is heat treated in an _{H 2 atmosphere.}

Before the formation of the gate electrode, it may be manufactured by including a sacrificial oxidation process (SOP) process in which dry oxidation is performed at 800 to 1200° C. for 30 to 50 minutes.

_{When the gate oxide film is heat-treated in an H 2} atmosphere before the formation of the gate electrode, the carbon compound generated at the SiC interface by the heat treatment is oxidized or removed by the SOP process.

Before the formation of the gate electrode, a TEOS oxide film may be formed on the gate oxide film and heat-treated in an NO atmosphere.

The doped layer of the source region formed on the entire surface of the epitaxial layer of the substrate may include doped layers on left and right sides of the gate electrode.

When the substrate is a substrate having an N-type epitaxial layer, the doped layer of the source region may include an n+ layer and a p+ layer adjacent to each other side by side on a p-base layer to the left and right of the gate electrode.

And, in the method of manufacturing a trench gate type SiC MOSFET device according to another aspect of the present invention, a SiC substrate having a doped layer for a source region (eg, a 4H-SiC substrate) is etched deeper than the doped layer of the source region. forming a gate trench; forming a gate oxide film; ion implantation to form a doped well under the gate oxide layer in the gate trench region; heat-treating; forming a gate electrode in the gate trench; forming an interlayer insulating film on the substrate on which the gate electrode is formed; patterning the gate oxide layer and the interlayer insulating layer; forming a source electrode covering an upper surface of a doping layer for a source region formed on the entire surface of the epitaxial layer of the substrate and an upper surface of the interlayer insulating film; and forming a drain electrode on the rear surface of the substrate.

The heat treatment may include heat treatment in _{H 2 atmosphere.}

Before the heat treatment, the method may further include forming a carbon capping layer on the gate oxide layer and removing the carbon capping layer after heat treatment in an Ar atmosphere.

Before forming the gate electrode, the method may include performing a sacrificial oxidation process (SOP) process of dry oxidation at 800 to 1200° C. for 30 to 50 minutes.

The manufacturing method of the trench gate type SiC MOSFET device is characterized in that the carbon compound generated at the SiC interface by the heat treatment in an _{H 2 atmosphere is oxidized or removed by the SOP process.}

The carbon compound forms a leaky interfacial layer in the trench gate type SiC MOSFET device to generate a reverse leakage current, and may reduce the reverse leakage current by the SOP process.

The carbon compound includes a graphitic carbon layer.

Before forming the gate electrode, the method may further include forming a TEOS oxide film on the gate oxide film and heat-treating it in an NO atmosphere.

The doped layer of the source region formed on the entire surface of the epitaxial layer of the substrate may include doped layers on left and right sides of the gate electrode.

When the substrate is a substrate having an N-type epitaxial layer, the doped layer of the source region may include an n+ layer and a p+ layer adjacent to each other side by side on a p-base layer to the left and right of the gate electrode.

The trench gate type SiC MOSFET device according to the present invention can provide a trench gate type SiC MOSFET device having a high quality and stable gate oxide film by performing _{H 2 heat treatment and a sacrificial oxidation process (SOP) process after forming a gate oxide film.} Utilizing excellent properties such as low intrinsic carrier concentration in SiC, high dielectric breakdown characteristics, high thermal conductivity and electron mobility, and low on-resistance, the trench-gate SiC MOSFET device of the present invention can achieve miniaturization of the device, that is, miniaturization of cell pitch. and can operate as a power device for realizing high withstand voltage.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included as part of the detailed description to help the understanding of the present invention, provide embodiments of the present invention and, together with the detailed description, explain the technical spirit of the present invention.
1 is a view for explaining the structure of a trench gate type SiC MOSFET device of the present invention.
2 is an example of an SEM photograph of the cross-sectional structure of the trench gate type SiC MOSFET device of the present invention.
3 is a view for explaining a method of manufacturing a trench gate type SiC MOSFET device of the present invention.
4 is an example of the SEM photograph of the trench shape before (a) and after (b) _{H 2} heat treatment in the trench gate type SiC MOSFET device of the present invention.
5 is an example of reverse current characteristics (a) and breakdown voltage characteristics (b) in reverse bias in the case where SOP processing is performed and when not in the trench gate type SiC MOSFET device of the present invention.
6 is a photograph showing the results of transmission microscopy according to whether SOP treatment is performed in the trench gate type SiC MOSFET device of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In this case, the same components in each drawing are denoted by the same reference numerals as much as possible. In addition, detailed descriptions of already known functions and/or configurations will be omitted. The content disclosed below will focus on parts necessary for understanding operations according to various embodiments, and descriptions of elements that may obscure the gist of the description will be omitted. Also, some components in the drawings may be exaggerated, omitted, or schematically illustrated. The size of each component does not fully reflect the actual size, so the contents described herein are not limited by the relative size or spacing of the components drawn in each drawing.

In describing the embodiments of the present invention, if it is determined that a detailed description of a known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, the terms to be described later are terms defined in consideration of functions in the present invention, which may vary according to intentions or customs of users and operators. Therefore, the definition should be made based on the content throughout this specification. The terminology used in the detailed description is for the purpose of describing embodiments of the present invention only, and should not be limiting in any way. Unless explicitly used otherwise, expressions in the singular include the meaning of the plural. In this description, expressions such as “comprising” or “comprising” are intended to indicate certain features, numbers, steps, acts, elements, some or a combination thereof, one or more other than those described. It should not be construed to exclude the presence or possibility of other features, numbers, steps, acts, elements, or any part or combination thereof.

In addition, terms such as first and second may be used to describe various components, but the components are not limited by the terms, and the terms are for the purpose of distinguishing one component from other components. used only as

1 is a view for explaining the structure of a trench gate type SiC MOSFET device 1000 of the present invention. 2 is an example of an SEM photograph of the cross-sectional structure of the trench gate type SiC MOSFET device 1000 of the present invention.

1 and 2, in the trench gate type SiC MOSFET device 1000 of the present invention, a gate trench formed in a substrate (eg, an n-type 4H-SiC substrate) 200 having an epitaxial layer 222 ( The gate oxide film 240 covering the 230 , a doped well (eg, BPW, bottom p-well) 225 formed under the gate oxide film 240 in the region of the gate trench 230 , and the gate oxide film 240 are covered The gate electrode 250 formed inside the gate trench 230 , the interlayer insulating film 260 formed on the gate electrode 250 , and doped layers 224 and 226 for the source region formed on the entire surface of the epitaxial layer of the SiC substrate 200 . , 228 , a source electrode 270 covering the top surface of the interlayer insulating film 260 , and a drain electrode 280 formed on the rear surface of the SiC substrate 200 .

The source region formed on the entire surface of the epitaxial layer 222 of the SiC substrate 200 includes doped layers 224 , 226 , and 228 to the left and right of the gate electrode 250 .

When the SiC substrate 200 is a substrate having an n-type epitaxial layer 222 as shown in the figure, the doped layers 224, 226, and 228 of the source region are a p-base layer 224, which is a lightly doped p-type layer. An n+ layer 228, which is a heavily doped n-type doped layer, and a p+ layer 226, which is a heavily doped p-type, includes adjacent layers side by side.

Hereinafter, a method of manufacturing the trench gate type SiC MOSFET device 1000 of the present invention will be described in detail with reference to FIG. 3 .

3 is a view for explaining a method of manufacturing the trench gate type SiC MOSFET device 1000 of the present invention.

First, referring to FIG. 3, for example, a substrate 210 (e.g., 6 inch n-type 4 ^o off-axis <0001> oriented 4H-SiC substrate) on the n-type (for example, 7 x 10 ¹⁵ cm ^{- Doping at a concentration of 3} ) to form an epitaxial layer 222, prepare a substrate 200 on which doping layers 224, 226, 228 for a source region are formed on the entire surface of the epitaxial layer 222 (S110) ). When the substrate 200 is a substrate having an n-type epitaxial layer as shown in the figure, the doped layers 224, 226, and 228 of the source region are heavily n-type doped on the p-base layer 224, which is a lightly doped p-type layer. An n+ layer 228 as a layer and a p+ layer 226 as a heavily p-type doped layer include adjacent layers side by side. For example, the p-base layer 224 and the p+ layer 226 may be formed by implanting Al ions, and the n+ layer 228 may be formed by implanting N (nitrogen) ions.

Next, the gate trench 230 is formed by etching deeper than the doped layers 224 , 226 , and 228 of the source region ( S120 ). _{For example, SiO 2} deposited by plasma-enhanced chemical vapor deposition (PECVD) equipment is patterned for a region corresponding to the region where the gate electrode 250 is to be formed and used as an etch mask, inductively coupled plasma (ICP, A trench (eg, a trench depth of about 2 μm) may be formed through a dry etcher using inductive coupled plasma). As an example, a trench cell pitch of 6.5 μm was formed in the active area 5×5 mm ^{2 .}

Next, a gate oxide film 240 is formed (S130). _{For example, the insulating layer SiO 2} may be formed to a thickness of 50 to 110 nm in the entire region including the sidewalls and the bottom of the gate trench. In one embodiment, the thickness of the gate oxide film on the trench sidewalls was about 80 nm.

A doped well (eg, BPW) 225 is formed under the gate oxide layer 240 in the region of the gate trench 230 by, for example, implanting Al ions ( S140 ).

After forming the doped well (e.g., BPW) 225, a carbon capping layer is formed on the gate oxide film 240 and in an Ar atmosphere at 1500 to 1900 °C (e.g. 1700 °C) for 50 to 70 minutes (e.g. , 60 min) after heat treatment, the carbon capping layer _{may be removed by O 2} plasma ashing (S150).

After heat treatment in Ar atmosphere, then, to control the shape of the gate trench 230 and smooth the sidewalls of the gate trench 230, H ₂ heat treatment in the atmosphere (S160).

Also, before forming the gate electrode 250 , a sacrificial oxidation process (SOP) process is performed. For example, dry oxidation may be performed on the gate trench 230 at 800 to 1200° C. (eg, 1000° C.) for 30 to 50 minutes (eg, 40 minutes). Samples not treated with SOP are also prepared for comparison.

After the sacrificial oxidation process (SOP) treatment is performed, a tetra ethoxysilane (TEOS) gate oxide film is formed by, for example, 720 ° C. by LPCVD (Low Pressure Chemical Vapor Deposition) equipment, and post-oxidation heat treatment in an NO atmosphere, that is, The nitriding heat treatment may be performed at 800 to 1200° C. (eg, 1175° C.) for 60 to 180 minutes (eg, 120 minutes). Samples not treated with SOP are also prepared for comparison.

Next, the gate electrode 250 is formed of a conductive material such as metal or polycrystalline Si in the gate trench 230 ( S180 ). For example, the gate electrode 250 may be formed by depositing n-type polycrystalline Si doped at a high concentration using CVD equipment or the like and then patterning it. The upper surface of the gate electrode 250 is preferably formed to be flush with the surfaces of the doped layers 224 , 226 , and 228 of the epitaxial layer 222 .

Next, an interlayer dielectric 260 is formed on the substrate on which the gate electrode 250 is formed ( S190 ). The interlayer insulating film 260 may be formed of an insulating film such as _{SiO 2 .}

Next, the gate oxide layer 240 and the interlayer insulating layer 260 may be simultaneously patterned through an exposure operation using a single mask ( S200 ).

Next, the source electrode 270 is formed of a conductive material (eg, Ti) such as metal (S210). For example, the source electrode 270 covering the upper surface of the doping layers 224 , 226 , 228 for the source region formed on the entire surface of the epitaxial layer 222 of the substrate 200 and the upper surface of the interlayer insulating film 260 . to form

Next, a drain electrode 280 is formed on the rear surface of the substrate 200 using a conductive material such as metal (eg, Ni/Ti alloy) (S220).

Here, it goes without saying that the ohmic layer may be formed before the source electrode 270 and the drain electrode 280 are formed.

Finally, the input/output pad metal connected to each of the gate electrode 250 , the source electrode 270 , and the drain electrode 280 may be made of Al.

4 is an example of an SEM photograph of a trench shape before (a) and after (b) _{H 2} heat treatment in the trench gate-type SiC MOSFET device 1000 of the present invention.

Figure 4 (a) is an example of the SEM photograph before the formation of the gate oxide film 240 and H ₂ heat treatment, and Figure 4 (b) is an example of the SEM photograph after the _{formation of the gate oxide film 240 and the H 2 heat treatment.} After the H ₂ heat treatment, the upper and lower corners of the trench 230 are rounded, and it can be seen that the surface of the sidewall of the trench 230 becomes smoother.

5 is an example of reverse current characteristics (a) and breakdown voltage characteristics (b) in reverse bias in the case where SOP processing is performed and when not in the trench gate type SiC MOSFET device 1000 of the present invention.

As shown in (a) of FIG. 5 , it is shown that the trench MOSFET without SOP treatment has a reverse leakage current that is 3 times higher at the gate reverse bias than the MOSFET with the SOP treatment. It is expected that the interfacial layer of the MOSFET without the SOP treatment reacts at the gate oxide layer 240 and the SiC interface to form a carbon compound (such as a graphitic carbon layer) during _{the H 2 heat treatment process that may chemically modify the surface layer.} Therefore, it is assumed that carbon compounds are oxidized and removed during SOP treatment. The breakdown voltage of the MOSFET with and without SOP treatment was measured between 800 and 900V, as shown in FIG. 5(b). It can be seen that the treatment of the SOP has no significant effect on the breakdown voltage characteristic.

6 is a photograph showing the results of transmission microscopy according to whether SOP treatment is performed in the trench gate type SiC MOSFET device of the present invention.

Referring to FIG. 6 , it can be confirmed by TEM that the reverse leakage current characteristics are improved through the SOP (Sacrificial Production Process) treatment. In the case of the device without the SOP process, it shows that a thick interfacial layer is observed at the gate oxide layer interface. This interfacial layer was judged to be a layer formed during the process of the gate oxide film after hydrogen heat treatment, and was expected to be a leaky interfacial layer. According to previously reported results (Y. Kawada et al., Jpn. J. appl. Phys. 48 (2009), p.116508), a carbon layer can be formed on the SiC surface during heat treatment in an Ar atmosphere at 1700 °C. As a cause, it has been reported that Si sublimes on the high-temperature SiC surface and the remaining carbon forms a graphitic carbon layer (graphitic carbon layer). Similarly, when the sacrificial oxidation process was performed, the graphitic carbon layer remaining on the SiC surface was effectively removed. It can be seen that a high leakage current is generated through the interfacial layer containing high graphitic carbon.

As described above, the trench gate-type SiC MOSFET device 1000 according to the present invention is a trench gate-type SiC MOSFET device having a high-quality and stable gate oxide film by performing _{H 2 heat treatment and SOP process after forming the gate oxide film 240 .} can provide Utilizing excellent characteristics such as low intrinsic carrier concentration in SiC, high dielectric breakdown characteristics, high thermal conductivity and electron mobility, and low on-resistance, the trench gate type SiC MOSFET device 1000 is a device for miniaturization, that is, a smaller cell pitch. and can operate as a power device for realizing high withstand voltage.

As described above, the present invention has been described with specific matters such as specific components and limited embodiments and drawings, but these are only provided to help a more general understanding of the present invention, and the present invention is not limited to the above embodiments. , various modifications and variations will be possible without departing from the essential characteristics of the present invention by those of ordinary skill in the art to which the present invention pertains. Therefore, the spirit of the present invention should not be limited to the described embodiments, and all technical ideas with equivalent or equivalent modifications to the claims as well as the claims to be described later are included in the scope of the present invention. should be interpreted as

substrate 210
Substrate 200 on which an epitaxial layer is formed
Gate Trench (230)
gate oxide film 240
Wells (eg BPW) (225)
gate electrode 250
Interlayer insulating film (260)
source electrode 270
drain electrode 280
p-base layer 224
n + layer (228)
p + layer (226)

Claims (20)

delete delete delete delete delete delete delete delete delete etching the SiC substrate having a doped layer for the source region deeper than the doped layer for the source region to form a gate trench;
forming a gate oxide film;
ion implantation to form a doped well under the gate oxide layer in the gate trench region;
heat-treating;
performing a sacrificial oxidation process (SOP) process for performing dry oxidation at 800 to 1200° C. for 30 to 50 minutes;
forming a gate electrode in the gate trench;
forming an interlayer insulating film on the substrate on which the gate electrode is formed;
patterning the gate oxide layer and the interlayer insulating layer;
forming a source electrode covering an upper surface of a doping layer for a source region formed on the entire surface of the epitaxial layer of the substrate and an upper surface of the interlayer insulating film; and
forming a drain electrode on the rear surface of the substrate
A method of manufacturing a trench gate-type SiC MOSFET device comprising a. 11. The method of claim 10,
In the heat treatment, the method of manufacturing a trench gate-type SiC MOSFET device, characterized in that heat treatment in an _{H 2 atmosphere.} 11. The method of claim 10,
Before the heat treatment step,
forming a carbon capping layer on the gate oxide layer and removing the carbon capping layer after heat treatment in an Ar atmosphere
Method of manufacturing a trench gate type SiC MOSFET device further comprising a. delete 11. The method of claim 10,
A method of manufacturing a trench gate-type SiC MOSFET device, characterized in that the carbon compound generated at the SiC interface by the heat treatment in the _{H 2 atmosphere is oxidized or removed by the SOP process.} 15. The method of claim 14,
The carbon compound forms a leaky interfacial layer in the trench gate SiC MOSFET device to generate a reverse leakage current, and reduces the reverse leakage current by the SOP process. manufacturing method. 15. The method of claim 14,
The method of manufacturing a trench gate type SiC MOSFET device, characterized in that the carbon compound comprises a graphitic carbon layer. 11. The method of claim 10,
Before forming the gate electrode,
forming a TEOS oxide film on the gate oxide film and heat-treating it in an NO atmosphere
Method of manufacturing a trench gate type SiC MOSFET device further comprising a. 11. The method of claim 10,
The method of manufacturing a trench gate type SiC MOSFET device, characterized in that the substrate is a 4H-SiC substrate. 11. The method of claim 10,
The method for manufacturing a trench gate type SiC MOSFET device, wherein the doped layer of the source region formed on the entire surface of the epitaxial layer of the substrate includes doped layers on the left and right sides of the gate electrode. 11. The method of claim 10,
When the substrate is a substrate having an N-type epitaxial layer, the doped layer of the source region comprises an n+ layer and a p+ layer adjacent to each other side by side on the p-base layer to the left and right of the gate electrode. A method of fabricating a trench gate-type SiC MOSFET device.

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