JP2016213374A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve all three characteristics of a MOS, formed by forming a trench gate electrode on a SiC substrate, whose on-resistance is high, voltage-withstanding is low, and a saturation current is high.SOLUTION: A swollen part is formed near a bottom surface of a trench to fill an embedded insulator film. Stress is applied to a SiC crystal of a portion to be a channel to reduce on-resistance. A distance between neighboring swollen parts becomes short to make it possible to suppress a saturation current low. Owing to the presence of the embedded insulator film, electric field concentration generated in a drift area is relaxed to improve the voltage-withstanding.SELECTED DRAWING: Figure 1

Description

The present specification discloses a vertical semiconductor device that uses a SiC substrate and has a resistance value between a front electrode and a back electrode that varies depending on the potential of a trench gate electrode. For example, a MOS is disclosed in which the resistance value between the source electrode formed on the surface of the SiC substrate and the drain electrode formed on the back surface varies depending on the potential applied to the trench gate electrode.
In this specification, a device in which electrodes are formed on both the front and back surfaces of a semiconductor substrate, and the resistance value between the front electrode and the back electrode changes depending on the potential of the trench gate electrode is referred to as a vertical semiconductor device.

  A trench penetrating a body layer (also referred to as a base layer) formed in the SiC substrate is formed, a gate electrode is formed in the trench, and a potential is applied to the trench gate electrode to thereby form a trench gate electrode. Patent Document 1 discloses a vertical semiconductor device in which a channel is formed at a facing position and a resistance value between a front electrode and a back electrode is changed depending on the presence or absence of the channel.

JP 2014-53595 A JP 2014-135366 A

The following problems remain in the vertical semiconductor device using the SiC substrate and the trench gate electrode.
(1) The on-resistance needs to be reduced. For this purpose, it is necessary to improve carrier mobility in the channel.
(2) The breakdown voltage of the element needs to be improved. When the voltage applied between the front electrode and the back electrode exceeds a predetermined value, a phenomenon occurs in which a current continues to flow between the front electrode and the back electrode even when an off voltage is applied to the trench gate electrode. It is necessary to increase the maximum voltage between the front surface electrode and the back surface electrode, in which the current between the front surface electrode and the back surface electrode can be controlled by the potential of the trench gate electrode.
(3) It is necessary to reduce the saturation current. The current flowing between the front electrode and the back electrode increases as the voltage between the front electrode and the back electrode increases, but when the voltage exceeds a predetermined value, the current value increases further. Phenomenon that does not. That is, a phenomenon occurs in which the current value is saturated. If the saturation current is low, for example, the value of the current that flows at the time of a short-circuit failure can be reduced, and a long time allowed for the abnormality processing can be secured.

  Conventionally, various techniques for improving the above have been developed. For example, in the technique of Patent Document 2, SiC crystals having different lattice intervals are used in a region where a channel is formed and other regions. According to this, distortion occurs in a region where a channel is formed, carrier mobility is improved, and on-resistance is lowered.

The technique of Patent Document 2 can cope with the problem (1) described above. However, the problems (2) and (3) remain unsolved. The current technology cannot cope with all of (1), (2), and (3).
The present specification discloses a vertical semiconductor device that can cope with all of the above (1), (2), and (3).

  The vertical semiconductor device disclosed in this specification uses a SiC substrate, and a surface-side n-type region, a p-type region, and a deep-side n-type region are stacked from the surface of the SiC substrate toward the deep portion. A trench that penetrates the surface side n-type region and the p-type region and reaches the deep-side n-type region is formed. A trench bulge that bulges laterally is formed in a range near the bottom of the trench and within the deep n-type region. The trench bulge is filled with an insulating material. On the surface side of the trench bulge, the trench gate electrode formed in the trench is opposed to the p-side region through a sidewall insulating film formed along the sidewall of the trench.

According to the semiconductor device, the following event is obtained.
(1) An insulating material filled in the trench bulge exists below the region where the channel is formed. SiC that forms a channel formation region due to the insulating material is distorted, electron mobility in the channel is improved, and on-resistance is reduced.
(2) The withstand voltage is defined mainly by the occurrence of electric field concentration in the deep n-type region facing the vicinity of the boundary between the bottom and side walls of the trench. According to this structure, since the insulating material filled in the trench bulge exists between the bottom surface and the side wall of the trench, the electric field concentration is relaxed and the breakdown voltage is improved.
(3) When the trench bulge portion is formed, the distance between adjacent trench bulge portions is shorter than the distance between the side walls of adjacent trench vertical portions. That is, the width of the deep n-type region through which the current passes becomes narrow. When the width becomes narrow, the saturation current decreases.
According to this structure, a vertical semiconductor device with low on-resistance, high breakdown voltage, and low saturation current can be obtained.

  This structure is a useful technique for IGBTs and the like, but exhibits a remarkable effect when applied to a MOS. That is, the front-side n-type region is a source region, the p-type region is a body region, the deep-side n-type region is a drift region, and an n-type drain region is formed in a range in contact with the back surface of the SiC substrate. If it is, a remarkable effect is obtained.

1 is a cross-sectional view of a vertical semiconductor device of Example 1. FIG. FIG. 3 is a cross-sectional view of a substrate obtained by epitaxially growing a SiC single crystal serving as a drift region 6 and a SiC single crystal serving as a body region 10 on an original substrate serving as a drain region 4. FIG. 3 is a cross-sectional view of a substrate in which a body contact region 14 and a source region 16 are formed by ion implantation from the surface of the substrate of FIG. 2. FIG. 5 is a cross-sectional view of a substrate in which a trench vertical portion 20b that reaches the drift region 6 through the source region 16 and the body region 10 is formed. Sectional drawing of the board | substrate of the state which formed the protective film in the wall surface of a trench vertical part, and removed the protective film formed in the bottom face of a trench vertical part. FIG. 6 is a cross-sectional view of the substrate after isotropic etching of the substrate of FIG. 5. Sectional drawing of the board | substrate after filling an insulating material into a trench. Sectional drawing of the board | substrate of the state which etched the insulating material and left the insulating material in the trench bulge part. Sectional drawing of the board | substrate of the state which formed the side wall insulating film in the side wall of a trench vertical part. Sectional drawing of the board | substrate of the state which filled the conductor into the trench vertical part. Sectional drawing of the board | substrate of the state which removed the conductor outside a trench. Sectional drawing of the board | substrate of the state in which the interlayer insulation film was formed. FIG. 6 is a characteristic diagram of the semiconductor device of Example 1; Sectional drawing of the vertical semiconductor device of Example 2. FIG.

The features of the technology disclosed in this specification will be summarized below. The items described below have technical usefulness independently.
(Feature 1) The gate insulating film is made of SiO ₂ .
(Feature 2) A trench bulge is formed by isotropic etching from the bottom of the vertical part of the trench.

FIG. 1 shows a cross-sectional structure of a vertical MOS that uses a SiC substrate. FIG. 1 shows two cells, and FIGS. 2 to 12 show only one cell. In an actual apparatus, the structure of FIG. 1 appears repeatedly in the left-right direction.
In FIG. 1, reference numeral 32 indicates a SiC substrate. The source electrode 18 is formed on the surface of the SiC substrate 32, and the drain electrode 2 is formed on the back surface.
An n-type source region 16, a p-type body region 10, an n-type drift region 6, and an n-type drain region 4 are stacked in this order from the surface side of the SiC substrate 32. A body contact region 14 is formed between adjacent source regions 16 and 16.
A trench reaching the drift region 6 through the source region 16 and the body region 10 is formed from the surface of the SiC substrate 32. The trench is formed by a trench vertical portion 20b extending in the vertical direction and a trench bulging portion 20a that bulges left and right from the vicinity of the bottom surface thereof. The trench vertical portion 20 b reaches the drift region 6, and the trench bulge portion 20 a remains in the drift region 6.
The trench bulging portion 20a is filled with an insulating material. The insulating material filling the trench bulging portion 20a is referred to as a buried insulating film 8a. A sidewall insulating film 8b is formed on the sidewall of the trench vertical portion 20b. A conductive trench gate electrode 12 is filled between the sidewall insulating film 8b and the sidewall insulating film 8b of the trench vertical portion 20b. An interlayer insulating film 8 c is formed on the upper surface of the trench gate electrode 12. The trench gate electrode 12 is insulated from the source electrode 18 by the interlayer insulating film 8c, and is insulated from the source region 16, the body region 10, and the drift region 6 by the sidewall insulating film 8b.

The source electrode 18 and the source region 16 are in ohmic contact. The source electrode 18 and the body contact region 14 are also in ohmic contact. The drain electrode 2 and the drain region 4 are also in ohmic contact.
The impurity concentration of the body region 10 is low, and when a positive voltage is applied to the trench gate electrode 12, the body region 10 at a position facing the trench gate electrode 12 through the sidewall insulating film 8b is inverted to n-type. The inverted region is called a channel. When an n-type channel is formed between the n-type source region 16 and the n-type drift region 6, the resistance between the source electrode 18 and the drain electrode 2 decreases.

  In the vertical MOS of FIG. 1, due to the presence of the buried insulating film 8a, (1) the body region 10 located at the position facing the trench gate electrode 12 through the sidewall insulating film 8b is distorted, and the mobility of electrons High, low on-resistance, (2) high breakdown voltage due to the presence of the buried insulating film 8a, (3) the width L1 of the drift region 6 existing between the neighboring buried insulating films 8a, 8a is narrow, and the saturation current is It has the characteristic of being low.

(Production method)
The manufacturing method will be described below. FIG. 2 shows an epitaxial growth of an n-type SiC single crystal serving as a drift region 6 on an original substrate 4 serving as a crystal growth, and an epitaxial growth of a p-type SiC single crystal serving as a body region 10 or the like thereon. Indicates the stage. The original substrate 4 becomes the drain region 4.

  Ions are implanted from the surface of the substrate of FIG. 2 to manufacture the source region 16 and the body contact region 14 (FIG. 3).

A protective film 22 having an opening 22a is formed on the surface of the substrate, and the SiC substrate is anisotropically etched from the opening 22a to form a trench vertical portion 20b that reaches the drift region 6 through the source region 16 and the body region 10. (FIG. 4).
A protective film 24 is formed on the inner surface (side surface and bottom surface) of the trench vertical portion 20b. Next, the protective film 24 is etched. At this time, an etching condition is employed in which the protective film 24 formed on the side surface remains and the protective film formed on the bottom surface is removed. The side wall of the trench vertical portion 20b is covered with the protective film 24, and a state where SiC is exposed on the bottom surface of the trench vertical portion 20b is obtained (FIG. 5).
Next, the SiC substrate is isotropically etched using an etchant that etches SiC without etching the protective film 24. As a result of the isotropic etching, the SiC substrate is also etched to the side, etched to the front side, and etched to the back side. As a result, a trench bulge 20a is formed (FIG. 6).

Next, the trench 20 is filled with an insulating material. An insulator deposition layer 26 is formed (FIG. 7).
Next, the insulating deposit 26 is etched to remove the insulating material in the trench vertical portion 20b (FIG. 8). At this stage, the buried insulating film 8a is formed.
Next, a sidewall insulating film 8b is formed on the sidewall of the trench vertical portion 20b (FIG. 9).
Next, a conductive substance is filled in the trench vertical portion 20b. A conductor deposition layer 28 is formed.
Next, the conductor deposition layer 28 is etched to remove the conductor outside the trench vertical portion 20b (FIG. 11).
Next, an interlayer insulating film 8c is formed (FIG. 12).
Thereafter, when the source electrode 18 and the drain electrode 2 are formed, the vertical MOS shown in FIG. 1 can be manufactured.

Actually, heat treatment is performed in the state of FIG. 7, and the contact interface between the buried insulating film 8a and the drift region 6 shown in FIG. During this heat treatment, distortion occurs in the SiC crystal forming the side wall of the trench vertical portion 20b. When the SiC crystal is distorted, the electron mobility is improved. According to the semiconductor device of FIG. 1, a phenomenon that the on-resistance is lowered is obtained by the presence of the buried insulating film 8a. (2) in FIG. 13 shows the relationship between the voltage and current between the source and drain in the normal region of the semiconductor device, graph A shows the case where there is no buried insulating film 8a, and graph B shows that the buried insulating film 8a is provided. The case characteristics are shown. In the apparatus of FIG. 1, the distance L1 between the adjacent buried insulating films 8a and 8a is shorter than the distance L2 between the adjacent trench vertical portions 20b and 20b. The current path is narrowed, which increases the on-resistance. In the apparatus shown in FIG. 1, the elements that increase the on-resistance due to the narrowed current path by the buried insulating film 8a and the elements that cause the channel to be distorted by the buried insulating film 8a and lower the on-resistance cancel each other. Is almost the same. While the current path is narrowed by the buried insulating film 8a, the on-resistance is prevented from increasing.
In the drift region 6, electric field concentration is likely to occur at a position facing the bottom surface of the trench gate electrode 12, which determines the breakdown voltage. In the semiconductor device of FIG. 1, a thick buried insulating film 8a is formed below the bottom surface of the trench gate electrode 12 from the intersection with one side surface to the intersection with the other side surface, that is, on the entire bottom surface. Electric field concentration in the drift region 6 is alleviated. The semiconductor device in FIG. 1 has a high breakdown voltage.
Further, in the apparatus of FIG. 1, the distance L1 between the adjacent buried insulating films 8a and 8a is shorter than the distance L2 between the adjacent trench vertical portions 20b and 20b. The saturation current flowing through the semiconductor device is exclusively defined by the width of the current path in the drift region 6. Since the distance L1 is regulated to be equal to or less than the distance L2, the saturation current flowing through the semiconductor device in FIG. 1 can be kept low. (1) in FIG. 13 shows the magnitude of the saturation current. Graph A shows the saturation current when there is no buried insulating film 8a, and graph B shows the saturation current when the buried insulating film 8a is provided. By adding the buried insulating film 8a, the saturation current can be kept low. When the saturation current is kept low, it is possible to ensure a long time allowed for processing to be performed when an abnormal phenomenon in which the saturation current flows occurs.

(Second embodiment)
FIG. 14 shows a second embodiment. Only differences from the first embodiment will be described. In the semiconductor device of the second embodiment, a p-type region 30 is formed below the buried insulating film 8a. The p-type region 30 is surrounded by the buried insulating film 8a and the n-type drift region 6, and is in a floating state. When the p-type floating region 30 is added, the breakdown voltage of the semiconductor device is further improved.

  When the semiconductor device of FIG. 14 is manufactured, when the state of FIG. 6 is obtained, p-type impurities are implanted from the trench vertical portion 20b toward the bottom surface of the trench bulge portion 20b. At this time, an oblique injection technique is used. Impurities are implanted in a range wider than the cross section of the vertical portion 20b. By subsequently performing heat treatment, the p-type floating region 30 having a cross section wider than that of the vertical portion 20b can be formed.

(Modification)
When the buried insulating film 8b is formed, a layer containing n-type impurities at a high concentration can be introduced between the body region 10 and the drift region 6 to further reduce the on-resistance. When the buried insulating film 8b is not used, since a breakdown voltage is lowered when a layer containing n-type impurities at a high concentration is introduced, a layer containing n-type impurities at a high concentration cannot be introduced. The use of the buried insulating film 8b can cope with the problem.

  In the process shown in FIG. 5, that is, when the protective film 24 is formed on the side surface and the bottom surface of the trench vertical portion 20b, heat treatment under the condition that the SiC crystal exposed on the sidewall of the trench becomes graphene can be employed. When several layers of graphene are formed on the sidewall of the trench, the carrier mobility in the channel can be further increased, and the on-resistance can be further reduced.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, the n-type impurity concentration in the range in contact with the body region 10 on the upper surface of the drift region 6 may be increased. When the n-type impurity concentration in the above region is increased, the on-resistance is lowered and the breakdown voltage is also lowered, and the on-resistance is lowered by increasing the n-type impurity concentration in the above region. I could not. According to the present technology, since the breakdown voltage can be prevented from being lowered by using the embedded insulating film 8a, a necessary breakdown voltage can be secured even if the n-type impurity concentration in the region is increased. The on-resistance can be lowered while ensuring the breakdown voltage.
It is also effective to form graphene in the channel region. When graphene is formed, carrier mobility is improved and on-resistance can be further reduced.
It is also effective to form a film obtained by epitaxially growing a single crystal such as SiC or Si in the channel region (position in contact with the sidewall insulating film 8b). This can also reduce the on-resistance.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: Drain electrode 4: Drain region (SiC original substrate)
6: drift region 8: gate insulating film 8a: buried insulating film 8b: sidewall insulating film 8c: interlayer insulating film 10: body region 12: gate electrode 14: body contact region 16: source region 18: source electrode 20: trench 20a: Trench bulging portion 20b: trench vertical portion 22: first protective film 22a: opening 24: second protective film 26: insulating material deposition layer 28: conductor deposition layer 30: p-type floating region 32: SiC substrate

Claims (2)

A vertical semiconductor device using a SiC substrate,
A surface-side n-type region, a p-type region, and a deep-side n-type region are stacked from the surface of the SiC substrate toward the deep portion,
A trench is formed that penetrates the surface-side n-type region and the p-type region to reach the deep-side n-type region;
A trench bulge that bulges laterally is formed in a range near the bottom of the trench and within the deep n-type region.
The trench bulge is filled with an insulating material,
A semiconductor device in which a trench gate electrode formed in the trench is opposed to the p-side region through a side wall insulating film formed along a side wall of the trench on the surface side of the trench bulge portion . The semiconductor device according to claim 1, wherein the surface-side n-type region is a source region, and an n-type drain region is formed in a range in contact with the back surface of the SiC substrate.

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