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WO2004095552A3 - Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur - Google Patents

Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur Download PDF

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Publication number
WO2004095552A3
WO2004095552A3 PCT/DE2004/000736 DE2004000736W WO2004095552A3 WO 2004095552 A3 WO2004095552 A3 WO 2004095552A3 DE 2004000736 W DE2004000736 W DE 2004000736W WO 2004095552 A3 WO2004095552 A3 WO 2004095552A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
tensioned
producing
substrate
layer structure
Prior art date
Application number
PCT/DE2004/000736
Other languages
English (en)
French (fr)
Other versions
WO2004095552A2 (de
Inventor
Siegfried Mantl
Original Assignee
Forschungszentrum Juelich Gmbh
Siegfried Mantl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forschungszentrum Juelich Gmbh, Siegfried Mantl filed Critical Forschungszentrum Juelich Gmbh
Priority to EP04726422A priority Critical patent/EP1616345A2/de
Priority to JP2006504293A priority patent/JP5259954B2/ja
Priority to US10/554,074 priority patent/US7615471B2/en
Publication of WO2004095552A2 publication Critical patent/WO2004095552A2/de
Publication of WO2004095552A3 publication Critical patent/WO2004095552A3/de
Priority to US12/496,676 priority patent/US7915148B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

Die Erfindung betrifft ein Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat mit den Schritten: Erzeugung eines Defektbereichs in einem zu der zu verspannenden Schicht benachbarten Schicht; Relaxation mindestens einer zu der zu verspannenden Schicht benachbarten Schicht. Es können epitaktisch weitere Schichten angeordnet werden. Derartig gebildete Schichtstrukturen sind vorteilhaft geeignet für verschiedenartigste Bauelemente.
PCT/DE2004/000736 2003-04-22 2004-04-08 Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur WO2004095552A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP04726422A EP1616345A2 (de) 2003-04-22 2004-04-08 Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur
JP2006504293A JP5259954B2 (ja) 2003-04-22 2004-04-08 基板上に歪層を製造する方法と層構造
US10/554,074 US7615471B2 (en) 2003-04-22 2004-04-08 Method for producing a tensioned layer on a substrate, and a layer structure
US12/496,676 US7915148B2 (en) 2003-04-22 2009-07-02 Method of producing a tensioned layer on a substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10318283A DE10318283A1 (de) 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
DE10318283.7 2003-04-22

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US10554074 A-371-Of-International 2004-04-08
US12/496,676 Continuation US7915148B2 (en) 2003-04-22 2009-07-02 Method of producing a tensioned layer on a substrate

Publications (2)

Publication Number Publication Date
WO2004095552A2 WO2004095552A2 (de) 2004-11-04
WO2004095552A3 true WO2004095552A3 (de) 2004-12-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2004/000736 WO2004095552A2 (de) 2003-04-22 2004-04-08 Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur

Country Status (5)

Country Link
US (2) US7615471B2 (de)
EP (1) EP1616345A2 (de)
JP (1) JP5259954B2 (de)
DE (1) DE10318283A1 (de)
WO (1) WO2004095552A2 (de)

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DE102004048096A1 (de) * 2004-09-30 2006-04-27 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7202124B2 (en) * 2004-10-01 2007-04-10 Massachusetts Institute Of Technology Strained gettering layers for semiconductor processes
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US8361889B2 (en) * 2010-07-06 2013-01-29 International Business Machines Corporation Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator
US8822306B2 (en) 2010-09-30 2014-09-02 Infineon Technologies Ag Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core
US8404562B2 (en) 2010-09-30 2013-03-26 Infineon Technologies Ag Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core
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EP2741320B1 (de) * 2012-12-05 2020-06-17 IMEC vzw Herstellungsverfahren einer finfet-vorrichtung mit zwei verspannten kanälen
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US9269714B2 (en) * 2013-06-10 2016-02-23 Globalfoundries Inc. Device including a transistor having a stressed channel region and method for the formation thereof
FR3041146B1 (fr) * 2015-09-11 2018-03-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de mise en tension d'un film semi-conducteur
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FR3050569B1 (fr) * 2016-04-26 2018-04-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Fabrication amelioree de silicium contraint en tension sur isolant par amorphisation puis recristallisation
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Also Published As

Publication number Publication date
US7615471B2 (en) 2009-11-10
JP2006524426A (ja) 2006-10-26
DE10318283A1 (de) 2004-11-25
WO2004095552A2 (de) 2004-11-04
US20060220127A1 (en) 2006-10-05
US20090298301A1 (en) 2009-12-03
US7915148B2 (en) 2011-03-29
JP5259954B2 (ja) 2013-08-07
EP1616345A2 (de) 2006-01-18

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