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WO2000019511A1 - Depot d'une couche d'oxyde sur la grille - Google Patents

Depot d'une couche d'oxyde sur la grille Download PDF

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Publication number
WO2000019511A1
WO2000019511A1 PCT/US1999/022603 US9922603W WO0019511A1 WO 2000019511 A1 WO2000019511 A1 WO 2000019511A1 US 9922603 W US9922603 W US 9922603W WO 0019511 A1 WO0019511 A1 WO 0019511A1
Authority
WO
WIPO (PCT)
Prior art keywords
depositing
gate
recited
oxide layer
active regions
Prior art date
Application number
PCT/US1999/022603
Other languages
English (en)
Inventor
Toru Ishigaki
Original Assignee
Advanced Micro Devices, Inc.
Fujitsu Limited
Fujitsu Amd Semiconductor Limited (Fasl)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc., Fujitsu Limited, Fujitsu Amd Semiconductor Limited (Fasl) filed Critical Advanced Micro Devices, Inc.
Priority to EP99952987A priority Critical patent/EP1125323A1/fr
Priority to JP2000572920A priority patent/JP2002526921A/ja
Priority to KR1020017003971A priority patent/KR20010088817A/ko
Publication of WO2000019511A1 publication Critical patent/WO2000019511A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates

Definitions

  • the invention relates generally to a method of providing an oxide layer to protect a gate of the semiconductor device during implantation of the active regions, and more particularly to a method of depositing the oxide layer to prevent undesired oxidation of the gate.
  • Figures 1A-1C illustrate a conventional method of protecting the gate of the semiconductor device with an oxide layer during implantation of the active regions.
  • the gate illustrated in Figures 1A-1C is of a stacked type and includes a first polysilicon gate or floating gate 21 and a second polysilicon gate or control gate 22.
  • the first gate 21 is separated from a semiconductor substrate 10 by a first gate oxide layer 11 and from the second gate by a second gate oxide layer 12.
  • the gate oxide layers 11, 12 typically have a thickness of about 100 A.
  • the first and second gates 21, 22 are patterned on a semiconductor substrate 10 by a conventional process that includes the steps of depositing photoresist, exposing the photoresist through a mask containing the desired gate pattern, developing the photoresist, etching/ and removing the developed photoresist ( Figure 1A) .
  • the semiconductor device then undergoes heating in an oxygen atmosphere at a temperature range of 800-1200 QC .
  • the heating achieves two goals. First, a silicon oxide (Si0 2 ) layer 30 is thermally grown on the top and sides of the gate to protect the gate against implantation damage. Second, etching damage is eliminated. For example, electron traps that are undesirably formed in the gate oxides to cause shifts in the threshold voltages are annealed out.
  • Figure IB Figure 1C illustrates the next step. In Figure 1C, ions are implanted into the active regions 23, 24 or are used to form the active regions 23, 24.
  • the oxide layer 30 protects the top and sides of the gate against implantation damage during this step.
  • a gate bird's beak is formed at the edges of the polysilicon gates 21, 22 during the heating step.
  • the effect of the gate bird's beak is illustrated in Figures IB and 1C as rounded edges of the polysilicon gates 21, 22.
  • the gate bird's beak is formed because some of the silicon in the polysilicon gates 21, 22 is consumed by reaction with oxygen in the atmosphere in forming the thermally grown oxide layer 30.
  • the gate bird's beak is disadvantageous because it shortens the effective channel length of the gate.
  • An object of this invention is to provide an oxide layer to protect the sides and top of a gate of a semiconductor device during implantation of active regions of the semiconductor device without forming a gate bird's beak at the edges of the gate .
  • the above and other objects of the invention are accomplished by depositing an oxide layer of a thickness of approximately 100-300 A on top and sides of a gate and active regions of a semiconductor device prior to the step of implanting the active regions.
  • the deposition is carried out by low pressure chemical vapor deposition (LPCVD) at a temperature between 750-900 QC, which is high enough to eliminate any damage caused by etching of the gate pattern.
  • the deposited oxide layer is preferably a layer of Si0 2 but may be a layer of tetraethyl orthosilicate (TEOS) .
  • TEOS tetraethyl orthosilicate
  • Another advantage of the invention is that a consistent conformal layer of oxide can be formed by depositing the oxide layer above the gate and the active regions. By comparison, a thermally grown oxide layer is less conformal than a deposited oxide layer . Additional objects, features and advantages of the invention will be set forth in the description of preferred embodiments which follows.
  • Figures 1A-1C illustrate a conventional process for implanting active regions of a semiconductor device
  • Figures 2A-2C illustrate a process of implanting active regions of a semiconductor device in accordance with the invention.
  • Figures 2A-2C illustrate a method of providing an oxide layer to protect the gate of the semiconductor device during implantation of the active regions or during formation of the active regions in accordance with the invention.
  • the gate illustrated in Figures 2A-2C is of a stacked type and includes a first polysilicon gate or floating gate 21 and a second polysilicon gate or control gate 22.
  • the first gate 21 is separated from a semiconductor substrate 10 by a first gate oxide layer 11 and from the second gate by a second gate oxide layer 12.
  • the gate oxide layers 11, 12 typically have a thickness of about 100 A.
  • the first and second gates 21, 22 are patterned on a semiconductor substrate 10 by a conventional process that includes the steps of depositing photoresist, exposing the photoresist through a mask containing the desired gate pattern, developing the photoresist, etching, and removing the developed photoresist (Figure 2A) .
  • an oxide layer 31 is deposited on the structure illustrated in Figure 2A to a thickness of about 100-300 A.
  • the deposition is carried out at a high temperature between 750-900 ⁇ c, preferably between 800-850 FJC .
  • the temperature range of 750-900 QC is sufficiently high to eliminate any damage caused by etching of the gate pattern.
  • the deposition of the oxide layer 31 is carried out by chemical vapor deposition (CVD) , preferably low-pressure chemical vapor deposition (LPCVD) .
  • the oxide layer 31 is preferably a layer of Si0 2 , but may be a layer of TEOS . By depositing the oxide, several advantages are attained.
  • thermal growth is suppressed because the rate of LPCVD is much faster than thermal growth and the gate is not exposed to the atmosphere for a time period that is sufficiently long for thermal growth. Consequently, the formation of the gate bird's beak is prevented and the polysilicon gates 21, 22 retain their etched profile as illustrated in Figure 2B .
  • Figure 2C illustrates the next step.
  • ions are implanted into the active regions 23, 24 or are used to form the active regions 23, 24.
  • the oxide layer 30 protects the top and sides of the gate against implantation damage during this step.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne le dépôt d'une couche d'oxyde, suivant une épaisseur d'environ 100 à 300 Å, sur une grille et sur les zones actives d'un composant à semiconducteur, avant l'implantation des zones actives. On réalise le dépôt à une température comprise entre 750 et 900 °C, soit une fourchette suffisamment élevée pour éviter les dégâts causés par l'attaque du motif de la grille. De cette façon, on supprime la formation du bec d'oiseau de la grille, parce que le silicium présent dans la grille n'est pas consommé durant l'opération de dépôt.
PCT/US1999/022603 1998-09-29 1999-09-28 Depot d'une couche d'oxyde sur la grille WO2000019511A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP99952987A EP1125323A1 (fr) 1998-09-29 1999-09-28 Depot d'une couche d'oxyde sur la grille
JP2000572920A JP2002526921A (ja) 1998-09-29 1999-09-28 ゲートへの酸化膜堆積方法
KR1020017003971A KR20010088817A (ko) 1998-09-29 1999-09-28 게이트 위에 산화막층의 증착

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16315598A 1998-09-29 1998-09-29
US09/163,155 1998-09-29

Publications (1)

Publication Number Publication Date
WO2000019511A1 true WO2000019511A1 (fr) 2000-04-06

Family

ID=22588726

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/022603 WO2000019511A1 (fr) 1998-09-29 1999-09-28 Depot d'une couche d'oxyde sur la grille

Country Status (5)

Country Link
EP (1) EP1125323A1 (fr)
JP (1) JP2002526921A (fr)
KR (1) KR20010088817A (fr)
TW (1) TW466604B (fr)
WO (1) WO2000019511A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002080247A1 (fr) * 2001-03-28 2002-10-10 Advanced Micro Devices, Inc. Pellicules sacrificielles conferant une integrite sacrificielle a des structures de dimensions critiques
US6566886B1 (en) 2001-03-28 2003-05-20 Advanced Micro Devices, Inc. Method of detecting crystalline defects using sound waves

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0446893A1 (fr) * 1990-03-13 1991-09-18 Kabushiki Kaisha Toshiba Procédé de fabrication des dispositifs semi-conducteurs ayant des grilles flottantes
US5208174A (en) * 1990-07-05 1993-05-04 Kabushiki Kaisha Toshiba Method for manufacturing a nonvolatile semiconductor memory device
EP0561271A2 (fr) * 1992-03-17 1993-09-22 Hitachi, Ltd. Mémoire flash, divisée en blocs, dont les lignes de données sont sans perturbation, et micro-ordinateur comprenant mémoire flash
JPH08186184A (ja) * 1994-12-29 1996-07-16 Nippon Steel Corp 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0446893A1 (fr) * 1990-03-13 1991-09-18 Kabushiki Kaisha Toshiba Procédé de fabrication des dispositifs semi-conducteurs ayant des grilles flottantes
US5208174A (en) * 1990-07-05 1993-05-04 Kabushiki Kaisha Toshiba Method for manufacturing a nonvolatile semiconductor memory device
EP0561271A2 (fr) * 1992-03-17 1993-09-22 Hitachi, Ltd. Mémoire flash, divisée en blocs, dont les lignes de données sont sans perturbation, et micro-ordinateur comprenant mémoire flash
JPH08186184A (ja) * 1994-12-29 1996-07-16 Nippon Steel Corp 半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 11 29 November 1996 (1996-11-29) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002080247A1 (fr) * 2001-03-28 2002-10-10 Advanced Micro Devices, Inc. Pellicules sacrificielles conferant une integrite sacrificielle a des structures de dimensions critiques
US6566886B1 (en) 2001-03-28 2003-05-20 Advanced Micro Devices, Inc. Method of detecting crystalline defects using sound waves

Also Published As

Publication number Publication date
EP1125323A1 (fr) 2001-08-22
JP2002526921A (ja) 2002-08-20
KR20010088817A (ko) 2001-09-28
TW466604B (en) 2001-12-01

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