TWM599059U - Voltage level shifter having output buffer circuit - Google Patents

Abstract

This creation proposes a potential converter with an output buffer circuit, which is composed of an input circuit (1), a latch circuit (2) and an output buffer circuit (3), wherein the input circuit (1) ) Is used to provide a differential input signal; the latch circuit (2) is used to save the differential input signal from the input circuit (1); and the output buffer circuit (3) is used to suppress the output potential competition And output the second signal (V(OUT)).

The potential converter with output buffer circuit proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device, and it is also effective The ground suppresses the competition between the pull-up path and the pull-down path, thereby reducing power loss.

Description

Potential converter with output buffer circuit

This creation proposes a potential converter with an output buffer circuit, especially one composed of an input circuit (1), a latch circuit (2) and an output buffer circuit (3), in order to obtain accurate voltage level conversion At the same time, it can effectively reduce the power loss of the electronic circuit.

A potential converter is an electronic circuit used to communicate signals between different integrated circuits (IC). In many applications, when the application system needs to transmit signals from the core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential converter is responsible for converting the low-voltage working signal into a high-voltage working signal.

Figure 1 shows another prior art mirror-type potential converter circuit by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) Together and connected to the drain of the first PMOS transistor (MP1), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is in the The saturation region and its gate voltage make the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high power supply voltage (VDDH) changes, the potential The performance of the converter will not be too Big change. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

Figure 2 shows a latch-type potential converter circuit of the prior art, which uses a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a first NMOS transistor (MN1) , A second NMOS transistor (MN2) and an inverter (INV) to form a potential converter circuit, where the bias voltage of the inverter (INV) is the second high power supply voltage (VDDL) and ground (GND), and the potential of the first signal (V(IN)) is also between the ground (GND) and the second high power supply voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output through the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on (ON). In addition, due to the cross-coupled method of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential converter is in a stable state, the latch type No static current is generated in the potential converter. In particular, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so as to pull up the gate potential of the second PMOS transistor (MP2) and turn off the second PMOS transistor (MP2); furthermore, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the second PMOS The gate potential of the transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the gate potential of the first PMOS transistor (MP1) is pulled up to turn off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) is close to turning on (or off) and the second NMOS transistor (MN2) is close to turning off (or on), the output terminal There is a contention phenomenon between the pull-up and pull-down of the potential on the (OUT), so the second signal (V(OUT)) is slower when it changes to a low potential. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion period may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor (MN1) and the second NMOS transistor (MN2) are completely turned on or completely turned off. This will cause a static current (static) between the first high power supply voltage (VDDH) and ground (GND). current), this quiescent current will increase power loss.

Furthermore, the performance of the latch-type potential converter is affected by the first high power supply voltage (VDDH), due to the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The first high power supply voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) that can make the latch type level converter operate normally is limited. When the second PMOS transistor (MP2) tends to be on (or off) and in When the second NMOS transistor (MN2) is close to turning off (or on), there is a contention phenomenon for the rise and fall of the potential on the output terminal (OUT), so the second signal (V (OUT)) The speed is slow when changing to a low potential.

In view of this, the main purpose of this creation is to propose a potential converter with an output buffer circuit, which can not only accurately and quickly convert the first signal to a second signal, but also effectively reduce the pull-up path and the pull-down path Compete with each other, thereby reducing power loss.

This creation proposes a potential converter with an output buffer circuit, which is composed of an input circuit (1), a latch circuit (2), and an output buffer circuit (3), wherein the input circuit (1) is Used to provide a differential input signal; the latch circuit (2) is used to save the differential input signal from the input circuit (1); and the output buffer circuit (3) is used to suppress the output potential competition and output The second signal (V(OUT)).

The simulation results confirm that the potential converter with output buffer circuit proposed in this creation not only can accurately and quickly convert the first signal to a second signal, but also has a simple circuit structure and is beneficial to the miniaturization of the device. Multiple functions can effectively reduce power loss at the same time.

1: Input circuit

2: Latching circuit

3: Output buffer circuit

GND: ground

I1: First inverter

N1: the first node

N2: second node

N3: third node

MP1: The first PMOS transistor

MP2: second PMOS transistor

MP3: third PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: The third NMOS transistor

MN4: Fourth NMOS transistor

OUT: output terminal

IN: the first input

V(OUT): second signal

INB: second input

V(IN): first signal

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Figure 1 is a circuit diagram showing the potential converter in the first prior art;

Figure 2 is a circuit diagram showing the potential converter in the second prior art;

Figure 3 is a circuit diagram showing a potential converter with an output buffer circuit in a preferred embodiment of the invention;

Figure 4 is a timing diagram showing the transient analysis of the first signal and the second signal of the preferred embodiment of this creation;

According to the above-mentioned purpose, this creation proposes a potential converter with an output buffer circuit, as shown in Figure 3, which consists of an input circuit (1), a latch circuit (2) and an output buffer circuit (3) The input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to store the differential input signal from the input circuit (1); and the output buffer circuit ( 3) It is used to suppress the competition of the output potential and output the second signal (V(OUT)); the input circuit (1) consists of a first NMOS transistor (MN1) and a second NMOS transistor (MN2) And a first inverter (I1), wherein the source of the first NMOS transistor (MN1) is connected to the ground (GND), the gate is connected to the first input (IN), and its The drain is connected to the first node (N1); the source of the second NMOS transistor (MN2) is connected to the ground (GND), the gate is connected to the second input (INB), and the drain is The pole is connected to the second node (N2); the first inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)), and Provide a signal that is inverse to the first signal (V(IN)); the latch circuit (2) is composed of a first PMOS transistor (MP1) and a second PMOS transistor (MP2), wherein , The source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the first node ( N1) is connected; the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the The second node (N2) is connected; the output buffer circuit (3) is composed of a third PMOS transistor (MP3), a third NMOS transistor (MN3) and a fourth NMOS The source of the third PMOS transistor (MP3) is connected to the first high power supply voltage (VDDH), the gate of the third PMOS transistor (MP3) is connected to the first node (N1), and the The drain is connected to the drain of the third NMOS transistor (MN3); the source of the third NMOS transistor (MN3) is connected to the third node (N3), and its gate is connected to the first input Terminal (IN), and its drain is connected to the drain of the third PMOS transistor (MP3); the source of the fourth NMOS transistor (MN4) is connected to ground (GND), and its gate is connected to The second input terminal (INB), and its drain is connected to the third node (N3); the first high power supply voltage (VDDH) is used to provide the potential converter with an output buffer circuit The first high power supply voltage; the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the level converter with an output buffer circuit; the second high power supply voltage (VDDL) The level is less than the level of the first high power supply voltage (VDDH); the first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is between 0 volts and 1.8 volts The corresponding waveform of the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts, and the first signal (V(IN)) is between 0 volts and 1.2 For a rectangular wave between volts, the second signal (V(OUT)) has a corresponding waveform between 0 volt and 1.8 volt.

Please refer to Figure 3 again. Now consider the steady-state operation of a potential converter with an output buffer circuit when the first signal (V(IN)) is at a logic low level (0 volts): on the first input (IN) The logic low level of is simultaneously transmitted to the input terminal of the first inverter (I1), the gate of the first NMOS transistor (MN1) and the third NMOS transistor (MN3), so that the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned off (OFF), and the first inverter (I1) transmits a logic high level (VDDL) to the second NMOS transistor (MN2) and the fourth NMOS transistor The gate of (MN4) makes both the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) turn on (ON). At this time, the first NMOS transistor (MN1) is turned off (OFF). , And the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on (ON), the potential of the second node (N2) and the third node (N3) will be pulled down to one The logic low level (0V), and the logic low level on the second node (N2) is transferred to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned on (ON) At this time, since the first PMOS transistor (MP1) is turned on (ON) and the first NMOS transistor (MN1) is turned off (OFF), the potential of the first node (N1) will be pulled up to a The logic high level of the first node (N1) makes the second PMOS transistor (MP2) and the third PMOS transistor (MP3) both turn off (OFF). At this time, the third PMOS transistor (MP3) and the third NMOS transistor (MN3) are both turned off (OFF), and the fourth NMOS transistor (MN4) is turned on (ON), therefore, the potential of the output terminal (OUT) will be maintained at a logic low level Quasi (0 volt) steady state value. In a nutshell, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) through the potential converter with an output buffer circuit. (OUT) output.

When the first signal (V(IN)) is at the logic high level (VDDL), the steady-state operation of the potential converter with the output buffer circuit: the logic high level on the first input (IN) is simultaneously transmitted to the The input terminal of the first inverter (I1), the gate of the first NMOS transistor (MN1) and the third NMOS transistor (MN3) make the first NMOS transistor (MN1) and the third NMOS transistor The transistors (MN3) are all turned on (ON), and the first inverter (I1) transmits a logic low level to the gates of the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4), so that The second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off (OFF). At this time, since the first NMOS transistor (MN1) is turned on (ON), the second NMOS transistor (MN2) and the The fourth NMOS transistor (MN4) is turned off (OFF), the potential of the first node (N1) will be pulled down to a logic low level (0 volts), and the logic low level of the first node (N1) makes the The second PMOS transistor (MP2) and the third PMOS transistor (MP3) are both turned on (ON). At this time, the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off (OFF). ), the potential of the second node (N2) will be pulled up to a logic high level, and the logic high level on the second node (N2) is transferred to the gate of the first PMOS transistor (MP1), so that The first PMOS transistor (MP1) is turned off (OFF). At this time, because the first PMOS transistor (MP1) is turned off (OFF) and the first NMOS transistor (MN1) is turned on (ON), the first PMOS transistor (MP1) is turned on (ON). The potential of a node (N1) will be maintained at a logic low level. Furthermore, since the third PMOS transistor (MP3) and the third NMOS transistor (MN3) are both turned on (ON), and the fourth NMOS transistor The crystal (MN4) is turned off (OFF), so the potential of the output terminal (OUT) will maintain a steady-state value at a logic high level. In a nutshell, when the first signal (V(IN)) is at a logic high level (VDDL), it is converted into a second signal with the first high power supply voltage (VDDH) by the level converter with the output buffer circuit. Output terminal (OUT) output.

To sum up, when the first signal (V(IN)) is at a logic low level (0 volt), the second signal (V(OUT)) is also at a logic low level (0 volt); and the first signal When (V(IN)) is the logic high level (VDDL), the second signal (V(OUT)) is the first high power supply voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.

The Spice transient analysis simulation results of the potential converter with output buffer circuit proposed in this creation are shown in Figure 4. The simulation results can confirm that the potential converter with output buffer circuit proposed in this creation has Not only can the first signal be converted into a second signal quickly and accurately, but also the competition between the pull-up path and the pull-down path of the output terminal (OUT) can be effectively reduced, thereby reducing power loss.

Although this creation specifically discloses and describes the selected best embodiment, anyone familiar with the technology can understand that any possible changes in form or details do not depart from the spirit and scope of this creation. Therefore, all changes within the scope of related technologies are included in the scope of patent application for this creation.

1: Input circuit

2: Latching circuit

3: Output buffer circuit

GND: ground

I1: First inverter

N1: the first node

N2: second node

N3: third node

MP1: The first PMOS transistor

MP2: second PMOS transistor

MP3: third PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: The third NMOS transistor

MN4: Fourth NMOS transistor

OUT: output terminal

IN: the first input

V(OUT): second signal

INB: second input

V(IN): first signal

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Claims (7)

A potential converter with an output buffer circuit for converting a first signal (V(IN)) into a second signal (V(OUT)), which includes: A first node (N1) for connecting the drain of a first PMOS transistor (MP1), the gate of a second PMOS transistor (MP2) and the drain of a first NMOS transistor (MN1) Together A second node (N2) for connecting the gate of the first PMOS transistor (MP1), the drain of the second PMOS transistor (MP2) and the drain of a second NMOS transistor (MN2) Together A third node (N3) for connecting the source of a third NMOS transistor (MN3) and the drain of a fourth NMOS transistor (MN4) together; A first input terminal (IN), coupled to the gates of the first NMOS transistor (MN1) and the third NMOS transistor (MN3), for providing the first signal (V(IN)); A second input terminal (INB) is coupled to the gate of the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) to provide the inverse of the first signal (V(IN)) Phase signal An output terminal (OUT), coupled to the third node (N3), for outputting the second signal (V(OUT)); A first high power supply voltage (VDDH), coupled to the source of the first PMOS transistor (MP1), the second PMOS transistor (MP2), and the third PMOS transistor (MP3) to provide The first high power supply voltage required by the level converter; A second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the level converter. The second high power supply voltage (VDDL) has a lower potential than the first high power supply voltage (VDDH). ) Of potential; An input circuit (1), coupled to the first input terminal (IN), for providing a differential input signal; A latch circuit (2), coupled to the first high power supply voltage (VDDH) and the input circuit (1), for storing the differential input signal from the input circuit (1); and An output buffer circuit (3) is used to suppress the competition of the output potential and output the second signal (V(OUT)). The potential converter with output buffer circuit as described in item 1 of the scope of patent application, wherein the input circuit (1) includes: A first NMOS transistor (MN1), its source is connected to ground (GND), its gate is connected to the first input (IN), and its drain is connected to the first node (N1); A second NMOS transistor (MN2) whose source is connected to ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2); as well as A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)), and providing a signal with the first signal (V(IN)) Inverted signal. The potential converter with output buffer circuit as described in item 2 of the scope of patent application, wherein the latch circuit (2) includes: A first PMOS transistor (MP1) whose source is connected to the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the first node ( N1) are connected; and A second PMOS transistor (MP2), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the second node ( N2) Connected. The potential converter with output buffer circuit as described in item 3 of the scope of patent application, wherein the output buffer circuit (3) includes: A third PMOS transistor (MP3) whose source is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the third NMOS transistor The drain of the crystal (MN3) is connected; A third NMOS transistor (MN3) whose source is connected to the third node (N3), its gate is connected to the first input terminal (IN), and its drain is connected to the third PMOS transistor ( MP3) is connected to the drain; and A fourth NMOS transistor (MN4) has its source connected to ground (GND), its gate connected to the second input terminal (INB), and its drain connected to the third node (N3). The potential converter with an output buffer circuit as described in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volt and the second high power supply voltage (VDDL). The potential converter with output buffer circuit as described in claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volt and the first high power supply voltage (VDDH). The potential converter with an output buffer circuit as described in item 6 of the scope of patent application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

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