TWM528555U - Voltage level converter - Google Patents

Description

Voltage level converter

The present invention relates to a voltage level converter, especially comprising an amplitude conversion circuit (1), a potential control transistor (2) and another potential control transistor (3) for obtaining a precise voltage level. An electronic circuit that converts and effectively reduces power consumption.

A voltage level converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when an application system needs to transfer a signal from a core logic with a lower voltage level to a peripheral device with a higher voltage level, the voltage level converter is responsible for converting the low voltage operation signal into a high voltage operation signal. .

Figure 1 shows a prior art latch-type voltage level converter circuit using a first PMOS (P-channel metal oxide semiconductor) transistor (MP1). a second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverting phase The inverter (INV) constitutes a voltage level converter circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and the ground (GND), and the input voltage (V(IN)) The potential is also between ground (GND) and the second high potential voltage (VDDL). The input voltage (V(IN)) and the inverted input voltage signal output through the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively. because Thus, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is turned ON. In addition, due to the cross-coupled manner of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch There is no static current generated in the lock type voltage level converter. In particular, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned "ON", the gate potential of the first PMOS transistor (MP1) is pulled down and Making the first PMOS transistor (MP1) turn on, so as to pull up the gate potential of the second PMOS transistor (MP2) to turn off the second PMOS transistor (MP2); further, when the first NMOS transistor When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS is pulled up. The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, the above-described conventional voltage level converter is in the process of approaching (or turning off) the second PMOS transistor (MP2) and approaching (or turning on) the second NMOS transistor (MN2), The pull-up and pull-down of the potential on the output node (OUT) have a contention, so the output voltage signal (V(OUT)) is slower when it is converted to a low potential. Furthermore, it is considered that when the input voltage (V(IN) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that the second The PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volt cannot be instantaneously converted to 1.8 volts, the lower input voltage (V(IN)) during the conversion period It may not be possible to make the first PMOS transistor (MP1), the second PMOS transistor (MP2), and the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are fully turned on or completely turned off, which causes a static current between the first high potential voltage (VDDH) and ground (GND). Will increase the power loss.

Furthermore, the performance of the latch type voltage level converter is affected by the first high potential voltage (VDDH) due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). The voltage is the first high potential voltage (VDDH), and the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch type voltage level converter operate normally is limited.

Figure 2 is a diagram showing another prior art mirror type voltage level converter circuit for connecting the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) Connected to the drain of the first PMOS transistor (MP1) together such that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is The saturation region, and its gate voltage, causes the saturation current to be equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror type voltage level converter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, The performance of the voltage level converter will not change much. Therefore, the mirror type voltage level converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are electrically charged. The bit is pulled down so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. As such, a quiescent current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

In view of this, the main purpose of the present invention is to propose a voltage level converter that not only accurately and quickly converts a first signal into a second signal, but also effectively reduces leakage current, thereby reducing power consumption.

The present invention proposes a voltage level converter which is composed of an amplitude conversion circuit (1), a potential control transistor (2) and another potential control transistor (3), wherein the amplitude conversion circuit (1) Is used as a potential conversion; the potential control transistor (2) is used to pull up the voltage level of the first node (N1); and the potential control transistor (3) is used to pull up the first The voltage level of the two nodes (N2).

It is confirmed by the simulation results that the voltage level converter proposed by the present invention not only can accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and miniaturization of the device. At the same time, it can effectively reduce power loss.

1‧‧‧Amplitude conversion circuit

2‧‧‧potential control transistor

3‧‧‧potential control transistor

I1‧‧‧First Inverter

N1‧‧‧ first node

N2‧‧‧ second node

N3‧‧‧ third node

N4‧‧‧ fourth node

MP1‧‧‧First PMOS transistor

MP2‧‧‧second PMOS transistor

MP3‧‧‧ Third PMOS transistor

MP4‧‧‧fourth PMOS transistor

MP5‧‧‧ Fifth PMOS transistor

MP6‧‧‧6th PMOS transistor

MN1‧‧‧First NMOS transistor

MN2‧‧‧Second NMOS transistor

IN‧‧‧ first input

V(IN)‧‧‧first signal

INB‧‧‧ second input

OUT‧‧‧ output

GND‧‧‧

V(OUT)‧‧‧second signal

VDDH‧‧‧first high potential voltage

VDDL‧‧‧ second high potential voltage

1 is a circuit diagram showing a voltage level converter in a first prior art; FIG. 2 is a circuit diagram showing a voltage level converter in a second prior art; and FIG. 3 is a voltage level showing a preferred embodiment of the present invention. The circuit diagram of the quasi-converter; FIG. 4 is a timing diagram showing the transient analysis of the first signal and the second signal of the preferred embodiment of the present invention.

According to the above object, the present invention proposes a voltage level converter, as shown in FIG. 3, which is composed of an amplitude conversion circuit (1), a potential control transistor (2), and another potential control transistor (3). The amplitude conversion circuit (1) is used for potential conversion; the potential control transistor (2) is used to pull up the voltage level of the first node (N1); The crystal (3) is used to pull up the voltage level of the second node (N2); the amplitude conversion circuit (1) is coupled to the first power voltage and ground (GND) for use as a potential conversion Used by a first PMOS transistor (MP1), a second PMOS transistor (MP2), a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), and a first NMOS device. a crystal (MN1), a second NMOS transistor (MN2), and a first inverter (I1), wherein a source of the first PMOS transistor (MP1) is connected to a first high potential voltage (VDDH) a gate connected to the fourth node (N4) and a drain connected to the first node (N1); a source of the second PMOS transistor (MP2) connected to the first high potential voltage (VDDH) The gate is connected to the third node (N3), and the drain is connected to the second node (N2); the source of the fifth PMOS transistor (MP5) is connected to the first node (N1) a gate connected to the first input terminal (IN) and a drain connected to the third node (N3); a source of the sixth PMOS transistor (MP6) connected to the second node ( N2), the gate thereof is connected to the second input terminal (INB), and the drain thereof is connected to the fourth node (N4); the source of the first NMOS transistor (MN1) is connected to the ground (GND a gate connected to the first input terminal (IN) and a drain connected to the third node (N3); a source of the second NMOS transistor (MN2) connected to ground (GND) Its gate is connected to The second input terminal (INB) is connected to the fourth node (N4), and the first inverter (I1) is coupled to the first input terminal (IN) for Receiving the first signal (V(IN)) and providing a signal inverted from the first signal (V(IN)); the potential control transistor (2) is composed of a third PMOS transistor (MP3) Composed of a source connected to a first high potential voltage (VDDH), a gate connected to the first input terminal (IN), and a drain connected to the first node (N1); the potential control The transistor (3) is composed of a fourth PMOS transistor (MP4) whose source is connected to the first high potential voltage (VDDH), the gate of which is connected to the second input terminal (INB), and The pole is connected to the second node (N2); the first power voltage is used to provide a first high potential voltage (VDDH) required by the voltage level converter, and the second power voltage is used to provide the a second high potential voltage (VDDL) required by the voltage level converter, the level of the second high potential voltage (VDDL) being less than the level of the first high potential voltage (VDDH), the first signal being Rectangle between 0 volts and 1.2 volts Wave, and the second signal is a corresponding waveform between 0 volts and 1.8 volts, the first high potential voltage (VDDH) is 1.8 volts, and the second high potential voltage (VDDL) is 1.2 volts, the first A signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is a corresponding waveform between 0 volts and 1.8 volts. .

Please refer to Figure 3 again. Now consider the steady-state operation of the voltage level converter when the first signal (V(IN)) is low (0 volts): the low potential at the first input (IN) Transmitting to the input of the first inverter (I1), the gates of the first NMOS transistor (MN1), the third PMOS transistor (MP3), and the fifth PMOS transistor (MP5), so that the first NMOS is The crystal (MN1) is turned off, the third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are turned on, and at this time, since the third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are both turned on, Third node The potential of (N3) is pulled up to a high potential; the high potential of the third node (N3) causes the second PMOS transistor (MP2) to be turned off, and the first inverter (I1) transmits the second high potential voltage (VDDL) to the gates of the second NMOS transistor (MN2), the fourth PMOS transistor (MP4), and the sixth PMOS transistor (MP6) such that the second NMOS transistor (MN2) is turned on, and the fourth PMOS transistor is turned on (MP4) and a sixth PMOS transistor (MP6). At this time, since the second NMOS transistor (MN2) is turned on, the potential of the fourth node (N4) is pulled down to a low potential (0 volt). The steady state value, further, the low potential on the fourth node (N4) is transferred to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned on due to the first PMOS transistor (MP1), the third PMOS transistor (MP3), and the fifth PMOS transistor (MP5) are all turned on, and the first NMOS transistor (MN1) is turned off, so that the potential of the third node (N3) is pulled up to one. a first high potential voltage (VDDH), and since the second NMOS transistor (MN2) is turned on, the second PMOS transistor (MP2), the fourth PMOS transistor (MP4), and the sixth PMOS transistor (MP6) are all turned off, Therefore, the potential of the fourth node (N4) will be dimensioned Hold at low potential (0 volts), so the potential at the output (OUT) is pulled down to a low potential (0 volts) steady state value. In other words, when the first signal (V(IN)) is low (0 volts), it is converted into a second signal with a low potential (0 volt) by a voltage level converter, and is outputted by the output terminal (OUT).

Considering the steady state operation of the voltage level converter when the first signal (V(IN)) is the second high potential voltage (1.2 volts): the second high potential voltage at the first input (IN) (VDDL) Simultaneously transmitting to the input terminals of the first inverter (I1), the gates of the first NMOS transistor (MN1), the third PMOS transistor (MP3), and the fifth PMOS transistor (MP5), such that the first The NMOS transistor (MN1) is turned on, the third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are turned off, and the first inverter (I1) transmits a low potential to the second NMOS transistor (MN2) a gate of the fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) such that the second NMOS transistor (MN2) is turned off The closed fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) are turned on. At this time, since the fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) are both turned on, the fourth node (N4) The potential of the fourth node (N4) is turned off, and the high potential of the fourth node (N4) causes the first PMOS transistor (MP1) to be turned off. At this time, since the first NMOS transistor (MN1) is turned on, the The potential of the third node (N3) is pulled down to a low potential (0 volt) steady state value, and the low potential at the third node (N3) is transferred to the second PMOS transistor (MP2). a gate such that the second PMOS transistor (MP2) is turned on, and since the second PMOS transistor (MP2) and the sixth PMOS transistor (MP6) are both turned on, the second NMOS transistor (MN2) is turned off, and therefore, the fourth node The potential of (N4) will be maintained at the first high potential voltage (VDDH), while the potential of the third node (N3) is maintained at a low potential (0 volts), so the potential of the output terminal (OUT) will be pulled up to one. The steady state value of the first high potential voltage (VDDH). In a word, when the first signal (V(IN)) is the second high potential voltage (1.2 volts), it is converted into a second signal having a first high potential voltage (1.8 volts) by the voltage level converter, and the output is output. End (OUT) output.

In summary, when the first signal (V(IN)) is low (0 volts), the second signal (V(OUT)) is also low (0 volts); and the first signal (V(IN)) When the second high potential voltage (1.2 volts) is, the second signal (V(OUT)) is the first high potential voltage (1.8 volts). Thus, the purpose of voltage level conversion is achieved.

The result of the Spice transient analysis of the voltage level converter proposed by this work, as shown in Fig. 4, can be confirmed by the simulation results. The voltage level converter proposed by the present invention can not only be fast and accurate. The first signal is converted into a second signal, and the power loss can be effectively reduced.

While the present invention has specifically disclosed and described the preferred embodiments, it will be apparent to those skilled in the art that Spirit and scope. Therefore, all changes in the relevant technical scope are included in the scope of the patent application of this creation.

1‧‧‧Amplitude conversion circuit

2‧‧‧potential control transistor

3‧‧‧potential control transistor

I1‧‧‧First Inverter

N1‧‧‧ first node

N2‧‧‧ second node

N3‧‧‧ third node

N4‧‧‧ fourth node

MP1‧‧‧First PMOS transistor

MP2‧‧‧second PMOS transistor

MP3‧‧‧ Third PMOS transistor

MP4‧‧‧fourth PMOS transistor

MP5‧‧‧ Fifth PMOS transistor

MP6‧‧‧6th PMOS transistor

MN1‧‧‧First NMOS transistor

MN2‧‧‧Second NMOS transistor

IN‧‧‧ first input

V(IN)‧‧‧first signal

INB‧‧‧ second input

OUT‧‧‧ output

GND‧‧‧

V(OUT)‧‧‧second signal

VDDH‧‧‧first high potential voltage

VDDL‧‧‧ second high potential voltage

Claims (7)

A voltage level converter for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: a first node (N1) for using a first a drain of the PMOS transistor (MP1), a drain of a third PMOS transistor (MP3), and a source of a fifth PMOS transistor (MP5) are connected together; a second node (N2) for a drain of a second PMOS transistor (MP2), a drain of a fourth PMOS transistor (MP4), and a source of a sixth PMOS transistor (MP6) are connected together; a third node (N3), The gate of a fifth PMOS transistor (MP5), the gate of a second PMOS transistor (MP2), and the drain of a first NMOS transistor (MN1) are connected together; a fourth node ( N4) for connecting the drain of a sixth PMOS transistor (MP6), the gate of a first PMOS transistor (MP1), and the drain of a second NMOS transistor (MN2); An input terminal (IN) coupled to a third PMOS transistor (MP3), a fifth PMOS transistor (MP5), and a gate of a first NMOS transistor (MN1) for providing a first signal (V(IN)); a second input terminal (INB) coupled to a fourth PMOS transistor (MP4), a sixth PMOS transistor (MP6) and a gate of a second NMOS transistor (MN2) for providing an inverted signal (V(INB)) of the first signal (V(IN)) ; An output terminal (OUT) coupled to the fourth node (N4) for outputting the second signal (V(OUT)); a first power supply voltage for providing a voltage level converter required a high potential voltage (VDDH); a second power supply voltage for providing a second high potential voltage (VDDL) required by the voltage level converter, the potential of the second high potential voltage (VDDL) being less than the first a potential of a high potential voltage (VDDH); an amplitude conversion circuit (1) coupled to the first power supply voltage and ground (GND) for potential conversion; a potential control transistor (2) coupled to The first input terminal (IN) is used to pull up the voltage level of the first node (N1); and a potential control transistor (3) is coupled to the second input terminal (INB) for pulling Raise the voltage level of the second node (N2). The voltage level converter according to claim 1, wherein the amplitude conversion circuit (1) comprises: a first PMOS transistor (MP1) whose source is connected to the first high potential voltage (VDDH), The gate is connected to the fourth node (N4), and the drain is connected to the first node (N1); a second PMOS transistor (MP2) whose source is connected to the first high potential voltage ( VDDH), the gate thereof is connected to the third node (N3), and the drain thereof is connected to the second node (N2); a fifth PMOS transistor (MP5) having a source connected to the first node (N1), a gate connected to the first input (IN), and a drain connected to the third node (N3) Connected; a sixth PMOS transistor (MP6) having a source connected to the second node (N2), a gate connected to the second input (INB), and a drain connected to the fourth node (N4) connected; a first NMOS transistor (MN1) having a source connected to ground (GND), a gate connected to the first input (IN), and a drain connected to the third node (N3) is connected; a second NMOS transistor (MN2) having a source connected to ground (GND), a gate connected to the second input (INB), and a drain connected to the fourth node a (N4) phase connection; and a first inverter (I1) coupled to the first input terminal (IN) for accepting the first signal (V(IN)) and providing a first Signal (V(IN)) inverted signal (V(INB)). The voltage level converter according to claim 2, wherein the potential control transistor (2) is composed of a third PMOS transistor (MP3) whose source is connected to the first high potential voltage ( VDDH) has its gate connected to the first input (IN) and its drain connected to the first node (N1). The voltage level converter according to claim 3, wherein the potential control transistor (3) is composed of a fourth PMOS transistor (MP4) whose source is connected to the first high potential voltage ( VDDH) has its gate connected to the second input (INB) and its drain connected to the second node (N2). The voltage level converter of claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high potential voltage (VDDL). The voltage level converter of claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high potential voltage (VDDH). The voltage level converter of claim 6, wherein the voltage source of the first inverter (I1) is the second high potential voltage (VDDL).