TWI868962B - Semiconductor device and fabricating method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a gate pad and a source pad laterally separated from each other and both disposed above a first surface of the substrate, and a drain region disposed on a second surface of the substrate. A first trench is disposed in the substrate and directly under the gate pad. A conductive portion fills up the first trench and a dielectric liner is disposed in the first trench to surround the conductive portion. A first doped region is disposed on sides of the first trench. A second trench is disposed in the substrate and directly under the source pad. A gate electrode fills up the second trench, and a gate dielectric layer is disposed in the second trench to surround the gate electrode. A source region is disposed on sides of the second trench. The first doped region and the source region have the same conductivity type.

Description

Semiconductor device and method for manufacturing the same

This disclosure relates to semiconductor technology, and in particular to semiconductor devices including trench-type power transistors and methods for manufacturing the same.

In power electronics systems, power transistors are usually used as power components such as power switches and converters. Power transistors refer to transistors that work under high voltage and high current conditions. The most common power transistors are power metal-oxide-semiconductor field effect transistors (power MOSFETs), which include horizontal structures such as laterally-diffused MOS (LDMOS) field effect transistors (FETs), and vertical structures such as planar gate MOSFETs, trench gate MOSFETs, and MOSFETs. MOSFET), in which the gate is set in the trench. Compared with the planar gate MOSFET, the trench gate MOSFET has the advantage of reducing the size of the component unit. However, the known trench gate MOSFET still has many needs to be improved, such as reducing the on-resistance (Ron) and reducing various parasitic capacitances.

In view of this, the present disclosure proposes a semiconductor device and a manufacturing method thereof, wherein a plurality of trenches are disposed directly below a gate pad, a dielectric liner and a conductive portion are disposed in the trenches, and a doping region is disposed on the sides of the trenches, thereby increasing the number of effective trench-type power transistors directly below the gate pad, thereby reducing the specific on-resistance (Ron,sp) of the semiconductor device. In addition, a thick oxide layer is provided at the bottom of the trenches, thereby reducing the gate-drain capacitance (Cgd) below the gate pad. In addition, a self-aligned contact metal silicide layer is used on the doped region on the side of the trench, which can further reduce the cell pitch of the trench power transistor and help reduce the characteristic on-resistance of the semiconductor device.

According to an embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a gate pad, a source pad, a drain region, a first trench, a conductive portion, a dielectric liner, a first doped region, a second trench, a gate electrode, a gate dielectric layer, and a source region. The substrate has a first surface and a second surface, the gate pad and the source pad are laterally separated from each other and are both disposed on the first surface of the substrate, and the drain region is disposed on the second surface of the substrate. The first trench is arranged in the substrate, directly below the gate pad, the conductive part is filled in the first trench, the dielectric liner is arranged in the first trench and surrounds the conductive part, and the first doped region is arranged on the side of the first trench. The second trench is arranged in the substrate, directly below the source pad, the gate electrode is filled in the second trench, the gate dielectric layer is arranged in the second trench and surrounds the gate electrode, and the source region is arranged on the side of the second trench, wherein the first doped region and the source region have the same conductive type.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising the following steps: providing a substrate, including forming a drain region and forming an epitaxial layer on the drain region; performing an ion implantation process on the epitaxial layer to form a first doped region and a source region, both of which have a first conductivity type; forming a first trench and a second trench in the epitaxial layer, adjacent to the first doped region and the source region, respectively; region; forming a dielectric liner and a gate dielectric layer in the first trench and the second trench respectively; forming a conductive portion and a gate electrode in the first trench and the second trench respectively, wherein the dielectric liner surrounds the conductive portion and the gate dielectric layer surrounds the gate electrode; and forming a gate pad and a source pad laterally separated from each other on the epitaxial layer, and located directly above the first trench and the second trench respectively.

In order to make the features of this disclosure clear and easy to understand, the following is a detailed description of the embodiments with the accompanying drawings.

100:Semiconductor devices

100G: Gate pad area

100S: Source pad area

101: Epitaxial layer

101-1: First epitaxial layer

101-2: Second epitaxial layer

102: Sheltered area

103: Drain area

105: Well area

107: N-type heavily doped region

107-1: The first mixed area

107-2: Source region

109: P-type heavily doped region

109-1: Second mixed area

109-2: Matrix area

110: Base

110F: First surface

110B: Second surface

111: Metal silicide layer

120-1: First groove

120-2: Second groove

120i: Initial groove

120iB: Bottom

120s: sub-groove

121: Conductive part

122: Gate electrode

123: Dielectric liner

123S: Part 1

123B: Part 2

125: Gate dielectric layer

125S: Part 3

125B: Part 4

131: First metal layer

132: Second metal layer

133: Dielectric layer

133-1: Part of the dielectric layer

133-2: Another part of the dielectric layer

134: Open your mouth

135: Conductive hole

137: Gate pad

137E: Extension

139: Source pad

140: Hard mask

141: Pad oxide layer

142: First spacer material layer

142S: Spacer

143: Second spacer material layer

143S: Another partition

145: Dielectric layer

T1, T2, T3, T4: thickness

S101, S103, S105, S107, S109, S111, S113, S115, S117, S119, S121, S123, S125, S127, S129,: Steps

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to at the same time when reading this disclosure. Through the specific embodiments in this article and reference to the corresponding drawings, the specific embodiments of this disclosure are explained in detail and the working principles of the specific embodiments of this disclosure are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a schematic top view of a gate pad and a source pad of a semiconductor device according to an embodiment of the present disclosure.

Figures 3, 4, 5, 6, 7, 8, 9 and 10 are cross-sectional schematic diagrams showing some stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for limitation. For example, the description below of "a first feature is formed on or above a second feature" may refer to "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in this disclosure, such as "under", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of semiconductor devices during use and operation. As the orientation of the semiconductor device is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

The terms "coupling", "coupling", and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

Although the invention disclosed herein is described below by means of specific embodiments, the invention principles disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure relates to a semiconductor device including a trench power transistor and a manufacturing method thereof. In an embodiment of the present disclosure, a plurality of trenches are disposed directly below a gate pad, a dielectric liner and a conductive portion are disposed in the trenches, and a doped region is disposed on the side of the trenches, thereby increasing the number of effective trench power transistors directly below the gate pad, thereby reducing the characteristic on-resistance (Ron,sp) of the semiconductor device, and at the same time, significantly reducing the contact area between the source electrode and the drift region, thereby effectively reducing the drain-source capacitance (Cds). In addition, in the embodiments disclosed herein, a thick oxide layer is provided at the bottom of each trench, which can reduce the gate-drain capacitance (Cgd) increased by arranging the trench power transistor directly below the gate pad, thereby reducing the switch loss. In addition, in the embodiments disclosed herein, a self-aligned contact metal silicide layer is used on the doped region on the side of each trench, which can reduce the cell pitch of the trench power transistor, and help reduce the characteristic on-resistance.

FIG. 1 is a cross-sectional schematic diagram of a semiconductor device 100 according to an embodiment of the present disclosure, wherein the semiconductor device 100 includes a gate pad region 100G and a source pad region 100S. FIG. 2 is a top view schematic diagram of a gate pad 137 and a source pad 139 of the semiconductor device 100 according to an embodiment of the present disclosure, wherein the gate pad region 100G of FIG. 1 is drawn along the section line AA' of FIG. 2, and the source pad region 100S of FIG. 1 is drawn along the section line BB' of FIG. 2. Referring to FIG. 1 , the semiconductor device 100 includes a substrate 110 having a first surface 110F (e.g., a front surface) and a second surface 110B (e.g., a back surface) opposite to each other. The substrate 110 may include a drain region 103 disposed on the second surface 110B of the substrate. The drain region 103 has a first conductivity type, such as an N-type heavily doped region (N ⁺ ). The substrate 110 further includes an epitaxial layer 101 disposed on the drain region 103. The epitaxial layer 101 has a first conductivity type, such as an N-type epitaxial layer. In some embodiments, the drain region 103 is composed of, for example, an N-type heavily doped silicon carbide substrate (N ⁺ SiC substrate), and the epitaxial layer 101 is composed of, for example, an N-type silicon carbide epitaxial layer (N SiC epitaxial layer), but is not limited thereto.

Still referring to FIG. 1 , the semiconductor device 100 includes a gate pad 137 and a source pad 139, both of which are disposed on the first surface 110F of the substrate 110. As shown in FIG. 2 , the gate pad 137 and the source pad 139 are laterally separated from each other on the same plane (e.g., XY plane). As shown in FIG. 1 , the semiconductor device 100 includes a plurality of first trenches 120-1 disposed in the substrate 110 and located directly below the gate pad 137, and a plurality of second trenches 120-2 disposed in the substrate 110 and located directly below the source pad 139. From the top view of FIG. 2, the long axes of the first trenches 120-1 and the second trenches 120-2 extend in the same direction (e.g., the Y-axis direction), and a first trench 120-1 directly below the gate pad 137 can be aligned with a second trench 120-2 directly below the source pad 139 and arranged on the same straight line.

As shown in FIG. 1 , a dielectric liner 123 is disposed on the sidewall and bottom of the first trench 120-1 directly below the gate pad 137. The dielectric liner 123 includes a first portion 123S located on the sidewall of the first trench 120-1 and a second portion 123B on the bottom, and the thickness T1 of the second portion 123B in the Z-axis direction is greater than the thickness T2 of the first portion 123S in the X-axis direction. The conductive portion 121 is filled in the first trench 120-1, and the dielectric liner 123 surrounds the conductive portion 121. In addition, a gate dielectric layer 125 is disposed on the sidewall and bottom surface of the second trench 120-2 directly below the source pad 139. The gate dielectric layer 125 includes a third portion 125S located on the sidewall of the second trench 120-2 and a fourth portion 125B on the bottom surface. Similarly, the thickness T1 of the fourth portion 125B in the Z-axis direction is greater than the thickness T2 of the third portion 125S in the X-axis direction. The gate electrode 122 is filled in the second trench 120-2, and the gate dielectric layer 125 surrounds the gate electrode 122.

In addition, the semiconductor device 100 includes a well region 105 disposed in the epitaxial layer 101. The well region 105 has a second conductivity type, such as a P-type well region (p-well), and the well region 105 extends laterally from directly below the gate pad 137 to directly below the source pad 139. In addition, a first doped region 107-1 and a second doped region 109-1 are provided in the well region 105 directly below the gate pad 137. The first doped region 107-1 has a first conductivity type, such as an N-type heavily doped region (N ⁺ ), and the second doped region 109-1 has a second conductivity type, such as a P-type heavily doped region (P ⁺ ). The first doped region 107-1 is adjacent to both sides of the first trench 120-1, and the second doped region 109-1 is located between the two first doped regions 107-1 and is adjacent to the first doped region 107-1. In addition, a source region 107-2 and a bulk region 109-2 are provided in the well region 105 directly below the source pad 139, the source region 107-2 has a first conductivity type, for example, an N-type heavily doped region (N ⁺ ), and the bulk region 109-2 has a second conductivity type, for example, a P-type heavily doped region (P ⁺ ), wherein the source region 107-2 is adjacent to both sides of the second trench 120-2, and the bulk region 109-2 is located between the two source regions 107-2 and adjacent to the source region 107-2. In addition, the semiconductor device 100 further includes a metal silicide layer 111 using a self-aligned contact, which is disposed on the first doped region 107-1, the second doped region 109-1, the source region 107-2 and the body region 109-2, and the metal silicide layer 111 contacts the top surfaces of the above regions. The semiconductor device 100 further includes a shielding region 102 in the epitaxial layer 101. The shielding region 102 is correspondingly disposed directly below each first trench 120-1 and each second trench 120-2 and surrounds the bottom of each first trench 120-1 and each second trench 120-2. The shielding region 102 has a second conductivity type, such as a P-type heavily doped region (P ⁺ ). The shielding region 102 can provide an electric field shielding effect, thereby increasing the breakdown voltage of the semiconductor device.

Still referring to FIG. 1 , the semiconductor device 100 further includes a first metal layer 131 disposed directly below the source pad 139, and the first metal layer 131 directly contacts the metal silicide layer 111 located directly below the source pad 139. In addition, the vertical projection area of the first metal layer 131 and the vertical projection area of the gate pad 137 do not overlap, and when viewed from a top view, the first metal layer 131 and the gate pad 137 do not overlap on the XY plane. In addition, the semiconductor device 100 includes a dielectric layer 133 covering the first metal layer 131 and the metal silicide layer 111, a portion 133-1 of the dielectric layer 133 is located directly below the gate pad 137, another portion 133-2 of the dielectric layer 133 is located directly below the source pad 139, and a thickness T3 of the portion 133-1 of the dielectric layer 133 is greater than a thickness T4 of the other portion 133-2 of the dielectric layer 133. In one embodiment, the via 135 is disposed in another portion 133-2 of the dielectric layer 133, the gate pad 137 and the source pad 139 are disposed on the dielectric layer 133, the top surface of the gate pad 137 and the top surface of the source pad 139 may be on the same plane, and the gate pad 137, the source pad 139 and the via 135 may all be formed by the second metal layer 132, and the source pad 139 may be electrically connected to the first metal layer 131 through the via 135. In this embodiment, the provision of the first metal layer 131 helps the source pad 139 to be electrically connected to the source region 107-2 and the substrate region 109-2, and can reduce the height difference in the cross-sectional structure when manufacturing the source pad 139 and the via 135, making the manufacturing process of the source pad 139 and the via 135 easier to carry out.

In one embodiment, the gate electrode 122 and the conductive portion 121 can both be electrically coupled to the gate pad 137 and have a gate potential, wherein the gate electrode 122 located directly below the source pad 139 can be electrically coupled to the extension portion 137E of the gate pad 137 in Figure 2 via other conductive holes and wires (not shown) provided in another portion 133-2 of the dielectric layer 133 and conductive holes (not shown) passing through the dielectric layer 145 located above the gate electrode 122, and thereby electrically connected to the gate pad 137. In addition, the conductive portion 121 located directly below the gate pad 137 can be electrically coupled to the gate pad 137 via other conductive vias (not shown) penetrating a portion 133 - 1 of the dielectric layer 133 and the dielectric layer 145 located above the conductive portion 121 . In addition, the first doped region 107-1 located on the side of the first trench 120-1 can be electrically coupled to the source pad 139 via the metal silicide layer 111 and the conductive via and the conductive wire (not shown) disposed in a portion 133-1 of the dielectric layer 133, and the source region 107-2 located on the side of the second trench 120-2 can be electrically coupled to the source pad 139 via the metal silicide layer 111, the first metal layer 131 and the conductive via 135. In this embodiment, the conductive portion 121 and the dielectric liner 123 in the first trench 120-1 directly below the gate pad 137, and the first doped region 107-1 located on the side of the first trench 120-1 can constitute a trench-type power transistor, so that the number of effective trench-type power transistors can be increased directly below the gate pad 137, thereby reducing the characteristic on-resistance (Ron,sp) of the semiconductor device 100.

Compared to other semiconductor devices that do not have a trench power transistor directly under the gate pad 137, the characteristic on-resistance (Ron,sp) of the semiconductor device 100 of the embodiment of the present disclosure can be reduced by about 5% to 10%, but not limited thereto. When the gate pad 137 occupies a larger proportion of the overall area of the die, the more effective trench power transistors can be added directly under the gate pad 137, so that the characteristic on-resistance (Ron,sp) of the semiconductor device 100 is reduced to a greater extent, especially for small-sized die, because the gate pad occupies a higher proportion of the area, so the effect of reducing the characteristic on-resistance is more significant. In addition, in other embodiments, depending on the different electrical requirements of the semiconductor device 100, the conductive portion 121 in the first trench 120-1 can be electrically coupled to other potentials other than the gate, for example, it can be electrically coupled to the source potential or the ground terminal.

In addition, compared to other semiconductor devices that do not have any trenches disposed under the gate pad 137, according to some embodiments of the present disclosure, a plurality of first trenches 120-1 disposed under the gate pad 137 can also effectively reduce the drain-source capacitance (Cds). In addition, according to some embodiments of the present disclosure, the bottom of the first trench 120-1 under the gate pad 137 has a thick oxide layer (i.e., the second portion 123B of the dielectric liner 123), thereby reducing the gate-drain capacitance (Cgd) increased by disposing a trench-type power transistor directly under the gate pad 137, thereby reducing the switching loss of the semiconductor device 100. In addition, according to some embodiments of the present disclosure, a self-aligned contact metal silicide layer 111 is used on the first doped region 107-1, the second doped region 109-1, the source region 107-2 and the body region 109-2, and the cell pitch of the trench power transistor can be further reduced, which helps to reduce the characteristic on-resistance (Ron,sp) of the semiconductor device 100.

Figures 3, 4, 5, 6, 7, 8, 9 and 10 are cross-sectional schematic diagrams of some stages of a method for manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In Figures 3, 4, 5 and 6, the gate pad region 100G and the source pad region 100S of the semiconductor device 100 have the same cross-sectional structure. In Figures 7, 8, 9 and 10, the cross-sectional structures of the gate pad region 100G and the source pad region 100S of the semiconductor device 100 begin to differ. Referring to FIG. 3 , a wafer is first provided, which includes a drain region 103 and a first epitaxial layer 101-1 epitaxially grown on the drain region 103. In one embodiment, the drain region 103 is, for example, an N-type heavily doped silicon carbide substrate (N ⁺ SiC substrate), and the first epitaxial layer 101-1 is, for example, an N-type silicon carbide epitaxial layer (N SiC epitaxial layer). Then, through an ion implantation process and using a patterned photoresist, a shield region 102 is formed in the first epitaxial layer 101-1, such as a P-type heavily doped shield region (P ⁺ shield region), and the doping concentration of the shield region 102 is, for example, 1E17 to 1E19 atoms/cm ³ , but is not limited thereto.

Continuing to refer to FIG. 3 , in step S101, a second epitaxial layer 101-2 is epitaxially grown on the first epitaxial layer 101-1, so that the shielding area 102 is buried in the epitaxial layer 101 composed of the first epitaxial layer 101-1 and the second epitaxial layer 101-2, and the drain region 103 and the epitaxial layer 101 formed on the drain region 103 provide a substrate 110 of the semiconductor device 100. In one embodiment, the second epitaxial layer 101-2 is, for example, an N-type silicon carbide epitaxial layer, and the doping concentration of the second epitaxial layer 101-2 may be substantially equal to or higher than the doping concentration of the first epitaxial layer 101-1. In one embodiment, the doping concentration of the first epitaxial layer 101-1 may be approximately 1E14 to 1E16 atoms/cm ³ , and the doping concentration of the second epitaxial layer 101-2 may be approximately 1E15 to 1E17 atoms/cm ³ , but is not limited thereto.

Next, still referring to FIG. 3, in step S103, a well region 105, such as a P-type well region, is first formed in the second epitaxial layer 101-2 through an ion implantation process and using a hard mask. Then, a P-type heavily doped region (P ⁺ ) 109 is formed in the well region 105 through another ion implantation process and using another hard mask, and its doping concentration is higher than that of the well region 105. The P-type heavily doped region 109 is subsequently used as the second doping region 109-1 of the gate pad region 100G and the body region 109-2 of the source pad region 100S. Then, through another ion implantation process and using another hard mask, an N-type heavily doped region (N ⁺ ) 107 is formed in the well region 105, and its doping concentration is higher than the doping concentration of the well region 105, and the N-type heavily doped region 107 is adjacent to the P-type heavily doped region 109. The N-type heavily doped region 107 subsequently serves as the first doping region 107-1 of the gate pad region 100G and the source region 107-2 of the source pad region 100S. Afterwards, a high temperature activation process can be performed to activate the doping ions in the N-type heavily doped region 107 and the P-type heavily doped region 109.

Next, referring to FIG. 4 , in step S105, a patterned pad oxide layer 141 and a patterned hard mask 140 are formed on the N-type heavily doped region 107 and the P-type heavily doped region 109 through deposition, photolithography and etching processes, and then an initial trench 120i is formed in the epitaxial layer 101 through the openings of the pad oxide layer 141 and the hard mask 140 using an etching process, which extends downward through the N-type heavily doped region 107 and the well region 105 but does not reach the shielding region 102. Among them, the initial trench 120i located in the gate pad region 100G can be called the first initial trench, and the initial trench 120i located in the source pad region 100S can be called the second initial trench. Referring to Figures 1 and 4 at the same time, in the gate pad region 100G, the first doping region 107-1 is located on both sides of the initial trench 120i, and the second doping region 109-1 is located between the two first doping regions 107-1. Similarly, in the source pad region 100S, the source region 107-2 is located on both sides of the initial trench 120i, and the base region 109-2 is located between the two source regions 107-2.

Continuing to refer to FIG. 4, in step S107, a first spacer material layer 142, such as a silicon oxide layer, is firstly formed conformally on the sidewalls and bottom surface of the initial trench 120i using a thermal oxidation process. Then, a second spacer material layer 143 is formed conformally on the sidewalls and bottom surface of the initial trench 120i using a deposition process to cover the first spacer material layer 142. The second spacer material layer 143 is, for example, a silicon nitride layer. Still referring to FIG. 4 , in step S109 , an etching process is used to remove the second spacer material layer 143 and the first spacer material layer 142 on the bottom surface of the initial trench 120i to expose the bottom surface 120iB of the initial trench 120i, and to form a spacer 142S and another spacer 143S on the sidewall of the initial trench 120i. In the gate pad region 100G, the spacer 142S on the sidewall of the initial trench 120i can be referred to as a first spacer. In the source pad region 100S, the spacer 142S on the sidewall of the initial trench 120i can be referred to as a second spacer. In addition, in the gate pad region 100G, another spacer 143S located on the sidewall of the initial trench 120i can be called a third spacer, wherein the third spacer (spacer 143S) covers the first spacer (spacer 142S). In the source pad region 100S, another spacer 143S located on the sidewall of the initial trench 120i can be called a fourth spacer, wherein the fourth spacer (spacer 143S) covers the second spacer (spacer 142S).

Next, referring to FIG. 5, in step S111, a portion of the epitaxial layer 101 directly below the initial trench 120i is removed by an etching process through the exposed bottom surface 120iB of the initial trench 120i (as shown in FIG. 4) to form a sub-trench 120s. The sub-trench 120s is connected to the initial trench 120i, and the bottom surface of the sub-trench 120s is located in the shielding area 102. Among them, the sub-trench 120s located in the gate pad area 100G can be called the first sub-trench, and the sub-trench 120s located in the source pad area 100S can be called the second sub-trench.

Continuing to refer to FIG. 5, in step S113, a thermal oxidation process is used to form an oxide layer 145 in the sub-trench 120s. In the gate pad region 100G, the oxide layer 145 located in the first sub-trench can be referred to as a first oxide layer, and in the source pad region 100S, the oxide layer 145 located in the second sub-trench can be referred to as a second oxide layer. During the thermal oxidation process of step S113, the spacer 142S located on the sidewall of the initial trench 120i is covered by another spacer 143S, so that the thickness T2 of the spacer 142S after the thermal oxidation process is substantially the same as the thickness T2 of the spacer 142S before the thermal oxidation process. In addition, by controlling the process parameters of the thermal oxidation process in step S113, such as controlling the amount of oxygen introduced, the heating temperature and time, the oxide layer 145 formed in the sub-trench 120s can have a thickness T1, and the thickness T1 of the oxide layer 145 is much greater than the thickness T2 of the spacer 142S. As shown in FIG. 5, after step S113, the outlines of the first trench 120-1 of the gate pad region 100G and the second trench 120-2 of the source pad region 100S can be formed.

Thereafter, still referring to FIG. 5 , in step S115 , a stripping process is used, such as a wet etching process using a phosphoric acid solution, to remove the hard mask 140 and the spacers 143S on the sidewalls of the first trench 120 - 1 and the second trench 120 - 2 , leaving the spacers 142S on the sidewalls of the first trench 120 - 1 and the second trench 120 - 2 , and also leaving the liner oxide layer 141 on each doped region in the well region 105 . The spacer 142S (first spacer) on the sidewall of the first trench 120-1 and the oxide layer 145 (first oxide layer) on the bottom surface constitute the dielectric liner 123 in the first trench 120-1, and the spacer 142S (second spacer) on the sidewall of the second trench 120-2 and the oxide layer 145 (second oxide layer) on the bottom surface constitute the gate dielectric layer 125 in the second trench 120-2.

Then, referring to FIG. 6 , in step S117, a conductive material layer is deposited on the liner oxide layer 141 by a deposition process, and fills the first trench 120-1 and the second trench 120-2. In one embodiment, the conductive material layer is composed of, for example, doped polysilicon. Then, the conductive material layer is etched back to form a conductive portion 121 in the first trench 120-1, and a gate electrode 122 in the second trench 120-2. The bottom surface of the conductive part 121 and the bottom surface of the gate electrode 122 are both lower than the bottom surface of the well region 105, and the dielectric liner 123 in the first trench 120-1 surrounds the conductive part 121, and the gate dielectric layer 125 in the second trench 120-2 surrounds the gate electrode 122. In this embodiment, the lower part of the conductive part 121 and the lower part of the gate electrode 122 below the bottom surface of the well region 105 can be used as a field plate, which has the function of dispersing the electric field, thereby increasing the breakdown voltage of the semiconductor device.

6, in step S119, a dielectric layer 145 may be formed on the conductive portion 121 and the gate electrode 122 using a thermal oxidation process. After the dielectric layer 145 is formed, the top surfaces of the conductive portion 121 and the gate electrode 122 may be slightly lower than the top surfaces of the doped regions in the well region 105. Then, the liner oxide layer 141 on each doped region in the well region 105 can be removed by forming a patterned photoresist and using an etching process to expose the first doped region 107-1 and the second doped region 109-1 of the gate pad region 100G, and expose the source region 107-2 and the body region 109-2 of the source pad region 100S.

Then, still referring to FIG. 6, in step S121, a metal material (not shown), such as titanium (Ti), cobalt (Co), nickel platinum (NiPt) or other suitable metal barrier materials, is deposited on the first doped region 107-1, the second doped region 109-1, the source region 107-2 and the base region 109-2 by a deposition process, and then a rapid thermal treatment (RTP) is performed. Processing (RTP) is performed to make the metal material react with the silicon in the first doped region 107-1, the second doped region 109-1, the source region 107-2 and the body region 109-2 to form a metal silicide layer 111 located in the gate pad region 100G and the source pad region 100S. Afterwards, the unreacted metal material is removed.

Next, referring to FIG. 7, in step S123, a first metal layer 131 is formed on the gate pad region 100G and the source pad region 100S by a deposition process, which covers the metal silicide layer 111 and the dielectric layer 145 on the conductive portion 121 and the gate electrode 122. In one embodiment, the composition of the first metal layer 131 is, for example, aluminum silicon copper (AlSiCu), but is not limited thereto. The use of aluminum silicon copper (AlSiCu) can avoid the occurrence of junction spikes between the first metal layer 131 and the silicon carbide substrate 110.

Then, referring to FIG. 8 , in step S125, a patterned photoresist is formed to cover the first metal layer 131 located in the source pad region 100S, and an etching process is used to remove the first metal layer 131 located in the gate pad region 100G, so that the metal silicide layer 111 on the first doped region 107-1 and the second doped region 109-1 of the gate pad region 100G is exposed, and the first metal layer 131 located in the source pad region 100S is left, so that the first metal layer 131 is electrically connected to the metal silicide layer 111 located on the source region 107-2 and the body region 109-2. Removing the first metal layer 131 located in the gate pad region 100G can avoid the generation of parasitic capacitance between the first metal layer 131 and the gate pad formed subsequently.

Afterwards, referring to FIG. 9, in step S127, a dielectric material layer is deposited in the gate pad region 100G and the source pad region 100S to cover the metal silicide layer 111 of the gate pad region 100G and the first metal layer 131 of the source pad region 100S. Then, a chemical mechanical planarization (CMP) process is performed on the dielectric material layer to form a dielectric layer 133, wherein the thickness T3 of the dielectric layer 133 in the gate pad region 100G is greater than the thickness T4 of the dielectric layer 133 in the source pad region 100S.

Next, referring to FIG. 10 , in step S129, a patterned photoresist is formed and an etching process is used to form an opening 134 in the dielectric layer 133 of the source pad region 100S to expose the first metal layer 131. Then, a second metal layer 132 is deposited on the dielectric layer 133 and in the opening 134, wherein the second metal layer 132 filled in the opening 134 forms a via 135. In one embodiment, the composition of the second metal layer 132 is, for example, aluminum copper (AlCu), but is not limited thereto. Thereafter, another patterned photoresist is formed and another etching process is used to pattern the second metal layer 132 on the dielectric layer 133 to form a gate pad 137 and a source pad 139 that are laterally separated from each other as shown in FIG. 2, and the semiconductor device 100 is completed. The gate pad 137 is located directly above the first trench 120-1, and the source pad 139 is located directly above the second trench 120-2. In addition, the top surface of the gate pad 137 and the top surface of the source pad 139 formed on the flat surface of the dielectric layer 133 are on the same plane. In this embodiment, the gate pad 137, the source pad 139 and the via 135 are all formed by the second metal layer 132.

According to some embodiments of the present disclosure, the structures of the gate pad region and the source pad region of the semiconductor device can be formed simultaneously in the same process step, so there is no need to increase the number of masks and process steps, and the number of effective trench-type power transistors can be increased directly below the gate pad, thereby achieving the purpose of improving the electrical performance of the semiconductor device and saving the manufacturing cost of the semiconductor device.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:Semiconductor devices

100G: Gate pad area

100S: Source pad area

101: Epitaxial layer

102: Sheltered area

103: Drain area

105: Well area

107-1: The first mixed area

107-2: Source region

109-1: Second mixed area

109-2: Matrix area

110: Base

110F: First surface

110B: Second surface

111: Metal silicide layer

120-1: First groove

120-2: Second groove

121: Conductive part

122: Gate electrode

123: Dielectric liner

123S: Part 1

123B: Part 2

125: Gate dielectric layer

125S: Part 3

125B: Part 4

131: First metal layer

132: Second metal layer

133: Dielectric layer

133-1: Part of the dielectric layer

133-2: Another part of the dielectric layer

135: Conductive hole

137: Gate pad

139: Source pad

145: Dielectric layer

T1, T2, T3, T4: thickness

Claims (19)

A semiconductor device comprises: a substrate having a first surface and a second surface, the substrate comprising an epitaxial layer; a well region disposed in the epitaxial layer; a body region disposed in the well region and having a second conductivity type; a gate pad and a source pad, which are laterally separated from each other and are both disposed on the first surface of the substrate; a drain region disposed on the second surface of the substrate, wherein the epitaxial layer is located on the drain region; a first trench disposed in the substrate and directly below the gate pad; a conductive portion filled in the first trench; a dielectric liner disposed in the first trench and surrounding the conductive portion; a first doped region disposed in the substrate; a second doped region having the second conductivity type and disposed in the well region, wherein the second doped region is adjacent to the first doped region; a second trench disposed in the substrate and directly below the source pad; a gate electrode filled in the second trench; a gate dielectric layer disposed The first doped region and the source region are disposed in the second trench and surround the gate electrode; and a source region is located on the side of the second trench, wherein the first doped region and the source region have the same conductivity type, and the body region is adjacent to the source region, wherein the first doped region and the source region both have a first conductivity type, and the well region has the second conductivity type. A semiconductor device as described in claim 1, wherein the dielectric liner includes a first portion and a second portion, which are respectively located on the sidewall and bottom surface of the first trench, and the thickness of the second portion is greater than the thickness of the first portion, and the gate dielectric layer includes a third portion and a fourth portion, which are respectively located on the sidewall and bottom surface of the second trench, and the thickness of the fourth portion is greater than the thickness of the third portion. A semiconductor device as described in claim 1, wherein the gate electrode and the conductive portion are both electrically coupled to the gate pad, and the first doped region and the source region are both electrically coupled to the source pad. A semiconductor device as described in claim 1, wherein the well region extends laterally from directly below the gate pad to directly below the source pad, wherein the drain region and the epitaxial layer both have the first conductivity type, and the first doped region and the source region are both disposed in the well region. The semiconductor device as described in claim 4 further includes a metal silicide layer directly contacting the top surfaces of the first doped region, the second doped region, the source region and the base region. The semiconductor device as described in claim 5 further includes a first metal layer disposed directly below the source pad and directly contacting the metal silicide layer, wherein the source pad is electrically connected to the first metal layer, and the vertical projection area of the first metal layer and the vertical projection area of the gate pad do not overlap. The semiconductor device as described in claim 6 further includes a dielectric layer covering the first metal layer and the metal silicide layer, a portion of the dielectric layer is located directly below the gate pad, another portion of the dielectric layer is located directly below the source pad, and the thickness of the portion of the dielectric layer is greater than the thickness of the other portion of the dielectric layer. A semiconductor device as described in claim 7, wherein the gate pad and the source pad are formed of a second metal, and the top surface of the gate pad and the top surface of the source pad are on the same plane. The semiconductor device as described in claim 4 further includes a shielding region disposed directly below the first trench and the second trench, and having a conductivity type opposite to that of the first doped region and the source region. A method for manufacturing a semiconductor device includes: providing a substrate, forming a drain region and an epitaxial layer on the drain region; performing an ion implantation process on the epitaxial layer to form a first doped region and a source region, both of which have a first conductivity type; after performing the ion implantation process on the epitaxial layer, forming a first trench and a second trench in the epitaxial layer, adjacent to the first doped region and the source region respectively; A dielectric liner and a gate dielectric layer are formed in the first trench and the second trench respectively; a conductive portion and a gate electrode are formed in the first trench and the second trench respectively, wherein the dielectric liner surrounds the conductive portion and the gate dielectric layer surrounds the gate electrode; and a gate pad and a source pad are formed on the epitaxial layer and are laterally separated from each other and are located directly above the first trench and the second trench respectively. The method for manufacturing a semiconductor device as described in claim 10, wherein the dielectric liner and the gate dielectric layer are formed in the first trench and the second trench, respectively, comprising: forming a first initial trench and a second initial trench in the epitaxial layer; forming a first spacer and a second spacer on the sidewalls of the first initial trench and the sidewalls of the second initial trench, respectively, and exposing the bottom surface of the first initial trench and the bottom surface of the second initial trench; removing the dielectric liner and the gate dielectric layer in the first ... A portion of the epitaxial layer directly below and directly below the second initial trench to form a first sub-trench and a second sub-trench, which are connected to the first initial trench and the second initial trench respectively; and a thermal oxidation process is performed in the first sub-trench and the second sub-trench to form a first oxide layer and a second oxide layer respectively, wherein the first spacer and the first oxide layer constitute the dielectric liner, and the second spacer and the second oxide layer constitute the gate dielectric layer. A method for manufacturing a semiconductor device as described in claim 11, wherein the thickness of the first oxide layer is greater than the thickness of the first spacer, and the thickness of the second oxide layer is greater than the thickness of the second spacer. The method for manufacturing a semiconductor device as described in claim 11, wherein before forming the first sub-trench and the second sub-trench, a third spacer is formed to cover the first spacer, and a fourth spacer is formed to cover the second spacer, and after forming the first oxide layer and the second oxide layer, and before forming the conductive part and the gate electrode, the third spacer and the fourth spacer are removed. The method for manufacturing a semiconductor device as described in claim 11 further includes forming a shielding area in the epitaxial layer, having a second conductivity type, wherein the bottom surface of the first sub-trench and the bottom surface of the second sub-trench are both located in the shielding area. The method for manufacturing a semiconductor device as described in claim 10 further includes forming a well region in the epitaxial layer, having a second conductivity type, the first doped region and the source region are both formed in the well region, and the bottom surface of the conductive portion and the bottom surface of the gate electrode are both lower than the bottom surface of the well region. The method for manufacturing a semiconductor device as described in claim 15 further includes forming a second doped region and a base region in the well region, both of which have the second conductivity type, and the second doped region is adjacent to the first doped region, and the base region is adjacent to the source region. The method for manufacturing a semiconductor device as described in claim 16 further includes depositing a metal material on the first doped region, the second doped region, the source region and the base region, and the metal material reacts with silicon in the first doped region, the second doped region, the source region and the base region to form a metal silicide layer. The method for manufacturing a semiconductor device as described in claim 17 further includes: depositing a first metal layer on the metal silicide layer; removing the first metal layer in a predetermined formation region of the gate pad; forming a dielectric layer covering the first metal layer and the predetermined formation region of the gate pad; forming an opening in the dielectric layer to expose the first metal layer; depositing a second metal layer on the dielectric layer and in the opening; and patterning the second metal layer to form the gate pad and the source pad. A method for manufacturing a semiconductor device as described in claim 18, wherein forming the dielectric layer comprises: depositing a dielectric material layer on the predetermined formation region of the gate pad and the first metal layer; and performing a planarization process on the dielectric material layer to form the dielectric layer, wherein the top surface of the gate pad and the top surface of the source pad formed on the dielectric layer are on the same plane.

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