JP4025063B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technology effective when applied to a semiconductor device having a power MISFET (Metal Insulator Semiconductor Effect Effect Transistor) having a trench gate structure.
[0002]
[Prior art]
As a semiconductor device used for a switching element such as a power amplifier circuit or a power supply circuit, for example, a semiconductor device having a power transistor (high voltage element) called a power MISFET is known. The power MISFET has a multi-cell structure in which a plurality of fine pattern MISFETs are connected in parallel in order to obtain high power.
[0003]
In the power MISFET, what is called a vertical type or a horizontal type is known, and in the vertical type, what is called a trench gate structure is also known. Here, MISFET is an insulated gate field effect transistor in which an insulating film is interposed between a channel formation region (semiconductor) and a gate electrode, and a gate insulating film made of a silicon oxide film is generally used. It is also called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In addition, a current flowing in the thickness direction (depth direction) of the semiconductor substrate is called a vertical type, and a current flowing in the surface direction of the semiconductor substrate is called a horizontal type. In addition, an n-type (or n-channel conductivity type) can form an electron channel (conducting passage) in a channel formation region between the source region and the drain region (under the gate electrode), and a hole channel can be formed. This is called p-type (p-channel conductivity type). The trench gate structure is a gate structure in which a gate electrode is provided inside a groove provided in a main surface of a semiconductor substrate with an insulating film interposed. A power MISFET having a trench gate structure is described in, for example, Japanese Patent Application Laid-Open No. 7-249770.
[0004]
[Problems to be solved by the invention]
In the power MISFET having the trench gate structure, the miniaturization of the cell is progressing for each generation. With the miniaturization of the cell, the width of the groove in which the gate electrode is formed (trench width) is also reduced. Reducing the groove width has the following two advantages. FIG. 23A is a schematic cross-sectional view of a conventional power MISFET having a trench gate structure, and FIG. 23B is a schematic cross-sectional view when the width of the groove in FIG. 23A is reduced. In FIG. 23, 30 is a semiconductor substrate, 30a is an n + type semiconductor layer, 30b is an n− type semiconductor layer, 32 is a p type semiconductor region, 33 is a groove, 33W is the width of the groove, 34 is a silicon oxide film, and 35 is a gate. An electrode, 36 is an n + type semiconductor region, 37 is a p + type semiconductor region, 38 is an insulating film, 39 is a source electrode layer, 40 is a drain electrode layer, Ce is a cell, and CeP is a cell pitch. A fine pattern MISFET mainly has a channel formation region, a gate insulating film, a gate electrode 35, a source region, and a drain region. The channel formation region is formed of a p-type semiconductor region 32, the gate insulating film is formed of a silicon oxide film 34, the gate electrode 35 is formed of a polysilicon (single crystal silicon) film, and the source region is an n + type semiconductor region 36. The drain region is formed of an n + type semiconductor layer 30a and an n − type semiconductor layer 30b.
[0005]
The first merit is that conduction loss can be reduced. As shown in FIG. 23, when the width 33W of the trench 33 is reduced, the cell pitch CeP can be reduced and the number of cells Ce can be increased, so that the gate width per unit area can be increased. Since the on-resistance (Ron) can be reduced by increasing the gate width per unit area, the conduction loss of the power MISFET can be reduced.
[0006]
The second merit is that switching loss can be reduced. When the width 33W of the trench 33 is reduced, the facing area where the bottom surface of the gate electrode 35 and the n − type semiconductor layer 30b which is the drain region face each other can be reduced, and the gate-drain parasitic capacitance (Cgd) is directly reduced. Therefore, the switching loss of the power MISFET can be reduced.
[0007]
However, the gate resistance (Rg) increases as a side effect. As shown in FIG. 23, since the gate electrode 35 is formed inside the trench 33, when the width 33W of the trench 33 is reduced, the cross-sectional area of the gate electrode 35 is reduced and the gate resistance is increased. In particular, when the cell layout is striped to reduce the gate-drain parasitic capacitance, the gate resistance increases remarkably. This increase in gate resistance causes a switching loss to increase. Therefore, the present inventor made the present invention paying attention to the structure of the gate electrode 35.
[0008]
An object of the present invention is to provide a technology capable of suppressing an increase in gate resistance accompanying a reduction in the width of a groove in a semiconductor device having a trench gate structure.
[0009]
Another object of the present invention is to provide a technique capable of reducing conduction loss and switching loss in a semiconductor device having a trench gate structure.
[0010]
Another object of the present invention is to provide a technique capable of obtaining stable and reproducible transistor characteristics in a semiconductor device having a trench gate structure.
[0011]
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
[0012]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) a first semiconductor region on a main surface of a semiconductor substrate;
A second semiconductor region formed on the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region;
A third semiconductor region formed in the second semiconductor region and having the same conductivity type as the first semiconductor region;
A groove formed in the first, second and third semiconductor regions and extending in a first direction of the main surface of the semiconductor substrate;
An insulating film formed inside and outside the groove;
A semiconductor device having a conductor formed on the insulating film inside and outside the groove,
In a plane including the second direction perpendicular to the first direction, the width of the conductor formed outside the groove in the second direction is larger than the width of the conductor formed in the groove in the second direction. ,
The thickness of the conductor formed outside the groove is larger than the width of the conductor formed in the groove in the second direction.
[0013]
(2) In the semiconductor device according to the means (1),
The semiconductor substrate is formed with a MISFET having the conductor as a gate electrode, the first semiconductor region as a drain, the second semiconductor region as a channel formation region, and the third semiconductor region as a source region. . A semiconductor device.
[0014]
(3) a first semiconductor region on a main surface of the semiconductor substrate;
A second semiconductor region formed on the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region;
A third semiconductor region formed in the second semiconductor region and having the same conductivity type as the first semiconductor region;
A groove formed in the first, second and third semiconductor regions and extending in a first direction of the main surface of the semiconductor substrate;
An insulating film formed inside and outside the groove;
A semiconductor device having a conductor formed on the insulating film inside and outside the groove,
In a plane including the second direction perpendicular to the first direction, the width of the conductor formed outside the groove in the second direction is larger than the width of the conductor formed in the groove in the second direction. ,
The third semiconductor region is formed vertically below and outside the conductor formed outside the groove, and is in contact with the groove.
[0015]
(4) In the semiconductor device according to the means (3),
The third semiconductor region has a first portion located vertically below a conductor formed outside the groove and a second portion located outside the conductor vertically formed outside the groove. ,
The first portion of the third semiconductor region has an impurity concentration that is lower than the peak concentration of the second portion of the third semiconductor region and higher than the peak concentration of the second semiconductor region.
[0016]
(5) In the semiconductor device according to the means (3),
The semiconductor substrate is formed with a MISFET having the conductor as a gate electrode, the first semiconductor region as a drain, the second semiconductor region as a channel formation region, and the third semiconductor region as a source region. .
[0017]
(6) In the semiconductor device according to the means (3),
The semiconductor substrate includes a first semiconductor region serving as a drain region, a second semiconductor region serving as a channel formation region, and a third semiconductor region on one of the two side surfaces in the second direction of the groove. A first MISFET having a region as a source region and the conductor as a gate electrode is formed; and on the other side of the two sides in the second direction of the trench, the first semiconductor region is a drain region; A second MISFET is formed in which the second semiconductor region is a channel formation region, the third semiconductor region is a source region, and the conductor is a gate electrode.
[0018]
(7) In the semiconductor device according to (6),
On the two side surfaces of the groove, the third semiconductor region is formed in a first portion located vertically below the conductor formed outside the groove and outside the vertical lower side of the conductor formed outside the groove. A second part located,
The first portion of the third semiconductor region has an impurity concentration that is lower than the peak concentration of the second portion of the third semiconductor region and higher than the peak concentration of the second semiconductor region.
[0019]
(8) a first semiconductor region on a main surface of the semiconductor substrate;
A second semiconductor region formed in the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region;
A groove formed in the first and second semiconductor regions and extending in a first direction of a main surface of the semiconductor substrate;
A third semiconductor region formed in a position in contact with the groove in the second semiconductor region and having the same conductivity type as the first semiconductor region;
An insulating film formed inside and outside the groove;
A conductor formed on the insulating film inside and outside the groove,
In a plane including the second direction perpendicular to the first direction, the width of the conductor formed outside the groove in the second direction is larger than the width of the conductor formed in the groove in the second direction. ,
The third semiconductor region includes a first portion close to the groove and a second portion far from the groove,
The first portion of the third semiconductor region has a lower impurity concentration peak value than the second portion of the third semiconductor region, and has a higher impurity concentration peak value than the second semiconductor region. There,
Before forming the trench, a first portion of the third semiconductor region is formed.
[0020]
(9) In the method for manufacturing a semiconductor device according to the means (8),
After forming the conductor, a second portion of the third semiconductor region is formed.
[0021]
(10) In the method for manufacturing a semiconductor device according to the means (8),
The conductor is a gate electrode, the first semiconductor region is a drain region, the second semiconductor region is a channel formation region, and the third semiconductor region is a source region.
[0022]
(11) a first semiconductor region on a main surface of the semiconductor substrate;
A second semiconductor region formed on the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region;
A groove formed in the first and second semiconductor regions and extending in a first direction of a main surface of the semiconductor substrate;
A third semiconductor region formed in a position in contact with the groove in the first and second semiconductor regions and having the same conductivity type as the first semiconductor region;
An insulating film formed inside and outside the groove;
A semiconductor device having a conductor formed on the insulating film inside and outside the groove,
In a plane including the second direction perpendicular to the first direction, the width of the conductor formed outside the groove in the second direction is larger than the width of the conductor formed in the groove in the second direction. ,
The third semiconductor region further includes a first portion close to the trench and a second portion far from the trench, and an impurity concentration peak in the first portion of the third semiconductor region is an impurity in the second portion of the third semiconductor region. Below the concentration peak.
[0023]
(12) In the semiconductor device according to the means (11),
The first portion of the third semiconductor region is formed vertically below the conductor formed outside the groove.
[0024]
(13) In the semiconductor device according to (11),
The second part of the third semiconductor region is formed outside vertically below the conductor formed outside the groove.
[0025]
(14) In the semiconductor device described in the means (11),
A MISFET having the conductor as a gate electrode, the first semiconductor region as a drain region, the second semiconductor region as a channel formation region, and the third semiconductor region as a source region is formed on the semiconductor substrate. Yes.
[0026]
(15) A method for manufacturing a semiconductor device comprising the following steps:
(A) forming a first semiconductor region on the main surface of the semiconductor substrate;
(B) forming a second semiconductor region having a conductivity type opposite to that of the first semiconductor region in the first semiconductor region;
(C) forming a groove extending in the first direction of the main surface of the semiconductor substrate in the first and second semiconductor regions;
(D) forming a conductor inside and outside the groove;
(E) After the step (d), in a region in contact with the second semiconductor region, the third semiconductor region has the same conductivity type as the second semiconductor region and has an impurity concentration higher than the impurity concentration of the second semiconductor region. Forming a semiconductor region;
[0027]
(16) In the method for manufacturing a semiconductor device according to the means (15),
In a plane including a second direction perpendicular to the first direction, the width in the second direction of the conductor formed outside the groove is larger than the width in the second direction of the conductor formed in the groove. .
[0028]
(17) A method for manufacturing a semiconductor device comprising the following steps:
(A) forming a first semiconductor region on the main surface of the semiconductor substrate;
(B) implanting a first impurity having a conductivity type opposite to that of the first semiconductor region into the first semiconductor region;
(C) forming a groove extending in the first direction of the main surface of the semiconductor substrate in the first semiconductor region;
(D) forming a conductor inside and outside the groove;
(E) A step of implanting a second impurity having the same conductivity type as the first impurity and having a dose larger than that of the first impurity after the step (d).
[0029]
(18) In the method for manufacturing a semiconductor device according to the means (17),
In a plane including a second direction perpendicular to the first direction, the width in the second direction of the conductor formed outside the groove is larger than the width in the second direction of the conductor formed in the groove. .
[0030]
(19) In the method of manufacturing a semiconductor device according to the means (17),
After the step (b), the method further includes (f) a step of performing a heat treatment on the semiconductor substrate.
[0031]
(20) In the method of manufacturing a semiconductor device according to the means (19),
The heat treatment temperature in the step (f) is 900 ° C. or higher.
[0032]
(21) In the method for manufacturing a semiconductor device according to the means (17),
A step of forming an insulating film in the trench is further included between the steps (c) and (d).
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0034]
(Embodiment 1)
In the present embodiment, an example in which the present invention is applied to a semiconductor device having a power MISFET will be described.
[0035]
FIG. 1 is a plan layout diagram showing a schematic configuration of a semiconductor device according to Embodiment 1 of the present invention.
FIG. 2 is a schematic plan view showing a gate electrode pattern of the semiconductor device of FIG.
FIG. 3 is a schematic plan view in which a portion of region A shown in FIG. 2 is enlarged.
4 is a schematic cross-sectional view along the line AA in FIG.
FIG. 5 is an enlarged schematic cross-sectional view of a part of FIG.
FIG. 6 is a schematic cross-sectional view enlarging a part of FIG.
7A is an impurity concentration distribution diagram along line BB ′ in FIG. 6, and FIG. 7B is an impurity concentration distribution diagram along line CC ′ in FIG. 6.
[0036]
As shown in FIG. 1, the semiconductor device of this embodiment is mainly configured by a semiconductor chip 20 having a rectangular plane. A source electrode layer 17 and a gate electrode layer 18 are disposed on the main surface (circuit formation surface) of the semiconductor chip 20. The source electrode layer 17 and the gate electrode layer 18 are used as external terminals (bonding pads), and connected to a connection means such as a bonding wire that mediates electrical continuity with the outside. A drain electrode layer is disposed on the back surface opposite to the main surface of the semiconductor chip 20.
[0037]
A power MISFET is mounted on the semiconductor device. Power MISFET is
In order to obtain a large electric power, a multi-cell structure in which a plurality of fine pattern MISFETs are connected in parallel is employed. As shown in FIGS. 2 and 3, the power MISFET of this embodiment is along the first direction in a plane including the first direction of the main surface of the semiconductor chip 20 and the second direction perpendicular to the first direction. Thus, a striped cell layout is formed in which a plurality of cells Ce extending in the second direction are arranged.
[0038]
As shown in FIG. 4, the semiconductor chip 20 is mainly composed of a semiconductor substrate (semiconductor substrate) 1. As the semiconductor substrate 1, for example, a semiconductor substrate in which an n − type semiconductor layer 1b made of single crystal silicon is provided on the main surface of an n + type semiconductor layer 1a made of single crystal silicon is used. The n − type semiconductor layer 1b is set at a lower impurity concentration than the n + type semiconductor layer 1a. The n− type semiconductor layer 1a is, for example, 1.0E16 cm ^-3 The n + type semiconductor layer 1a is set to, for example, 2.0E19 cm. ^-3 The impurity concentration is set to a degree.
[0039]
A plurality of fine MISFETs are formed on the semiconductor substrate 1. Each MISFET mainly has a channel formation region, a gate insulating film, a gate electrode 9, a source region, and a drain region. The channel formation region is formed of, for example, a p − type semiconductor region (well region) 3 provided in the n − type semiconductor layer 1b. The gate insulating film is formed of, for example, a silicon oxide film 7 that is an insulating film. The source region is formed by an n-type semiconductor region 4 provided in the p-type semiconductor region 3 and an n + -type semiconductor region 11 provided in contact with the n-type semiconductor region 4 in the p-type semiconductor region 3. . The drain region is formed of an n − type semiconductor layer 1b and an n + type semiconductor layer 1a.
[0040]
On the main surface of the semiconductor substrate 1, a groove 6 that is recessed in the depth direction is formed. The groove 6 extends along the first direction of the main surface of the semiconductor substrate 1 and is provided for each cell Ce. On the back surface (other main surface) opposite to the main surface of the semiconductor substrate 1, a drain electrode layer 19 is provided in contact with the n + type semiconductor layer 1a. The drain electrode layer 19 is formed of a metal film whose main material is, for example, gold (Au).
[0041]
The silicon oxide film 7 is formed over the inside and outside of the groove 6, and the gate electrode 9 is composed of a conductor formed on the silicon oxide film 7. In the present embodiment, the gate electrode 9 includes a first portion (embedded portion) 9 a embedded in the trench 6 with the silicon oxide film 7 interposed therebetween, and a first portion that protrudes from the trench 6 and continues to the first portion 9 a. It has a configuration having two portions (protruding portions) 9b. The first portion 9 a and the second portion 9 b are formed along the extending direction of the groove 6. That is, the power MISFET has a trench gate structure.
[0042]
The gate electrode 9 includes, for example, mainly a polysilicon (polycrystalline silicon) film 8a into which an impurity for reducing a resistance value is introduced, and a tungsten silicide (WSi) film 8b having higher conductivity than the polysilicon film 8a. It has the composition which has. In the present embodiment, the first portion 9a of the gate electrode 9 is formed of a polysilicon film 8a, and the second portion 9b is formed of a polysilicon film 8a and a WSi film 8b provided on the polysilicon film 8a. .
[0043]
Each MISFET has a source region composed of an n-type semiconductor region 4 and an n + -type semiconductor region 11, a channel formation region composed of a p-type semiconductor region 3, and an n − -type semiconductor layer from the main surface of the semiconductor substrate 1 in the depth direction. The drain region composed of 1b and n + type semiconductor layer 1a is sequentially arranged. That is, each MISFET is configured as a vertical type in which current flows in the thickness direction of the semiconductor substrate 1, and further, an electron channel (conductive path) is formed in a channel formation region between the source region and the drain region (under the gate electrode). N channel conductivity type.
[0044]
The main surface (upper surface) of the second portion 9b of the gate electrode 9 is covered with the insulating film 10 formed in the same pattern as the second portion 9b, and the two side surfaces in the second direction of the second portion 9b are: The second portion 9b is covered with a side wall spacer 13 formed by self-alignment. The insulating film 10 and the sidewall spacer 13 are formed of an insulating film such as a silicon oxide film, for example.
[0045]
On the main surface of the semiconductor substrate 1, a groove 14 that is recessed in the depth direction is formed. The groove 14 extends along the first direction and is provided between the gate electrodes 9. A p + type semiconductor region 15 is provided under the trench 14, and the p + type semiconductor region 15 is formed in the p type semiconductor region 3.
[0046]
A barrier metal film 16 is formed on the main surface of the semiconductor substrate 1 so as to cover the second portion 9 b of the gate electrode 9, and a source electrode layer 17 is formed on the barrier metal film 16. The source electrode layer 17 is electrically connected to the n + type semiconductor region 11 and the p + type semiconductor region 15 with the barrier metal film 16 interposed therebetween. The second portion 9 b of the gate electrode 9 is electrically separated from the barrier metal film 16 and the source electrode layer 17 by the insulating film 10 and the sidewall spacer 13.
[0047]
The gate electrode 9 of each MISFET is formed integrally with a gate lead wiring extending so as to surround a cell array portion in which a plurality of cells Ce are arranged. The gate lead wiring is electrically connected to the gate electrode layer 18. ing. The gate electrode layer 18 is formed in the same layer as the source electrode layer 17 and is formed of, for example, a metal film made of aluminum or an alloy mainly composed of aluminum.
[0048]
As shown in FIGS. 4 and 5, the gate electrode 9 includes a first portion 9a embedded in the groove 6 formed in the semiconductor substrate 1 with a silicon oxide film 7 interposed therebetween, and the first portion 9a. It has the structure which has the 2nd part (protrusion part) 9b which continues and protrudes from the groove | channel 6. FIG. With this configuration, the width W1 in the second direction of the first portion 9a is reduced when the width 6W in the second direction of the groove 6 is reduced, but the width W2 in the second direction of the second portion 9b is reduced. Since the width 6W in the second direction of the trench 6 is not reduced, the reduction in the width 6W of the trench 6 can suppress an increase in gate resistance (Rg) accompanying the reduction in the width 6W of the trench 6.
[0049]
In the plane including the second direction perpendicular to the first direction of the main surface of the semiconductor substrate 1, the width W2 of the second portion 9b of the gate electrode 9 in the second direction is the width W1 of the first portion 9a in the second direction. Is bigger than. By adopting such a configuration, the resistance in the second portion 9b can be lowered, so that the increase in gate resistance (Rg) accompanying the reduction in the width 6W of the groove 6 can be further suppressed. Note that a silicon oxide film 7 is interposed between the projecting portion of the second portion 9b of the gate electrode 9 projecting above the ridge and the main surface of the semiconductor substrate 1, and both are insulated and separated by the silicon oxide film 7. ing.
[0050]
The thickness t of the second portion 9b of the gate electrode 9 is thicker than the width W1 of the first portion 9a. By configuring in this way, the resistance in the second portion 9b can be lowered, so that the increase in gate resistance (Rg) accompanying the reduction in the width 6W of the groove 6 can be further suppressed.
[0051]
The first portion 9a of the gate electrode 9 is formed of a polysilicon film 8a, and the second portion 9b is formed of a polysilicon film 8a and a WSi film 8b provided on the polysilicon film 8a. By adopting such a configuration, the resistance in the second portion 9b can be lowered, so that the increase in gate resistance (Rg) accompanying the reduction in the width 6W of the groove 6 can be further suppressed.
[0052]
Two MISFETs are formed in one cell Ce. These two MISFETs share the gate electrode 9. One MISFET has a channel formed on one side surface of two side surfaces opposite to each other in the first direction of the first portion 9 a of the gate electrode 9, and the other MISFET has the first portion of the gate electrode 9. A channel is formed on the other side of the two sides opposite to each other in the first direction of 9a.
[0053]
The source region is composed of an n-type semiconductor region 4 close to the trench 6 and an n + -type semiconductor region 11 far from the trench 6. The n-type semiconductor region 4 is formed in contact with the groove 6 vertically below the second portion 9 b of the gate electrode 9, and the n + -type semiconductor region 11 is formed outside the vertical portion of the second portion 9 b of the gate electrode 9. It is formed in contact with the region 4. That is, the source region includes an n-type semiconductor region 4 formed in contact with the groove 6 vertically below the second portion 9b of the gate electrode 9, and an n-type semiconductor region outside the vertically lower portion of the second portion 9b of the gate electrode 9. 4 and an n + type semiconductor region 11 formed in contact with the substrate 4.
[0054]
Here, when the n-type semiconductor region 4 is not provided, that is, when the source region is arranged away from the groove 6, the gate electrode is displaced due to misalignment of the mask when the gate electrode 9 is formed with reference to the groove 6. The channel length of the MISFET having the channel forming region on one side surface of the first portion 9a of the 9 is different from the channel length of the MISFET having the channel forming region on the other side surface of the second portion 9a of the gate electrode 9. Due to the structure, characteristics such as the on-resistance (Ron) and threshold voltage (Vth) of the power MISFET vary. In order to cope with this, it is necessary to form the source region deeply. In this case, the channel formation region and the trench 6 must also be formed deeply. Since it is extremely difficult to form the narrow and deep groove 6 in terms of the processing process, it is difficult to proceed with miniaturization. Further, when the source region, the channel formation region, and the trench 6 are deep, the parasitic capacitance increases, so that the switching loss increases.
[0055]
On the other hand, in the present embodiment, the n-type semiconductor region 4 is provided in contact with the groove 6 below the second portion 9b of the gate electrode 9, that is, the source region is in contact with the groove 6. Therefore, even if mask misalignment occurs when the gate electrode 9 is formed with reference to the groove 6, the channel length on the one side surface of the first portion 9 a of the gate electrode 9 and the first Since the channel length on the other side surface of the portion 9a is constant, variations in on-resistance, threshold voltage, and the like can be suppressed. Thereby, stable and reproducible transistor characteristics can be obtained.
[0056]
In addition, since it is not necessary to form a deep source region, the channel formation region and the groove 6 can be shallowed, and miniaturization is facilitated. Further, since it is not necessary to form a deep source region, an increase in parasitic capacitance can be suppressed. Thereby, an increase in switching loss can be suppressed.
[0057]
As shown in FIG. 7, the n + type semiconductor region 11 has a peak concentration of 1E20 to 5E20 cm, for example. ^-3 For example, the n-type semiconductor region 4 has a peak concentration of 1E18 to 1E20 cm. ^-3 For example, the p-type semiconductor region 3 has a peak concentration of 1E16 to 1E18 cm. ^-3 The impurity concentration is set to a degree. That is, the n-type semiconductor region 4 is set to an impurity concentration lower than that of the n + -type semiconductor region 11 and higher than that of the p-type semiconductor region 3. The reason for this concentration relationship is shown below.
[0058]
The n + -type semiconductor region 11 is 1E20 to 5E20 cm in order to make ohmic contact with the source electrode layer 17. ^-3 It is necessary to make the concentration as high as possible. If the concentration of the n-type semiconductor region 4 is increased to the same level as that of the n + -type semiconductor region 11, the n-type semiconductor region 4 becomes too deep and the channel length becomes extremely short. If it does so, since it will become easy to punch through, sufficient withstand pressure | voltage cannot be obtained.
[0059]
The reason why the n-type semiconductor region 4 is deepened when the concentration of the n-type semiconductor region 4 is increased to the same level as that of the n + -type semiconductor region 11 is that the heat treatment received after the formation is different. Since the n + -type semiconductor region 11 is formed after processing the gate electrode, heat treatment necessary for activation may be performed, for example, at 900 ° C. for about 20 minutes, but the n-type semiconductor region 4 forms the groove 6 and the gate electrode. Since it must be formed in the previous step, the number of heat treatment steps such as a gate oxidation step increases, and the n-type semiconductor region 4 becomes deep.
[0060]
As described above, the n-type semiconductor region 4 can be formed shallower by setting the n-type semiconductor region 4 to an impurity concentration lower than that of the n + -type semiconductor region 11 and higher than that of the p-type semiconductor region 3. Sufficient breakdown voltage can be obtained.
[0061]
Next, manufacturing of the semiconductor device will be described with reference to FIGS. 8 to 18 are schematic cross-sectional views during the manufacturing process of the semiconductor device.
[0062]
First, the semiconductor substrate 1 shown in FIG. 8 is prepared, and then the insulating film 2 is formed on the main surface of the semiconductor substrate 1.
[0063]
Next, as shown in FIG. 9, a p-type semiconductor region 3 is formed on the main surface of the semiconductor substrate 1. The p-type semiconductor region 3 is formed by introducing an impurity (for example, boron) into the main surface of the semiconductor substrate 1 by an ion implantation method and then performing an activation heat treatment.
[0064]
Next, as shown in FIG. 10, an n-type semiconductor region 4 is formed on the main surface of the p-type semiconductor region 3. The n-type semiconductor region 4 is formed by introducing an impurity (for example, arsenic) into the main surface of the p-type semiconductor region 3 by an ion implantation method and then performing an activation heat treatment. For example, the impurity is introduced at a dose of 1E14 to 5E14 cm. ^-2 The degree of energy is about 80 Kev. The heat treatment for activating the impurities is performed under conditions of 900 ° C. or higher.
[0065]
Next, the insulating film 2 is removed, and then a mask 5 made of, for example, a silicon oxide film is formed on the main surface of the semiconductor substrate 1 as shown in FIG. The mask 5 is formed in a pattern having an opening in a groove forming region on the main surface of the semiconductor substrate 1.
[0066]
Next, using the mask 5 as an etching mask, the semiconductor substrate 1 is etched to form the grooves 6.
[0067]
Next, after removing the mask 5, a thermal oxidation process is performed to form a silicon oxide film 7 on the inner wall of the trench 6 and the main surface of the semiconductor substrate 1 (inside and outside of the trench 6), as shown in FIG. This silicon oxide film 7 is used as a gate insulating film. The thermal oxidation treatment is performed by a wet oxidation method at about 850 ° C., for example. In this step, the n-type semiconductor region 4 is subjected to high-temperature heat treatment when the silicon oxide film 7 is formed, but the n-type semiconductor region 4 has a peak concentration of 1E18 to 1E20 cm. ^-3 Therefore, the diffusion of the n-type semiconductor region 4 extending in the depth direction can be suppressed.
[0068]
When a silicon oxide film is formed on the inner wall of the groove 6 and the main surface of the semiconductor substrate 1 by thermal oxidation, at the upper edge of the groove 6 (corner between the side surface of the groove and the main surface of the substrate). Since the thickness of the silicon oxide film is thinner than other portions, it causes a reduction in gate breakdown voltage. This decrease in film thickness can be suppressed by forming a silicon oxide film by a dry oxidation method at 1100 ° C. or higher. When the silicon oxide film 7 is formed by this dry oxidation method, the n-type semiconductor region 4 is subjected to a higher temperature heat treatment. Therefore, it is necessary to set the n-type semiconductor region 4 to an impurity concentration with as little diffusion as possible according to the temperature condition when forming the silicon oxide film 7.
[0069]
Next, as shown in FIG. 13, a polysilicon film 8a is formed on the main surface of the semiconductor substrate 1 so as to fill the trench 6, for example, by CVD, and then a WSi film 8b is formed on the polysilicon film 8a, for example, by CVD. Then, the insulating film 10 made of, for example, a silicon oxide film is formed on the WSi film 8b by the CVD method.
[0070]
Next, the insulating film 10, the WSi film 8b, and the polysilicon film 8a are sequentially patterned to form the gate electrode 9 as shown in FIG. In this step, a gate electrode 9 having a first portion 9 a embedded in the groove 6 of the semiconductor substrate 1 and a second portion 9 b that continues to the first portion 9 a and protrudes from the groove 6 is formed. In this step, the gate electrode 9 is formed so that the width of the second portion 9b in the second direction is wider than the width of the first portion 9a in the second direction. In this step, the gate electrode 9 is formed such that the thickness of the second portion 9b is larger than the width of the first portion 9a in the second direction.
[0071]
Next, as shown in FIG. 15, an n + type semiconductor region 11 is formed on the main surface of the p type semiconductor region 3. The n + -type semiconductor region 11 uses the gate electrode 9 and the insulating film 10 as an impurity introduction mask, introduces impurities (for example, arsenic) into the main surface of the semiconductor substrate 1 by ion implantation, and then activates heat treatment. It is formed by applying. For example, the impurity is introduced at a dose of 5E15 to 1E16 cm. ^-2 The degree of energy is about 80Kev. The heat treatment for activating the impurities is performed under conditions of 900 ° C. or higher. In this step, an n-type semiconductor region 4 formed in contact with the groove 6 vertically below the second portion 9b of the gate electrode 9, and an n-type semiconductor region 4 formed outside vertically below the second portion 9b of the gate electrode 9 A source region having an n + type semiconductor region 11 formed in contact therewith is formed.
[0072]
Next, as shown in FIG. 16, an insulating film 12 made of, for example, a silicon oxide film is formed on the entire main surface of the semiconductor substrate 1 including the gate electrode 9, and then RIE (Reactive Ion Etching) is formed on the insulating film 12. As shown in FIG. 17, sidewall spacers 13 are formed on each of the two side surfaces of the second portion 9 b of the gate electrode 9 in the second direction. The sidewall spacer 13 is formed in a self-aligned manner with respect to the second portion 9 b of the gate electrode 9. Through this step, the second portion 9 b of the gate electrode 9 is covered with the sidewall spacer 13 and the insulating film 10.
[0073]
Next, using the insulating film 10 and the side wall spacers 13 as an etching mask, the main surface of the semiconductor substrate 1 is etched, and as shown in FIG. 18, a groove that is recessed in the depth direction from the main surface of the semiconductor substrate 1. 14 is formed. The trench 14 is formed in self-alignment with the insulating film 10 and the sidewall spacer 13.
[0074]
Next, the insulating film 10 and the sidewall spacer 13 are used as an impurity introduction mask, and an impurity (for example, boron) is selectively introduced into the bottom of the groove 14 by an ion implantation method. As shown in FIG. A p + -type semiconductor region 15 is formed in the portion of the p-type semiconductor region 3 facing the bottom surface of 14.
[0075]
Next, a barrier metal film 16 is formed on the entire surface of the semiconductor substrate 1 including the inside of the trench 14 by, for example, sputtering, and then, for example, aluminum or an alloy containing aluminum as a main component is formed on the entire surface of the barrier metal film 16. A metal film is formed by, for example, a sputtering method, and then the metal film and the barrier metal film 16 are sequentially patterned to form the source electrode layer 17 and the gate electrode layer 18. The source electrode layer 17 is electrically connected to the p + type semiconductor region 15 and the n + type semiconductor region 11 with the barrier metal film 16 interposed therebetween. By this step, the source electrode layer 17 and the gate electrode 9 can be separated by self-alignment.
[0076]
Next, a protective film made of, for example, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1, and then the protective film is subjected to patterning so that a part of the surface of the source electrode layer 17 is exposed and the gate electrode layer The semiconductor device shown in FIGS. 1 to 4 is almost completed by forming an opening exposing a part of the surface of 18 and then forming a drain electrode layer 19 on the back surface opposite to the main surface of the semiconductor substrate 1. To do.
[0077]
Thus, according to the present embodiment, the following effects can be obtained.
(1) The gate electrode 9 is connected to the first portion 9 a embedded in the groove 6 formed in the semiconductor substrate 1 with the silicon oxide film 7 interposed therebetween, and projects from the groove 6. It has the structure which has the 2nd part (protrusion part) 9b. With this configuration, the width W1 of the first portion 9a is reduced when the width 6W of the groove 6 is reduced, but the width W2 of the second portion 9b is not reduced even when the width 6W of the groove 6 is reduced. The increase in gate resistance (Rg) accompanying the reduction of the width 6W of the trench 6 can be suppressed.
[0078]
Moreover, since the increase in gate resistance (Rg) accompanying the reduction in the width 6W of the groove 6 can be suppressed, the conduction loss and switching loss of the power MISFET can be reduced.
[0079]
(2) The width W2 of the second portion 9b of the gate electrode 9 is larger than the width W1 of the first portion 9a. By configuring in this way, the resistance in the second portion 9b can be lowered, so that the increase in gate resistance (Rg) accompanying the reduction in the width 6W of the groove can be further suppressed.
[0080]
(3) The thickness t of the second portion 9b of the gate electrode 9 is thicker than the width W1 of the first portion 9a. By configuring in this way, the resistance in the second portion 9b can be lowered, so that the increase in gate resistance (Rg) accompanying the reduction in the width 6W of the groove can be further suppressed.
[0081]
(4) The first portion 9a of the gate electrode 9 is formed of a polysilicon film 8a, and the second portion 9b is formed of a polysilicon film 8a and a WSi film 8b provided on the polysilicon film 8a. By adopting such a configuration, the resistance in the second portion 9b can be lowered, so that the increase in gate resistance (Rg) accompanying the reduction in the groove width 6W can be further suppressed.
[0082]
(5) The source region includes an n-type semiconductor region 4 formed in contact with the groove 6 vertically below the second portion 9b of the gate electrode 9, and an n-type semiconductor outside the vertically lower portion of the second portion 9b of the gate electrode 9. The structure includes an n + type semiconductor region 11 formed in contact with the region 4. With such a configuration, even when misalignment of the mask occurs when the gate electrode 9 is formed with reference to the groove 6, the channel length on the one side surface of the first portion 9a of the gate electrode 9 and the gate Since the channel length on the other side surface of the first portion 9a of the electrode 9 is constant, variations in on-resistance, threshold voltage, and the like can be suppressed. Thereby, stable and reproducible transistor characteristics can be obtained.
[0083]
In addition, since it is not necessary to form a deep source region, the channel formation region and the groove 6 can be shallowed, and miniaturization is facilitated. Further, since it is not necessary to form a deep source region, an increase in parasitic capacitance can be suppressed. Thereby, an increase in switching loss can be suppressed.
[0084]
(6) The n-type semiconductor region 4 is set to an impurity concentration lower than that of the n + -type semiconductor region 11 and higher than that of the p-type semiconductor region 3. With such a configuration, the n-type semiconductor region 4 can be formed shallow, so that a sufficient breakdown voltage can be obtained.
[0085]
(Embodiment 2)
FIG. 19 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to Embodiment 2 of the present invention.
[0086]
As shown in FIG. 19, the semiconductor device of the present embodiment has basically the same configuration as that of the first embodiment described above, and the configuration of the gate electrode 9 is different.
[0087]
That is, in the gate electrode, the first portion 9a and the second portion 9b are composed of the polysilicon film 8a and the WSi film 8b. By adopting such a configuration, the resistance in the first portion 9a and the second portion 9b can be lowered, so that the increase in gate resistance (Rg) accompanying the reduction in the groove width 6W can be further suppressed.
[0088]
(Embodiment 3)
FIG. 20 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to Embodiment 3 of the present invention.
[0089]
As shown in FIG. 20, the semiconductor device of this embodiment has basically the same configuration as that of the first embodiment described above, and the following configuration is different.
[0090]
That is, in the first embodiment described above, the p + type semiconductor region 15 which is a contact region is formed immediately below the groove 14. However, in this embodiment, the groove 14 is omitted and the main surface of the semiconductor substrate 1 is formed. The p + type semiconductor region 15 is formed in a self-aligned manner with respect to the sidewall spacer 13. Even in such a semiconductor device, by applying the present invention, the same effects as those of the first embodiment can be obtained.
[0091]
(Embodiment 4)
FIG. 21 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to Embodiment 4 of the present invention.
[0092]
As shown in FIG. 21, the semiconductor device of this embodiment has basically the same configuration as that of the above-described first embodiment, and the following configuration is different.
[0093]
That is, in the first embodiment, the source electrode layer 17 is connected to the n + type semiconductor region 11 and the p + type semiconductor region 15 through self-alignment through the connection hole defined by the sidewall spacer 13. In the present embodiment, an interlayer insulating film 21 made of, for example, a silicon oxide film is formed on the main surface of the semiconductor substrate 1 so as to cover the second portion 9 b of the gate electrode 9, and well-known photolithography is formed on the interlayer insulating film 21. A connection hole is formed by a technique, and the source electrode layer 17 is connected to the n + type semiconductor region 11 and the p + type semiconductor region 15 through the connection hole. Even in such a semiconductor device, by applying the present invention, the same effects as those of the first embodiment can be obtained.
[0094]
(Embodiment 5)
FIG. 22 is a schematic plan view showing a schematic configuration of the semiconductor device according to the third embodiment of the present invention.
[0095]
As shown in FIG. 22, the semiconductor device of the present embodiment has basically the same configuration as that of the first embodiment described above, and the following configuration is different.
[0096]
That is, the power MISFET mounted on the semiconductor device has a mesh structure in which the gate electrode 6 is formed in a stitch shape. Even in such a semiconductor device, by applying the present invention, the same effects as those of the first embodiment can be obtained.
[0097]
Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.
[0098]
For example, the present invention can be applied to a semiconductor device having an IGBT (Insulated Gate Bipolar Transistor) having a trench gate structure.
[0099]
In addition, the present invention can be applied to a power IC (Integrated Circuit) in which a cell array unit composed of a plurality of transistor cells composed of transistor elements having a trench gate structure and a control circuit unit are mixedly mounted on the same semiconductor substrate.
[0100]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0101]
According to the present invention, in a semiconductor device having a trench gate structure, it is possible to suppress an increase in gate resistance due to a reduction in the width of a groove.
[0102]
According to the present invention, conduction loss and switching loss can be reduced in a semiconductor device having a trench gate structure.
[0103]
According to the present invention, stable and reproducible transistor characteristics can be obtained in a semiconductor device having a trench gate structure.
[Brief description of the drawings]
FIG. 1 is a plan layout diagram illustrating a schematic configuration of a semiconductor device according to a first embodiment of the present invention;
2 is a schematic plan view showing a gate electrode pattern of the semiconductor device of FIG. 1. FIG.
FIG. 3 is a schematic plan view in which a part (region A) of FIG. 2 is enlarged.
4 is a schematic cross-sectional view taken along the line AA in FIG. 3. FIG.
5 is an enlarged schematic cross-sectional view of a part of FIG.
6 is an enlarged schematic cross-sectional view of a part of FIG.
7A is an impurity concentration distribution diagram along the line BB ′ in FIG. 6; FIG. 7B is an impurity concentration distribution diagram along the line CC ′ in FIG. 6;
FIG. 8 is a schematic cross-sectional view during the manufacturing process of the semiconductor device according to the first embodiment of the present invention;
9 is a schematic cross sectional view of the semiconductor device during a manufacturing step following that of FIG. 8; FIG.
10 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9; FIG.
11 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10; FIG.
12 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG.
13 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG.
14 is a schematic cross sectional view of the semiconductor device during a manufacturing step following that of FIG. 13; FIG.
15 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 14; FIG.
16 is a schematic cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG.
17 is a schematic cross sectional view of the semiconductor device during a manufacturing step following that of FIG. 16; FIG.
18 is a schematic cross sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; FIG.
FIG. 19 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to a second embodiment of the present invention.
FIG. 20 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to a third embodiment of the present invention.
FIG. 21 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 22 is a schematic plan view showing a main part of a gate electrode pattern of a semiconductor device according to a fifth embodiment of the present invention.
23A is a schematic cross-sectional view of a conventional semiconductor device having a power MISFET, and FIG. 23B is a schematic cross-sectional view when the width of the groove shown in FIG.
[Explanation of symbols]
1 ... Semiconductor substrate
1a ... n + type semiconductor layer
1b: n-type semiconductor layer
2… Insulating film
3 ... p-type semiconductor region
4 ... n-type semiconductor region
5 ... Mask
6 ... Groove
7 ... Silicon oxide film
8a ... polysilicon film
8b: Tungsten silicide (WSi) film
9 ... Gate electrode
9a: Embedded portion (first portion)
9b ... Projecting part (second part)
10. Insulating film
11 ... n + type semiconductor region
12 ... Insulating film
13. Side wall spacer
14 ... Groove
15 ... p + type semiconductor region
16 ... Barrier metal film
17 ... Source electrode layer
18 ... Gate electrode layer
19 ... Drain electrode layer

Claims (3)

A first semiconductor region formed at a certain depth from the surface of the semiconductor substrate;
A second semiconductor region formed in a region whose depth from the surface of the semiconductor substrate is shallower than the first semiconductor region, and having a conductivity type opposite to that of the first semiconductor region;
A third semiconductor region having the same conductivity type as the first semiconductor region, formed from a region having a shallower depth from the surface of the semiconductor substrate than the second semiconductor region to the surface of the semiconductor substrate;
Formed in contact with the first, second, and third semiconductor regions, extends in a first direction on the surface of the semiconductor substrate, and has a first width in a second direction orthogonal to the first direction. With a groove
An insulating film formed over the inner wall of the groove and the surface of the semiconductor substrate;
In the groove and along the insulating film on the surface of the semiconductor substrate, it is formed from the bottom of the groove to the surface of the semiconductor substrate, and on the surface of the semiconductor substrate outside the groove, in the second direction. A first conductive film formed so as to cover the groove with a width larger than the first width and both ends in the second direction having a certain width from the groove wall, and from the bottom in the groove; A portion provided so as to be surrounded by the first conductive film up to a surface of the semiconductor substrate, and a second surface of the semiconductor substrate outside the groove so as to be stacked on the first conductive film. And a second conductive film having a conductivity higher than that of the first conductive film, which is integrally formed with a portion provided in a direction larger than the first width. And the thickness of the second conductive film is larger than the first width, Width, a gate electrode formed shorter than the first width,
A semiconductor device comprising: a transistor including: The semiconductor device according to claim 1,
The third semiconductor region is
A first impurity region located under the first conductive film on the surface of the semiconductor substrate outside the trench and overlapping the first conductive film; and the first impurity region than the first impurity region. A second impurity region that is separated from the trench in the direction of 2 by the first width, is in contact with the first impurity region, and has a higher impurity concentration than the first impurity region;
A semiconductor device comprising: The semiconductor device according to claim 1 or 2 ,
The first conductive film is a polysilicon film doped with impurities,
The semiconductor device, wherein the second conductive film is a silicide film.

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