CN107910266B - Power semiconductor device and method of manufacturing the same - Google Patents

Abstract

The application discloses a power semiconductor device and a method of manufacturing the same. The method comprises the following steps: forming an insulating stack on sidewalls and bottoms of the plurality of trenches, the insulating stack comprising a first insulating layer and a second insulating layer, the first insulating layer surrounding the second insulating layer; filling shielding conductors in the plurality of trenches; forming openings on two sides of the shielding conductor at the upper parts of the plurality of grooves; forming a gate dielectric on sidewalls of upper portions of the plurality of trenches; forming a gate conductor to fill the opening; wherein the gate conductor and the shield conductor are isolated from each other by at least one layer of the insulating stack, the gate conductor and the body region are isolated from each other by the gate dielectric, and the shield conductor and the semiconductor substrate are isolated from each other by the insulating stack. The method forms an isolation layer on top of the shield conductor to avoid gate-source shorting.

Description

Power semiconductor device and manufacturing method thereof

Technical field

The present invention relates to the technical field of electronic devices, and more specifically, to power semiconductor devices and manufacturing methods thereof.

Background technique

Power semiconductor devices are also called power electronic devices, including power diodes, thyristors, VDMOS (vertical double diffused metal oxide semiconductor) field effect transistors, LDMOS (lateral diffused metal oxide semiconductor) field effect transistors, and IGBT (insulated gate bipolar) transistor) etc. The VDMOS field effect transistor includes a source region and a drain region formed on opposite surfaces of a semiconductor substrate. In the conductive state, current mainly flows along the longitudinal direction of the semiconductor substrate.

In the high-frequency application of power semiconductor devices, lower conduction loss and switching loss are important indicators for evaluating device performance. On the basis of VDMOS field effect transistors, trench-type MOS field effect transistors are further developed, in which a gate conductor is formed in the trench, and a gate dielectric is formed on the sidewalls of the trench to separate the gate conductor and the semiconductor layer. , thereby forming a channel in the semiconductor layer along the direction of the trench sidewall. The trench process changes the channel from horizontal to vertical, eliminating the influence of the parasitic JFET resistance of the planar structure and greatly reducing the cell size. On this basis, increasing the unit cell density and increasing the total channel width per unit area of the chip can increase the channel width-to-length ratio of the device on the unit silicon wafer, thereby increasing the current, reducing the on-resistance and related parameters. It has been optimized to achieve the goal of smaller-sized dies with greater power and high performance, so trench processes are increasingly used in new power semiconductor devices.

However, as the unit density increases, the inter-electrode resistance will increase, and the switching loss will increase accordingly. The gate-to-drain capacitance Cgd is directly related to the switching characteristics of the device. In order to reduce the gate-to-leak capacitance Cgd, the split gate trench (Split Gate Trench, abbreviated as SGT) type power semiconductor device has been further developed, in which the gate conductor extends to the drift region, and a thick oxide is used between the gate conductor and the drain. It is separated by objects, thereby reducing the gate-drain capacitance Cgd, increasing the switching speed and reducing switching losses. At the same time, the shield conductor under the gate conductor is connected to the source electrode and is grounded together, thus introducing a charge balance effect and reducing the surface electric field (Reduced Surface Field, abbreviated as RESURF) in the vertical direction of the power semiconductor device. ) effect, further reducing the on-resistance Rdson, thereby reducing the conduction loss.

1a and 1b respectively show cross-sectional views of the main steps of a manufacturing method of an SGT power semiconductor device according to the prior art. As shown in FIG. 1a, a trench 102 is formed in the semiconductor substrate 101. The first insulating layer 103 is formed in the lower part of the trench 102, and the shielding conductor 104 fills the trench 102. In the upper part of the trench 102, two openings separated by the shield conductor 104 are formed. Further, as shown in FIG. 1 b , a gate dielectric 105 is formed on the upper sidewall of the trench 102 and the exposed portion of the shield conductor 104 , and then the conductive material is filled in the two openings separated by the shield conductor 104 to form two Gate conductor 106.

In the SGT power semiconductor device, the shielding conductor 104 is connected to the source electrode of the power semiconductor device for generating the RESURF effect. Two gate conductors 106 are located on either side of the shield conductor 104 . The shield conductor 104 is separated from the drain region of the power semiconductor device by a first insulating layer 103 and from the gate electrode 106 by a gate dielectric 105 . Gate conductor 106 is separated from the well region in semiconductor substrate 101 by gate dielectric 105, thereby forming a channel in the well region. As shown, the thickness of first insulating layer 103 is less than the thickness of gate dielectric 105 .

According to the SGT theory, no matter which SGT structure is used, the material of the shielding conductor 104 needs to be isolated from the second conductive material and the material used for isolation needs to meet certain capacitance parameters. Otherwise, failures such as gate-source short circuit and abnormal gate-drain capacitance Cgd will easily occur. . How to optimize the device structure and meet the product parameters and reliability requirements, while making the wiring method the most efficient and low-cost is what those in this technical field need to study.

Contents of the invention

In view of the above problems, an object of the present invention is to provide a power semiconductor device and a manufacturing method thereof, in which an isolation layer is formed on top of a shielding conductor to avoid gate-source short circuit, thereby improving reliability.

According to an aspect of the present invention, a method for manufacturing a power semiconductor device is provided, including: forming a plurality of trenches in a first doping type semiconductor substrate; forming on sidewalls and bottoms of the plurality of trenches An insulating stack, the insulating stack includes a first insulating layer and a second insulating layer, the first insulating layer surrounds the second insulating layer; shielding conductors are filled in the plurality of trenches, and the shielding A first opening is formed on the top of the conductor; a second opening is formed on both sides of the shield conductor in the upper part of the plurality of trenches, and the second opening exposes the side walls of the upper part of the plurality of trenches; in the Forming an isolation layer in the first opening and the second opening; forming a gate dielectric on the sidewalls of the upper portions of the plurality of trenches; forming a gate conductor to fill the second opening; adjoining the semiconductor substrate A body region of a second doping type is formed in the region of the trench, the second doping type being opposite to the first doping type; a source region of the first doping type is formed in the body region; and forming a source electrode and a gate electrode, the source electrode is electrically connected to the source region and the shield conductor, the gate electrode is electrically connected to the gate conductor, wherein the gate conductor is The shield conductors are isolated from each other by at least one layer of the insulating stack, the gate conductor and the body region are isolated from each other by the gate dielectric, and the shield conductor and the semiconductor liner are isolated from each other. The bases are isolated from each other by the insulating laminate.

Preferably, a planarization step is further included between the steps of filling the shielding conductor and the step of forming the second opening.

Preferably, before the planarization step, the shielding conductor, the first insulating layer and the second insulating layer respectively include first portions located in the plurality of trenches and laterally on the surface of the semiconductor substrate. The extended second portion, in the planarization step, uses the first insulating layer as a stop layer to remove the respective second portions of the shielding conductor and the second insulating layer, so that the shielding conductor and the The top ends of the respective first portions of the second insulating layer are flush with the surface of the first insulating layer.

Preferably, in the step of forming the second opening, a portion of the first portion of the first insulating layer located above the plurality of trenches is removed, so that the shielding conductor extends upward from the surface of the semiconductor substrate by a predetermined height. .

Preferably, the step of forming the gate conductor includes depositing a first conductive layer to fill the second opening, the first conductive layer including a first portion located in the second opening and on a surface of the semiconductor substrate a laterally extending second portion; and patterning the second portion of the gate layer conductor into a wiring.

Preferably, in the patterning step, the second portion of the first conductive layer is completely removed in the first region of the semiconductor substrate, and the second portion of the first conductive layer is partially removed in the second region of the semiconductor substrate. A second portion of a conductive layer is removed from the second portion of the gate conductor in the first region of the semiconductor substrate.

Preferably, the source electrode is located in the first region, the gate electrode is located in the second region, and the first region and the second region are spaced apart from each other.

Preferably, the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride or polysilicon.

Preferably, the plurality of grooves have a width in a range of 0.2 to 10 microns and a depth in a range of 0.1 to 50 microns.

Preferably, the first doping type is one of N-type and P-type, and the second doping type is the other one of N-type and P-type.

Preferably, the side walls of the plurality of grooves are inclined such that the top width of the plurality of grooves is greater than the bottom width of the plurality of grooves.

Preferably, the steps of filling the shield conductor and forming the gate conductor each comprise at least one deposition.

According to another aspect of the present invention, a power semiconductor device is provided, including: a plurality of trenches located in a semiconductor substrate, the semiconductor substrate being a first doping type; and a body region located in the semiconductor substrate , the body region is adjacent to the upper portions of the plurality of trenches and is of a second doping type, and the second doping type is opposite to the first doping type; the source region located in the body region, The source region is a first doping type; an insulating stack located at the lower sidewalls and bottom of the plurality of trenches, the insulating stack includes a first insulating layer and a second insulating layer, and the first insulating layer surrounds the second insulating layer; at least a portion of a shielding conductor located in the plurality of trenches, the shielding conductor extending from above the plurality of trenches to the bottom thereof, and between the shielding conductor and the semiconductor substrate by the Insulation stacks are isolated from each other; gate conductors on both sides of the shield conductor in upper portions of the plurality of trenches; source electrodes electrically connected to the source region and the shield conductor; and to the gate electrode A gate electrode electrically connected by a conductor, wherein the gate conductor and the shield conductor are isolated from each other by at least one layer of the insulating stack, and the gate conductor and the body region are separated by the The gate dielectrics are isolated from each other, and the shield conductor and the semiconductor substrate are isolated from each other by the insulating stack.

Preferably, the shielding conductor extends upwardly from the semiconductor substrate surface by a predetermined height.

Preferably, the gate conductor further includes a second portion extending laterally on the surface of the semiconductor substrate, and the second portion of the gate layer conductor serves as a wiring such that the source electrode and the gate electrode separated from each other.

Preferably, the source electrode is located in the first region, and the gate electrode is located in the second region.

Preferably, the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride or polysilicon.

Preferably, the plurality of grooves have a width in a range of 0.2 to 10 microns and a depth in a range of 0.1 to 50 microns.

Preferably, the first doping type is one of N-type and P-type, and the second doping type is the other one of N-type and P-type.

Preferably, the side walls of the plurality of grooves are inclined such that the top width of the plurality of grooves is greater than the bottom width of the plurality of grooves.

Preferably, the power semiconductor device is one selected from the group consisting of CMOS devices, BCD devices, MOSFET transistors, IGBTs and Schottky diodes.

In a method according to an embodiment of the present invention, an SGT structure is formed in a power semiconductor device, wherein an insulating stack is formed between a shield conductor and a semiconductor substrate, thereby reducing gate-to-drain capacitance Cgd. Further, a doping region with a doping type opposite to that of the semiconductor substrate is formed at the bottom of the trench. During the operation of the power semiconductor device, carriers in the doped region and the semiconductor substrate are mutually depleted, thereby making full use of the electrical balance theory to further reduce the gate-to-drain capacitance Cgd. This step can directly employ the photoresist mask used to form the trenches, which can reduce process complexity and reduce manufacturing costs.

In a preferred embodiment, the gate conductor includes a first portion located in the trench and a second portion serving as a wiring layer, the second portion being connected to said first portion and extending laterally on the semiconductor substrate. The second part of the gate conductor serves as a wiring layer so that the gate electrode can be located away from the source electrode, thereby improving the reliability of the power semiconductor device. Furthermore, this method does not require the use of additional conductive layers for rewiring the gate electrode, thereby reducing process complexity and manufacturing costs.

In a preferred embodiment, the shielding conductor extends upwardly from the semiconductor substrate surface a predetermined height (which height is approximately equal to the thickness of the first insulating layer). In the step of forming the gate conductor, the gate conductor covers the shield conductor. Then, in an etching step, over the first region of the semiconductor substrate, the portion of the gate conductor over the shield conductor can be completely removed. Further, an isolation layer is formed on top of the shield conductor. This design can improve the reliability of the power semiconductor device, thereby avoiding a short circuit between the gate and source of the power semiconductor device, that is, avoiding the formation of a short circuit path starting from the source area, passing through the source electrode, shielding conductor, contact hole, and reaching the gate electrode. .

This method realizes the SGT structure through relatively simple process steps, solves the problems of complicated processes in conventional processes, prone to gate-source short circuit, abnormal gate-drain capacitance Cgd, etc., thereby meeting the parameters and reliability requirements of the product, and combines the wiring with specific process steps. The method is the most efficient and low-cost. Compared with the existing technology, based on the 0.25-0.35um process, this method can reduce the number of photoresist masks used in the current manufacturing process by 3 to 4 photoresist masks.

The split-gate power semiconductor device structure and formation method adopted in the embodiment of the present invention to reduce source-drain capacitance can also be applied to CMOS, BCD, power MOSFET, high-power transistor, IGBT, Schottky and other products.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

1a and 1b respectively show cross-sectional views of main steps of a manufacturing method of a power semiconductor device according to the prior art.

FIG. 2 shows a flow chart of a manufacturing method of a power semiconductor device according to an embodiment of the present invention.

3a to 3i illustrate cross-sectional views at different stages of a semiconductor device manufacturing method according to embodiments of the present invention.

Detailed ways

The invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, identical elements are designated with similar reference numerals. For the sake of clarity, parts of the figures are not drawn to scale. Additionally, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It should be understood that, when describing the structure of a device, when one layer or region is referred to as being "on" or "over" another layer or region, it can mean that it is directly on the other layer or region, or There are other layers or areas between it and another layer, another area. And if the device is turned over, that layer or region will be "below" or "under" another layer or region.

If we want to describe a situation that is directly above another layer or another area, this article will use the expression "A is directly above B" or "A is above B and adjacent to it". In this application, "A is directly located in B" means that A is located in B, and A is adjacent to B, rather than A being located in the doped region formed in B.

In this application, the term "semiconductor structure" refers collectively to the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.

Many specific details of the present invention are described below, such as device structures, materials, dimensions, processing processes and techniques, in order to provide a clearer understanding of the present invention. However, as one skilled in the art will appreciate, the invention may be practiced without these specific details.

Unless otherwise specified below, various portions of the semiconductor device may be constructed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and Group IV semiconductors, such as Si, Ge.

2 shows a flow chart of a manufacturing method of an SGT power semiconductor device according to an embodiment of the present invention, and FIGS. 3a to 3i respectively show cross-sectional views in different steps. The steps of the manufacturing method according to the embodiment of the present invention are described below in conjunction with Figures 2 and 3a to 3i.

The method begins with a semiconductor substrate 101 . The semiconductor substrate is, for example, a silicon substrate doped to N type. The longitudinal doping of the silicon substrate is uniform, and the resistivity is, for example, in the range of 1 to 15Ω·cm. The semiconductor substrate has opposing first and second surfaces. Preferably, a voltage dividing ring structure of the power semiconductor is formed on the first surface of the semiconductor substrate through photolithography, etching, ion implantation, impurity activation and other processes. The voltage dividing ring structure is a well-known device structure in this field. The structural part will not be described in detail here. Preferably, the semiconductor substrate 101 used in this embodiment can be formed with semiconductor devices such as MOS field effect transistors, IGBT insulated gate field effect transistors, and Schottky diodes.

In step S101, trenches 102 are respectively formed in the first region 201 and the second region 202 of the semiconductor substrate 101, as shown in FIG. 3a.

The process for forming the trench 102 includes forming a resist mask by photolithography and etching, and etching to remove the exposed portion of the semiconductor substrate 101 through openings of the resist mask.

In this embodiment, the first region 201 refers to the wiring region of the source region and the shield conductor in the SGT structure, and the second region 202 refers to the wiring region of the gate conductor in the SGT structure.

The trench 102 extends downwardly from the surface of the semiconductor substrate 101 and reaches a predetermined depth in the semiconductor substrate 101 . In this embodiment, the width of the trench 102 is, for example, 0.2 to 10 microns, and the depth is, for example, 0.1 to 50 microns. The width of the trench of the SGT structure is much wider than that of conventional trench power semiconductor devices with the same conduction efficiency level, and the depth of the trench is also much deeper than that of conventional trench power semiconductor devices.

Preferably, the side walls of the trench 102 are sloped, for example at an angle of 85 to 89 degrees relative to the top of the vertical trench 102, such that the bottom width of the trench 102 is less than the top width. The angle of the trench is relatively oblique, which facilitates the subsequent filling of dielectric layers and conductive materials, and reduces problems such as defects caused by filling gaps.

In step S102, an insulating stack including a conformal first insulating layer 122 and a second insulating layer 123 is sequentially formed on the surface of the semiconductor substrate 101, as shown in FIG. 3b.

In the trench 102, the first insulating layer 122 surrounds the second insulating layer 123. The first insulation layer 122 and the second insulation layer 123 are composed of different insulation materials. In this embodiment, the first insulating layer 122 is composed of silicon oxide, for example. The second insulating layer 123 is composed of, for example, at least one selected from silicon nitride, oxynitride, or polysilicon. Preferably, the second insulating layer 123 is composed of silicon nitride. The thickness of the first insulating layer 122 is, for example, 500 to 50,000 angstroms, and the thickness of the second insulating layer 123 is, for example, 50 to 5,000 angstroms. The greater the thickness of the first insulating layer 122, the smaller the gate-to-drain capacitance Cgd.

The process for forming the first insulating layer 122 includes forming an oxide layer on the inner wall of the trench 102 through thermal oxidation, chemical vapor deposition (CVD) or high-density plasma chemical vapor deposition. The oxide layer conformally covers the sidewalls and bottom of trench 102 so that a portion of the interior space of trench 102 is still preserved.

The process for forming the second insulating layer 123 includes forming a nitride layer on the surface of the first insulating layer 122 through chemical vapor deposition (CVD) or high-density plasma chemical vapor deposition. The nitride layer conformally covers the surface of the first insulating layer 122 so that a portion of the interior space of the trench 102 is still retained.

In step S103, a shield conductor 104 is formed in the trench 102, as shown in Figure 3c.

The shielding conductor 104 consists, for example, of doped amorphous silicon or polycrystalline silicon. The process for forming the shield conductor 104 includes, for example, using a process such as sputtering to deposit polysilicon so that the remaining portion of the trench 102 is filled with the polysilicon, and using chemical mechanical planarization (CMP) to remove the polysilicon outside the trench 102 so that the trench is filled. 102 of polysilicon forms shield conductor 104.

The deposition rate of the polysilicon is, for example, 1 to 100 angstroms per minute, the deposition temperature is, for example, 510 to 650 degrees Celsius, and the thickness is, for example, 1,000 to 100,000 angstroms. By controlling the doping concentration of shield conductor 104, its resistance can be adjusted. In this embodiment, the sheet resistance Rs of the shielding conductor 104 is less than 20 ohms, for example. Furthermore, the smaller the sheet resistance Rs of the shielding conductor 104 is, the greater the thickness of the oxide layer formed in the subsequent oxidation process is compared with silicon. Furthermore, if the material of the shielding conductor 104 is amorphous, it is easier to form a lower sheet resistance Rs.

In the above deposition steps, the material forming the shield conductor 104 may be deposited one or more times. When depositing multiple times, the rate of subsequent deposition steps is smaller than that of the previous deposition step, so the deposition rate gradually decreases. During the trench filling process, the slower the deposition rate, the better the filling effect. The bottom of the trench is more difficult to fill than the top of the trench. Therefore, when filling multiple times, the rate of previous deposition needs to be smaller than the rate of any subsequent deposition.

In the above chemical mechanical planarization step, the first insulating layer 122 is used as a stop layer, thereby not only removing the portion of the polysilicon outside the trench 102 , but also removing the portion of the second insulating layer 123 outside the trench 102 . Therefore, the tops of the shield conductor 104 and the second insulation layer 123 are flush with the surface of the first insulation layer 122 .

Preferably, a portion of the polysilicon is etched away from the top of the shield conductor 104 to form the first opening 1241 .

The etching process is, for example, dry etching. Due to the selectivity of the etchant, the exposed portions of shield conductor 104 are removed relative to first insulating layer 122 and second insulating layer 123 , thereby etching back a portion of the polysilicon of shield conductor 104 to form opening 1241 . The opening 1241 is used to provide a receiving space for the isolation layer, thereby improving the mechanical strength of the isolation layer.

In step S104 , a portion of the first insulating layer 122 is removed by etching, thereby forming second openings 1242 on both sides of the shielding conductor 104 in the upper part of the trench 102 , and filling the first opening 1241 and the second opening 1242 with the isolation layer 131 , as shown in Figure 3d. The second opening 1242 re-exposes the upper sidewall of the trench 102 .

The etching process is, for example, wet etching. Due to the selectivity of the etchant, the exposed portions of the first insulating layer 122 are removed with respect to the semiconductor substrate 101 , the second insulating layer 123 and the shielding conductor 104 . This etching not only removes the portion of the first insulating layer 122 located outside the trench 102 , but also etches back the portion of the first insulating layer 122 located inside the trench 102 , thereby exposing the surface of the semiconductor substrate 101 . The height of the portion of the second insulating layer 123 and the shielding conductor 104 extending upward from the surface of the semiconductor substrate 101 corresponds to the thickness of the first insulating layer 122, for example, 500 to 50,000 angstroms. The extended height facilitates the subsequent contact hole drilling process. The depth of the first insulating layer 122 extending downward from the top of the semiconductor substrate 101 is, for example, 0.5 to 5 microns. After etching, a portion of the first insulating layer 122 located at the lower sidewalls and the bottom of the trench 102 remains, so that the lower portion of the shielding conductor 104 and the semiconductor substrate 101 are still isolated from each other by the insulating stack.

The process for forming the isolation layer 131 includes thermal oxidation, chemical vapor deposition (CVD), or high-density plasma chemical vapor deposition. In this embodiment, the isolation layer 131 is composed of silicon oxide, for example. In this step, the isolation layer 131 is formed not only in the first opening 1241 but also in the second opening 1242 . Therefore, the thickness of the isolation layer 131 is selected such that the isolation layer 131 only fills a part of the depth of the second opening 1242 so that the space of the second opening 1242 can further accommodate the gate conductor. The thickness of the isolation layer 131 is, for example, 500 to 5000 angstroms. After the isolation layer 131 is formed, the depth of the second opening 1242 is preferably 0.5 to 5 microns. In step S105, gate dielectric 105 is formed on the upper sidewalls of trench 102 and on top of shield conductor 104, as shown in Figure 3e.

The process used to form gate dielectric 105 may employ thermal oxidation. The temperature of the thermal oxidation is, for example, 950 to 1200 degrees Celsius. The exposed silicon material of semiconductor substrate 101 and shield conductor 104 forms silicon oxide during a thermal oxidation process. In the thermal oxidation step, the surface of the semiconductor substrate 101 is also exposed to the atmosphere. Gate dielectric 105 not only covers the upper sidewalls of trench 102 but also covers the surface of semiconductor substrate 101 .

Compared with the dense semiconductor substrate 101, the shielding conductor 104 is a heavily doped amorphous or polycrystalline material with a looser structure and a higher doping concentration. As a result, the thickness of the second portion of the gate dielectric 105 located on the surface of the shield conductor 104 is greater than the thickness of the first portion located on the surface of the semiconductor substrate 101 and in the trench 102 . The thickness of the first portion of the gate dielectric 105 is, for example, 50 to 5,000 angstroms, and the thickness of the second portion is, for example, 60 to 10,000 angstroms.

In step S106, a gate conductor 106 is formed in the trench, and a body region 107 and a source region 108 are formed in a region of the semiconductor substrate 101 adjacent to the trench 102, as shown in FIG. 3f.

Gate conductor 106 consists, for example, of doped amorphous silicon or polycrystalline silicon. The process for forming the gate conductor 106 includes, for example, depositing polysilicon using a process such as sputtering, so that the polysilicon fills the second openings 1242 on both sides of the shield conductor 104 .

The deposition rate of the polysilicon is, for example, 1 to 100 angstroms per minute, the deposition temperature is, for example, 510 to 650 degrees Celsius, and the thickness is, for example, 1,000 to 100,000 angstroms. By controlling the doping concentration of gate conductor 106, its resistance can be adjusted. In this embodiment, the sheet resistance Rs of the gate conductor 106 is less than 20 ohms, for example. Furthermore, the smaller the sheet resistance Rs of the gate conductor 106 is, the greater the thickness of the oxide layer formed in the subsequent oxidation process is compared with silicon. Furthermore, if the material of the gate conductor 106 is amorphous, it is easier to form a lower sheet resistance Rs.

In the above-described deposition steps, the material forming the gate conductor 106 may be deposited one or more times. When depositing multiple times, the rate of subsequent deposition steps is smaller than that of the previous deposition step, so the deposition rate gradually decreases. During the trench filling process, the slower the deposition rate, the better the filling effect. The bottom of the trench is more difficult to fill than the top of the trench. Therefore, when filling multiple times, the rate of previous deposition needs to be smaller than the rate of any subsequent deposition.

Next, a resist mask is formed by photolithography and etching, and a portion located above the first region of the semiconductor substrate 101 is removed by etching through the opening of the resist mask, so that the shield conductor 104 is in the second region of the semiconductor substrate 101 extends horizontally above the area.

Next, a P-type body region 107 is formed in the semiconductor substrate 101 , and an N-type source region is formed in the body region 107 . The process used to form the body region 107 and the source region 108 is, for example, multiple ion implantations. Different types of doped regions are formed by selecting appropriate dopants, followed by thermal annealing to activate the impurities. During ion implantation, the shield conductor 104 and the gate conductor 106 are used as a hard mask to define the lateral positions of the body region 107 and the source region 108, thereby eliminating the need for a photoresist mask. The angle of the ion implantation is, for example, zero angle, that is, the ion implantation is perpendicular to the surface of the semiconductor substrate 101 . By controlling the energy of ion implantation, the implantation depth of the body region 107 and the source region 108 can be defined, thereby defining the vertical position.

When forming the body region 107, the dopant used is B11 or BF2, or B11 can be injected first and then BF2. The implantation energy is 20 to 100Kev, the implantation dose is 1E14 to 1E16, and the thermal annealing temperature is 500 to 1000 degrees Celsius. When forming the source region 108, the dopant used is P+ or AS+, the implantation energy is 60-150Kev, the implantation dose is 1E14-1E16, and the thermal annealing temperature is 800-1100 degrees Celsius.

In this step, an SGT structure is formed in trench 102, including shield conductor 104 and gate conductor 106 located in the trench. Gate conductor 106 includes a first portion located in trench 102 and a second portion extending over semiconductor substrate 101 . A first portion of the gate conductor 106 is formed in the second opening 1242 on either side of the shield conductor 104 so that the shield conductor 104 is sandwiched. The shield conductor 104 and the gate conductor 106 are isolated from each other by the second insulation layer 123 . The lower part of the shield conductor 104 extends to the lower part of the trench 102 and is isolated from the semiconductor substrate 101 by an insulating stack including a first insulating layer 122 and a second insulating layer 123 . Gate conductor 106 is adjacent body region 107 and source region 108 and are isolated from each other by gate dielectric 105 .

The isolation layer 131 and the second insulating layer 123 formed in the above steps together surround the shielding conductor 104 , further improving the isolation between the shielding conductor 104 and the gate conductor 106 , thereby avoiding the occurrence of interference between the shielding conductor 104 and the gate conductor 106 . Source-drain short circuit improves reliability.

In step S107, an interlayer dielectric layer 109 is deposited on the surface of the semiconductor structure, as shown in FIG. 3g.

The interlayer dielectric layer 109 covers the first region and the second region of the semiconductor substrate 101. The interlayer dielectric layer 109 may be composed of at least one selected from silicon dioxide, silicon nitride, and silicon oxynitride, and may be a single layer. or laminated structure. In this embodiment, the interlayer dielectric layer 109 may be, for example, borophosphosilicate glass (BPSG) with a thickness of 2,000 to 15,000 angstroms.

In step S108 , a plurality of contact holes 125 reaching the source region 108 , the gate conductor 106 and the shield conductor 104 are formed in the interlayer dielectric layer 109 , and contact regions 110 are respectively formed at the bottoms of the plurality of contact holes 125 through ion implantation. , as shown in Figure 3h.

The process for forming the contact hole 125 is, for example, dry etching. The sidewalls of the contact hole 125 are sloped, for example at an angle of 85 to 89.9 degrees relative to the top of the vertical trench 102, such that the bottom width of the contact hole 125 is smaller than the top width. The contact hole 125 has an oblique angle, which facilitates subsequent filling of conductive materials and reduces problems such as defects caused by filling gaps.

In the first region 201 of the semiconductor substrate 101 , a first set of the plurality of contact holes 125 sequentially passes through the interlayer dielectric layer 109 and the gate dielectric 105 to a predetermined depth in the shield conductor 104 , and a second The set of contact holes sequentially passes through the interlayer dielectric layer 109 , the gate dielectric 105 , and the source region 108 to a predetermined depth in the body region 107 . The predetermined depth is, for example, 0.1 to 1 micron.

In the second region 202 of the semiconductor substrate 101 , a third group of contact holes among the plurality of contact holes 125 sequentially pass through the interlayer dielectric layer 109 and extend to a predetermined depth in the gate conductor 106 .

During ion implantation, the interlayer dielectric layer is used as a hard mask to define the lateral position of the contact region 110, thereby eliminating the need for a photoresist mask. The dopant used in this ion implantation is B11 or BF2, or B11 can be injected first and then BF2. The implantation energy is 20 to 100Kev, the implantation dose is 1E14 to 1E16, and the thermal annealing temperature is 500 to 1000 degrees Celsius. After ion implantation, a thermal anneal can be performed to activate the dopants.

Further, in the second region 202 of the semiconductor substrate 101 , the gate conductor 106 not only includes the first and second portions filling the trench 102 , but also includes a third portion laterally extending from the trench 102 on the surface of the semiconductor substrate 101 . part. This third part serves as a wiring layer. This is mainly due to the limited trench width of power semiconductor devices. After the shield conductor 104 within the trench forms contact holes, the contact holes in the first region 201 of the semiconductor substrate 101 are densely populated. In order to improve the electrical isolation between the source region 108 and the gate conductor 106, the third portion of the gate conductor 106 is used as a wiring layer, so that among the plurality of contact holes 125, the contact hole for the source region can be far away from the gate. The contact hole of the conductor 106 thereby reduces the process difficulty and improves the reliability of the power semiconductor device.

In step S109, the source electrode 111 and the gate electrode 112 are formed, as shown in FIG. 3i.

This step includes, for example, depositing a metal layer and patterning. The metal layer is composed of, for example, one selected from Ti, TiN, TiSi, W, AL, AlSi, AlSiCu, Cu, Ni or an alloy thereof. The metal layer is patterned into the source electrode 111 and the gate electrode 112 by etching. As shown, source electrode 111 and gate electrode 112 are isolated from each other.

In the first region 201 of the semiconductor substrate 101 , the source electrode 111 reaches the shield conductor 104 via a first set of the plurality of contact holes 125 , via a second set of the plurality of contact holes 125 . The holes reach source region 108, thereby electrically connecting source region 108 and shield conductor 104 to each other. In the second region 202 of the semiconductor substrate 101 , the gate electrode 112 reaches the gate conductor 106 via a third set of the plurality of contact holes 125 .

After step S109, metallization of the power semiconductor device has been achieved. Furthermore, according to the needs of the product, passivation layer protection can be added to complete the processing of the front structure of the power semiconductor device. After a series of back-end processes such as thinning, gold backing, and dicing, the device is finally realized.

It should be noted that although in the above-mentioned cross-sectional view, the shield conductors 104 in different trenches are isolated from each other and the gate conductors 106 are isolated from each other, in an actual power semiconductor device, when viewed from a planar structure, the above-mentioned different trenches are isolated from each other. The shield conductors 104 may be connected to each other, and the gate conductors 106 may also be connected to each other. In one embodiment, the connection method is, for example, that the gate conductors 106 in different trenches 102 are integrally formed by a single conductive layer, and the shield conductors 104 in different trenches 102 are integrally formed by a single conductive layer. In an alternative embodiment, the connection is, for example, using a common source electrode to connect the shield conductors 104 in different trenches 102 to each other, and using a common gate electrode to connect the gate conductors 106 in different trenches 102 to each other. connect.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations are mutually exclusive. any such actual relationship or sequence exists between them. Furthermore, the terms "comprises," "comprises," or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed other elements, or elements inherent to the process, method, article or equipment. Without further limitation, an element qualified by the statement "comprises a..." does not exclude the presence of additional identical elements in the process, method, article, or device that includes the element.

According to the above embodiments of the present invention, these embodiments do not exhaustively describe all the details, nor do they limit the invention to only specific embodiments. Obviously, many modifications and variations are possible in light of the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and make modifications based on the present invention. The invention is limited only by the claims and their full scope and equivalents.

Claims (12)

1. A method of manufacturing a power semiconductor device, comprising: forming a plurality of trenches in the first doped type semiconductor substrate; forming an insulating stack on sidewalls and bottoms of the plurality of trenches, the insulating stack including a first insulating layer and a second insulating layer, the first insulating layer surrounding the second insulating layer; Filling the plurality of trenches with shielding conductors, forming a first opening on the top of the shielding conductor, the shielding conductor and the semiconductor substrate being isolated from each other by the insulating stack; Etching the first insulating layer in the upper portion of the plurality of trenches to form second openings located on both sides of the shield conductor, the second opening exposing sidewalls in the upper portion of the plurality of trenches; forming an isolation layer in the first opening and the second opening, the isolation layer being respectively located above the shielding conductor and the first insulating layer; forming a gate dielectric on sidewalls of upper portions of the plurality of trenches; A gate conductor is formed to fill the second opening, a portion of the gate conductor extends laterally from the second opening to above the surface of the semiconductor substrate to form a wiring layer, between the wiring layer and the shielding conductor Isolated from each other by the isolation layer, the wiring layer and the semiconductor substrate are isolated from each other by the gate dielectric, and the sidewalls of the gate conductor and the shield conductor are isolated from each other by the second insulation Layers are isolated from each other; forming a body region of a second doping type in a region of the semiconductor substrate adjacent to the trench, the second doping type being opposite to the first doping type; forming a source region of the first doping type in the body region; and forming a source electrode and a gate electrode, the source electrode being electrically connected to the source region and the shield conductor, and the gate electrode being electrically connected to the gate conductor, Wherein, the wiring layer extends laterally so that the contact hole of the gate electrode is away from the contact hole of the source electrode. In the step of forming the source region, the wiring layer serves as a hard mask so that the contact hole below the wiring layer No source region is formed in the semiconductor substrate. 2. The manufacturing method according to claim 1, further comprising a planarization step between the steps of filling the shielding conductor and the step of forming the second opening. 3. The manufacturing method according to claim 2, wherein before the planarization step, the shielding conductor, the first insulating layer and the second insulating layer respectively comprise a third insulating layer located in the plurality of trenches. a portion and a second portion extending laterally on the surface of said semiconductor substrate, In the planarization step, using the first insulating layer as a stop layer, the respective second portions of the shielding conductor and the second insulating layer are removed, so that the respective second portions of the shielding conductor and the second insulating layer A portion of the top end is flush with the surface of the first insulating layer. 4. The manufacturing method according to claim 3, wherein in the step of forming the second opening, a portion of the first portion of the first insulating layer located above the plurality of trenches is removed, so that the shielding conductor is removed from The semiconductor substrate surface extends upward by a predetermined height. 5. The manufacturing method of claim 1, wherein forming the gate conductor includes: Depositing a first conductive layer to fill the second opening, the first conductive layer including a first portion located in the second opening and a second portion extending laterally from the second opening toward the surface of the semiconductor substrate. part; and The second portion of the first conductive layer is patterned into a wiring layer. 6. The manufacturing method of claim 5, wherein in the patterning step, the second portion of the first conductive layer is completely removed in the first region of the semiconductor substrate. In the second region, a second portion of the first conductive layer is partially removed. 7. The manufacturing method according to claim 6, wherein the source electrode is located in the first region, the gate electrode is located in the second region, the first region and the second region Areas are separated from each other. 8. The manufacturing method according to claim 1, wherein the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride and oxynitride. 9. The manufacturing method of claim 1, wherein the plurality of trenches have a width in a range of 0.2 to 10 microns and a depth in a range of 0.1 to 50 microns. 10. The manufacturing method according to claim 1, wherein the first doping type is one of N type and P type, and the second doping type is the other one of N type and P type. . 11. The manufacturing method of claim 1, wherein side walls of the plurality of trenches are inclined such that a top width of the plurality of trenches is greater than a bottom width of the plurality of trenches. 12. The manufacturing method of claim 1, wherein filling the shield conductor and forming the gate conductor each comprise at least one deposition.