CN106601811B - Trench type power transistor - Google Patents

Abstract

A trench power transistor. The trench gate structure of the trench power transistor is located in an element trench of an epitaxial layer and at least comprises a shielding electrode, a gate electrode and an insulating layer. The insulating layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the third dielectric layer is positioned at the lower half part of the element groove, part of the second dielectric layer positioned at the lower half part of the element groove is clamped between the first dielectric layer and the third dielectric layer, and the dielectric constant of the second dielectric layer is larger than that of the first dielectric layer.

Description

Trench Power Transistor

technical field

The present invention relates to a power transistor, in particular to a trench type power metal oxide semiconductor field effect transistor with shielding electrodes.

Background technique

Power metal oxide semiconductor field effect transistors (Power Metal Oxide Semiconductor Field Transistor, Power MOSFET) are widely used in switching elements of power devices, such as power supplies, rectifiers, or low-voltage motor controllers. Today's power metal oxide semiconductor field effect transistors are mostly designed with a vertical structure to increase the device density. This type of power metal oxide semiconductor field effect transistor with vertical structure design is also called trench power metal oxide semiconductor field effect transistor. .

The operating losses of power MOSFETs can be divided into two categories: switching loss and conducting loss, of which the gate/drain capacitance (Cgd) is an important parameter that affects switching loss. . Too high gate/drain capacitance will increase the switching loss, which will limit the switching speed of the power metal-oxide-semiconductor field-effect transistor, which is not conducive to application in high-frequency circuits.

In order to improve the above problems and reduce the gate/drain capacitance, in the conventional power MOSFET, a shielding electrode is additionally formed in the lower half of the gate trench.

However, in the process of fabricating a trench-type power MOSFET with a shielding electrode structure, after the shielding electrode located in the lower half of the gate trench is formed, it is usually pre-formed in the gate trench. The dielectric layer on the sidewalls of the upper half of the trench is etched away and a new gate dielectric layer is redeposited. However, in the process of etching the dielectric layer, it is difficult to control the etching depth of the dielectric layer, resulting in the formation of holes or holes between the subsequently formed gate dielectric layer and the dielectric layer located on the sidewall of the lower half of the gate trench. gap. When a voltage is applied to the gate of the trench power metal oxide semiconductor field effect transistor, these holes or gaps may cause leakage current between the gate and source, which makes the trench power metal oxide semiconductor field effect transistor. Field effect transistors do not perform well electrically.

SUMMARY OF THE INVENTION

The present invention provides a trench-type power transistor, which is formed by forming an oxide layer and a nitride layer on the inner wall surface of the trench and the surface of the epitaxial layer in the manufacturing process of the trench-type power transistor without removing the oxide layer and the nitride layer. In the case of the nitride layer, subsequent processes of shielding the electrode and the gate electrode are performed to avoid the generation of holes or voids in the trench gate structure.

One embodiment of the present invention provides a trench power transistor including a substrate, an epitaxial layer, a trench gate structure, a body region and a source region. The epitaxial layer is located on the substrate and has at least one element trench formed therein. The trench gate structure is located in the element trench, and the trench gate structure includes a shielding electrode, a gate electrode and an insulating layer. The shielding electrode is located in the lower half of the element trench, and the gate electrode is located in the upper half of the element trench and is electrically insulated from the shielding electrode. The insulating layer is arranged in the element trench and has a contour conforming to the inner wall surface of the element trench, wherein the gate electrode and the shielding electrode are isolated from each other by the insulating layer and the epitaxial layer, wherein the insulating layer at least comprises a first dielectric layer, a second A dielectric layer and a third dielectric layer, wherein the third dielectric layer is located in the lower half of the element trench, and the second dielectric layer partially located in the lower half of the element trench is sandwiched between the first dielectric layer and the third dielectric layer, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer. The body region is formed in the epitaxial layer and surrounds the trench gate structure. The source region is formed over the body region.

Another embodiment of the present invention provides a trench power transistor, including a substrate, an epitaxial layer, a trench gate structure, a first base region, a source region, a first terminal electrode structure, a second terminal electrode structure, and at least a Two second matrix regions. The epitaxial layer is located on the substrate, wherein the epitaxial layer defines an active region and a rectifying region. The trench gate structure is formed in the epitaxial layer and located in the active region. The first body region is formed in the epitaxial layer within the active region and surrounding the trench gate structure. The source region is formed over the first body region. The first terminal electrode structure and the second terminal electrode structure are both formed in the epitaxial layer and located in the rectification region, wherein the first terminal electrode structure and the second terminal electrode structure are adjacent and juxtaposed along a first direction. At least two second base regions are located in the epitaxial layer between the first terminal electrode structure and the second terminal electrode structure, and are arranged along a second direction, wherein two adjacent second base regions are separated from each other by a predetermined distance, to define at least one Schottky contact area.

To sum up, the trench power transistor of the present invention can avoid the generation of holes or voids in the insulating layer. Therefore, when the gate electrode is biased, the leakage current between the gate electrode and the drain can be avoided, thereby improving the electrical performance of the trench power transistor.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic partial cross-sectional view of a trench power transistor according to an embodiment of the present invention.

FIG. 2 is a schematic partial cross-sectional view of a trench power transistor according to another embodiment of the present invention.

FIG. 3 shows a process flow diagram of a trench power transistor according to an embodiment of the present invention.

4A to 4K are partial cross-sectional schematic diagrams of each step in the manufacturing process of the trench power transistor according to an embodiment of the present invention, respectively.

5A to FIG. 5C are partial cross-sectional schematic diagrams of each step in the manufacturing process of the trench power transistor according to another embodiment of the present invention, respectively.

FIG. 6 is a schematic partial cross-sectional perspective view of a trench power transistor according to another embodiment of the present invention.

Detailed ways

Please refer to Figure 1. FIG. 1 is a schematic diagram of a partial cross-sectional structure of a trench power transistor according to an embodiment of the present invention. The trench power transistor 1 includes a substrate 100 , an epitaxial layer 120 , a trench gate structure 160 , a body region 140 and a source region 150 .

In FIG. 1 , the substrate 100 has a high concentration of first-type conductivity impurities to form a first heavily doped region. The first heavily doped region is used as a drain of the trench power transistor, and can be distributed in a local area of the substrate 100 or in the entire substrate 100 . In this embodiment, the first heavily doped regions are distributed in the entire substrate 100 , but are only used for example and are not used to limit the present invention. The aforementioned first-type conductivity impurities may be N-type or P-type conductivity impurities. Assuming that the substrate 100 is a silicon substrate, the N-type conductivity impurities are pentavalent element ions, such as phosphorus ions or arsenic ions, and the P-type conductivity impurities are trivalent element ions, such as boron ions, aluminum ions, or gallium ions.

If the trench power transistor is N-type, the substrate 100 is doped with N-type conductive impurities. On the other hand, in the case of a P-type trench power transistor, the substrate 100 is doped with P-type conductive impurities. In the embodiments of the present invention, an N-type trench power transistor is used as an example for description.

An epitaxial layer 120 is located on the substrate 100 and has a low concentration of first-type conductivity impurities. That is to say, taking an NMOS transistor as an example, the substrate 100 is doped with a high concentration of N-type (N+), and the epitaxial layer 120 is doped with a low concentration of N-type (N-). On the contrary, taking a PMOS transistor as an example, the substrate 100 is P-doping with a high concentration (P+doping), and the epitaxial layer 120 is P-doping with a low concentration.

In this embodiment, the trench power transistor 1 further includes a buffer layer 110 disposed between the epitaxial layer 120 and the substrate 100 . The buffer layer 110 has the same conductivity type as the substrate 100 and the epitaxial layer 120 , that is, the buffer layer 110 is also doped with impurities of the first type conductivity. It should be noted that the doping concentration of the buffer layer 110 is between the doping concentration of the substrate 100 and the doping concentration of the epitaxial layer 120 . By disposing the buffer layer 110 between the substrate 100 and the epitaxial layer 120 , the on-state source/drain resistance (Rdson) can be reduced, thereby reducing the power of the trench power transistor 1 consume.

In addition, the epitaxial layer 120 can be divided into a drift region 130 (drift region), a body region (body region) and a source region (source region) 150 by doping different regions with different concentrations and different types of conductive impurities . The body region 140 and the source region 150 are formed in the epitaxial layer 120 on the side of the trench gate structure 160 , and the drift region 130 is located on the side of the epitaxial layer 120 close to the substrate 100 . That is, the body region 140 and the source region 150 are formed in the upper half of the epitaxial layer 120 , and the drift region 130 is formed in the lower half of the epitaxial layer 120 .

In detail, the base region 140 is formed by doping the epitaxial layer 120 with impurities of the second type conductivity, and the source region 150 is formed by doping the base region 140 with impurities of the first type conductivity with a high concentration formed, and the source region 150 is formed on the upper half of the base region 140 . For example, for an NMOS transistor, the body region 140 is P-type doped (eg, P-well, P-well), and the source region 150 is N-type doped. In addition, the doping concentration of the body region 140 is smaller than that of the source region 150 .

In addition, in this embodiment, the epitaxial layer 120 defines an active region AR and a termination region TR adjacent to the active region AR. The aforementioned body region 140 is formed in the active region AR and the termination region TR, while the source region 150 is formed only in the active region AR. The epitaxial layer 120 also has at least one element trench 120a located in the active region AR.

It should be noted that the element trench 120a of the embodiment of the present invention has a deep trench structure. That is, the element trench 120 a extends downward from the surface of the epitaxial layer 120 to below the base region 140 , that is, into the drift region 130 , and the bottom of the element trench 120 a is closer to the substrate 100 .

In the embodiment of the present invention, at least one trench gate structure 160 is disposed in the corresponding element trench 120 a and has a shielding electrode 165 , a gate electrode 167 and an insulating layer 164 .

The shielding electrode 165 is located in the lower half of the element trench 120 a, and the gate electrode 167 is disposed above the shielding electrode 165 and is electrically insulated from the shielding electrode 165 . Specifically, the trench gate structure 160 further includes an inter-electrode dielectric layer 166 disposed between the shielding electrode 165 and the gate electrode 167 to isolate the gate electrode 167 from the shielding electrode 165 . The material constituting the gate electrode 167 and the shielding electrode 165 may be, but not limited to, heavily doped polysilicon. The material constituting the inter-electrode dielectric layer 166 may be oxide (eg, silicon oxide), nitride (eg, nitride) or other insulating materials, which are not limited in the present invention.

It should be noted that the deep trench structure of the device trench 120 a helps to increase the breakdown voltage of the trench power transistor 1 , but increases the gate/drain capacitance (Cgd) and the source/drain conduction. Resistance (Rdson). Accordingly, in the embodiment of the present invention, disposing the shielding electrode 165 at the bottom of the element trench 120a can reduce the capacitance (Cgd) of the gate/drain, so as to reduce the work loss. Besides, the shielding electrode 165 can be electrically connected to the source electrode, so that the drift region 130 can achieve a charge balance and further increase the breakdown voltage. Therefore, the impurity doping concentration of the drift region 130 can be relatively increased to reduce the on-resistance in the drift region 130 . It should also be noted that, in the embodiment of the present invention, the lower edge of the base region 140 is used as the reference plane, and the device trench 120a is roughly divided into an upper half and a lower half.

The insulating layer 164 is conformally disposed on the inner wall surface of the element trench 120a, and has a contour conforming to the inner wall surface of the element trench 120a. The aforementioned inner wall surface includes the two side wall surfaces and the bottom surface of the element groove 120a. The insulating layer 164 can be used to electrically isolate the gate electrode 167 and the shielding electrode 165 from the epitaxial layer 120 .

In detail, the insulating layer 164 includes a first dielectric layer 161 , a second dielectric layer 162 and a third dielectric layer 163 . In this embodiment, the direction from the inner sidewall of the element trench 120 a to the direction close to the gate electrode 167 and the shielding electrode 165 is the first dielectric layer 161 , the second dielectric layer 162 and the third dielectric layer 163 in sequence. , wherein the third dielectric layer 163 is located in the lower half of the element trench, and part of the second dielectric layer located in the lower half of the element trench 120a is sandwiched between the first dielectric layer 161 and the third dielectric layer 163 between.

That is, the first dielectric layer 161 and the second dielectric layer 162 both extend from the upper half of the element trench 120a to the lower half and bottom of the element trench 120a, but the third dielectric layer 163 is only formed in the lower half and the bottom of the element trench 120a. Therefore, in this embodiment, the first dielectric layer 161 and the second dielectric layer 162 located in the upper half of the element trench 120a surround the gate electrode 167 and serve as a gate dielectric layer. Accordingly, the second dielectric layer 162 is located between the gate electrode 167 and the first dielectric layer 161 in the upper half of the element trench 120a.

In addition, the first dielectric layer 161 , the second dielectric layer 162 and the third dielectric layer 163 located in the lower half of the element trench 120 a surround the shielding electrode 165 and can serve as shielding dielectric layers. Therefore, the third dielectric layer 163 is located between the second dielectric layer 162 and the shielding electrode 165 . In one embodiment, the level of the top surface of the third dielectric layer 163 is lower than the lowermost edge of the base region 140 , so as to ensure that inversion channels can be generated in the base region 140 .

In addition, it should be noted that the structure in which the first dielectric layer 161 and the second dielectric layer 162 extend from the upper half of the element trench 120a to the lower half of the element trench 120a can avoid the formation of voids or voids in the element trench 120a. holes, thereby avoiding the generation of gate/source leakage current and improving the poor electrical performance caused by the gate/source leakage current.

In addition, in one embodiment, the dielectric constant of the second dielectric layer 162 is greater than the dielectric constant of the first dielectric layer 161 . Therefore, the materials constituting the first dielectric layer 161 and the second dielectric layer 162 are different, but the materials constituting the first dielectric layer 161 and the third dielectric layer 163 can be selected from the same or different materials. For example, the material constituting the first dielectric layer 161 and the third dielectric layer 163 can be, but not limited to, oxide, such as silicon oxide, and the material constituting the second dielectric layer 162 is nitride, such as nitrogen Silicon, or other materials with a high dielectric constant, such as hafnium oxide, yttrium oxide, or aluminum oxide, etc.

Therefore, compared to using only the oxide layer as the gate dielectric layer, under the same thickness, the gate dielectric layer of this embodiment, that is, the first dielectric layer located in the upper half of the element trench 120a The second dielectric layer 161 and the second dielectric layer 162 may have higher capacitance, also called gate-to-channel capacitance (Cgs). It should be noted that when the gate electrode 167 is biased to form an inversion channel in the body region 140, the gate/channel capacitance value and the inversion channel resistance (Rch) become negative. related. Accordingly, as the gate/channel capacitance increases, the inversion channel resistance decreases. Since the inversion channel resistance is positively correlated with the source/drain on-resistance, the inversion channel resistance decreases, which can further reduce the source/drain on-resistance of the trench power transistor 1 .

However, as long as the above effects can be achieved, the materials of the first to third dielectric layers 161 - 163 can also be selected from different insulating materials according to practical applications, and the present invention is not limited thereto.

In addition, in this embodiment, the total thickness of the first dielectric layer 161 and the second dielectric layer 162 determines the voltage that the trench power transistor gate can withstand according to the total thickness of the trench power transistor, which is usually between 12V to 25V. Specifically, the thickness of the first dielectric layer is between 10 and 35 nm, the thickness of the second dielectric layer is between 20 and 30 nm, and the thickness of the third dielectric layer 163 is between 50 and 200 nm. , and the third layer thickness can determine the breakdown voltage.

Please continue to refer to FIG. 1 , in this embodiment, the epitaxial layer 120 further has a termination trench 120b located in the termination region TR. In addition, the trench power transistor 1 further includes a terminal electrode structure 170 formed in the terminal trench 120b. In detail, the terminal electrode structure 170 includes a terminal electrode 172 located in the terminal trench 120b and a terminal dielectric layer 171 for isolating the terminal electrode 172 and the epitaxial layer 120 from each other.

Further, the termination dielectric layer 171 is conformally disposed on the inner wall of the termination trench 120b and has a contour conforming to the inner wall of the termination trench 120b to electrically isolate the termination electrode 172 from the epitaxial layer 120 . In this embodiment, the termination dielectric layer 171 is a laminated structure. The direction of the aforementioned stacked structure from the inner sidewall of the first terminal trench 120b to the terminal electrode 172 is a first oxide layer 171a, a nitride layer 171b and a second oxide layer 171c in sequence. That is, the nitride layer 171b of the termination dielectric layer 171 is sandwiched between the aforementioned first oxide layer 171a and the second oxide layer 171c.

The trench power transistor 1 according to the embodiment of the present invention further includes an interlayer dielectric layer 180 , at least one source conductive plug 184 and a conductive layer 190 .

Referring to FIG. 1 , the interlayer dielectric layer 180 is formed on the epitaxial layer 120 and has a protective layer 181 and a planarization layer 182 .

In this embodiment, the protective layer 181 is directly formed on the surface of the epitaxial layer 120 and has a laminated structure. The protective layer 181 at least includes a first film layer 181 a formed on the surface of the epitaxial layer 120 and a second film layer 181 b formed on the first film layer 181 a. The materials of the first film layer 181a and the second film layer 181b may be the same as those of the first dielectric layer 161 and the second dielectric layer 162 located in the element trench 120a, respectively. That is, when the first dielectric layer 161 is an oxide layer and the second dielectric layer 162 is a nitride layer, the protective layer 181 has oxide (the first film layer 181 a ) and nitride (the second film layer 181 a ) 181b) of the laminated structure. In this case, the first film layer 181a and the first dielectric layer 161 may be formed in the same deposition process. Similarly, the second film layer 181b and the second dielectric layer 162 can also be formed in the same deposition process. The detailed process steps will be described later and will not be repeated here.

In other embodiments, the materials constituting the first film layer 181a and the second film layer 181b may also be different from those of the first dielectric layer 161 and the second dielectric layer 162, which are not limited in the present invention. The flat layer 182 is formed on the protective layer 181, and the material used for the subsequent deposition of the conductive layer 190 and forming the flat layer 182 can be borophosphosilicate glass (BPSG), phosphorous silicate glass (PSG), oxide, nitride or its combination.

In addition, the interlayer dielectric layer 180 has at least one source contact window 183 . In this embodiment, the source contact window 183 extends from the upper surface of the interlayer dielectric layer 180 into a part of the epitaxial layer 120 and is formed on one side of the source region 150 . In addition, the epitaxial layer 120 further includes a contact doping region 121 , and the contact doping region 121 is located just below the bottom of the source contact window 183 . In one embodiment, boron difluoride (BF2) is implanted in the epitaxial layer 120 through the source contact window 183 to form the contact doped region 121 .

However, the position of the source contact window 183 may be changed according to the design of the device, and is not limited to the embodiment of the present invention. In other embodiments, the source contact window 183 may also directly correspond to the position of the source region 150 and be formed just above the source region 150 .

The source conductive plug 184 is formed in the source contact window 183 to be electrically connected to the source region 150 . Specifically, the source conductive plug 184 is formed in the source contact window 183 and directly contacts the source region 150 in the epitaxial layer 120 and the contact doped region 121 , so that the source conductive plug 184 and the source An ohmic contact is formed between the pole regions 150 . The material constituting the source conductive plug 184 may be a metal such as, but not limited to, tungsten, copper, nickel, or aluminum.

The conductive layer 190 covers the flat layer 182 and is electrically connected to the source region 150 through the source conductive plug 184 passing through the interlayer dielectric layer 180 . That is, the conductive layer 190 can be used as the source electrode of the trench power transistor 1 and used to be electrically connected to an external control circuit. The material of the conductive layer 190 can be titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum-silicon alloy (Al-Si) or aluminum-silicon-copper alloy (Al-Si-Cu), etc. Not limited to this.

Referring to FIG. 2 , a schematic partial cross-sectional view of a trench power transistor according to another embodiment of the present invention is shown. The same elements of the trench power transistor 1' of this embodiment and the trench power transistor 1 of FIG. 1 have the same reference numerals, and the same parts of this embodiment and the previous embodiment will not be repeated.

The difference between the embodiment shown in FIG. 2 and the previous embodiment is that in the trench power transistor 1 ′ of the present embodiment, the insulating layer 164 ′ of the trench gate structure further includes a fourth dielectric layer 168 . The fourth dielectric layer 168 is formed on the upper half of the element trench 120 a and sandwiched between the side surface of the gate electrode 167 and the second dielectric layer 162 .

The first dielectric layer 161 , the second dielectric layer 162 and the fourth dielectric layer 168 located in the upper half of the element trench 120 a serve as gate dielectric layers of the trench gate structure. In one embodiment, the material of the fourth dielectric layer 168 may be the same as that of the first dielectric layer 161 , such as silicon oxide. In addition, in this embodiment, the total thickness of the first dielectric layer 161, the second dielectric layer 162 and the fourth dielectric layer 168 determines the voltage that the trench power transistor gate can withstand, which is usually between 12V and 12V. between 25V. Specifically, compared with the previous embodiment, the thickness of the first dielectric layer 161 can be thinner, about 10 nm, the thickness of the second dielectric layer 162 is unchanged, ranging from 20 nm to 30 nm, the third dielectric layer The thickness of the layer 163 is between 50 and 200 nm, and the thickness of the fourth dielectric layer 168 is between 10 and 25 nm.

In addition, the inter-electrode dielectric layer 166' of this embodiment includes a first insulating layer 166a and a second insulating layer 166b, wherein the first insulating layer 166a and the second insulating layer 166b are stacked on the shielding electrode 165 in sequence. That is to say, the inter-electrode dielectric layer 166' in this embodiment is a laminated structure. In one embodiment, the second insulating layer 166b and the fourth dielectric layer 168 may be made of the same material and formed in the same process, but the invention is not limited thereto.

Next, embodiments of the present invention provide a fabrication process of the trench power transistor. Please refer to FIG. 3 , which shows a process flow diagram of the trench power transistor according to an embodiment of the present invention. In addition, please refer to FIG. 4A to FIG. 4K , which are schematic partial cross-sectional views of each step in the manufacturing process of the trench power transistor according to an embodiment of the present invention.

In step S300, a substrate is provided. Next, in step S301, an epitaxial layer is formed on the substrate. Please refer to Figure 4A. FIG. 4A shows a substrate 100, and an epitaxial layer 120 has been formed on the substrate 100, wherein the substrate 100 is, for example, a silicon substrate, which has a first re-doping with a high doping concentration The impurity region is used as the drain of the trench power transistor, and the epitaxial layer 120 has a low doping concentration.

In this embodiment, before the step of forming the epitaxial layer 120 on the substrate 100 , it further includes forming a buffer layer 110 on the substrate 100 . As shown in FIG. 4A , the buffer layer 110 is located between the substrate 100 and the epitaxial layer 120 . In addition, the buffer layer 110 has the same conductivity type as the substrate 100 and the epitaxial layer 120 , but the doping concentration of the buffer layer 110 is between the doping concentration of the substrate 100 and the doping concentration of the epitaxial layer 120 . In addition, in this embodiment, the epitaxial layer 120 defines an active region AR and a termination region TR.

Please refer to FIG. 3 again. Next, in step S302 , at least one element trench is formed in the epitaxial layer. The manufacturing process of the trench power transistor provided in this embodiment may further include forming a termination trench in the epitaxial layer when forming the element trench.

In detail, please refer to FIG. 4B , the element trench 120a is formed in the active region AR, and the termination trench 120b is formed in the termination region TR. In addition, in one embodiment, the positions of the element trenches 120 a and the terminal trenches 120 b are first defined by a photomask (not shown), and then the element trenches are formed in the epitaxial layer 120 by dry etching or wet etching. Slot 120a and terminal trench 120b.

Next, please refer to Figure 3 again. In step S303, a trench gate structure is formed in the element trench, wherein the trench gate structure includes a shielding electrode, a gate electrode and an insulating layer, wherein the insulating layer is conformally disposed on the inner wall surface of the element trench, and The gate electrode and the shielding electrical and epitaxial layers are isolated from each other. The insulating layer at least includes a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the third dielectric layer is located in the lower half of the element trench, and part of the second dielectric layer is located in the lower half of the element trench The layer is sandwiched between the first dielectric layer and the third dielectric layer.

In addition, the method for the trench power transistor of this embodiment further includes: forming a terminal electrode structure in the terminal trench. Also, the steps of forming the terminal electrode structure and forming the trench gate structure can be performed simultaneously. The terminal electrode structure includes a terminal electrode and a terminal dielectric layer, wherein the terminal dielectric layer is compliantly arranged on the inner wall surface of the first terminal trench to isolate the terminal electrode and the epitaxial layer, wherein the terminal dielectric layer includes at least two layers of oxides layer and a nitride layer sandwiched between the oxide layers.

In detail, please refer to FIG. 4C to FIG. 4H , which show the detailed process of forming the trench gate electrode and the terminal electrode structure. Please refer to FIG. 4C first. In FIG. 4C , the first dielectric material 210 , the second dielectric material 220 and the third dielectric material 230 are sequentially blanket formed on the inner walls (including the two side walls) of the element trench 120 a and the terminal trench 120 b and bottom surface), and the surface of the epitaxial layer 120 . The first dielectric material 210 may be an oxide layer or a nitride layer. For example, the first dielectric material 210 is silicon oxide (SiOx) and is formed by a thermal oxidation process. In other embodiments, the first dielectric material 210 may also be formed by a physical vapor deposition or chemical vapor deposition process.

In one embodiment, the dielectric constant of the second dielectric material 220 is higher than the dielectric constant of the first dielectric material 210 . For example, when the first dielectric material 210 is silicon oxide, the second dielectric material can be nitride, such as silicon nitride, and conformally cover the first dielectric material by physical vapor deposition or chemical vapor deposition material 210.

The third dielectric material 230 can be any one of oxide or nitride, such as silicon oxide (SiO 4 ), and is not particularly limited. Furthermore, a process for depositing the third dielectric material 230 can be selected according to the selected material and actual requirements, such as a physical vapor deposition or chemical vapor deposition process.

In one embodiment, the thickness of the first dielectric material 210 is between 20 and 30 nm, the thickness of the second dielectric material 220 is between 20 and 30 nm, and the thickness of the third dielectric material 230 is between 60 and 120 nm.

After the deposition of the first to third dielectric materials 210 - 230 is completed, a first polysilicon structure is firstly formed on the third dielectric layer 163 by blanketing, and the element trench 120 a and the terminal trench 120 b are filled middle. The first polysilicon structure may be a conductive impurity-containing polysilicon structure (doped poly-Si). Next, the first polysilicon structure covered on the surface of the third dielectric layer 163 is removed by etch back, and the first polysilicon structure 240a and the terminal trench 120b located in the element trench 120a are respectively left behind the first polysilicon structure 240b.

4D, a photoresist layer 3 is formed on the third dielectric material 230, wherein the photoresist layer 3 has an opening 3a to expose the device trench 120a in the active region AR. That is to say, the photoresist layer 3 covers the termination trench 120b in the termination region TR and a part of the surface of the third dielectric material 230 . Next, the first polysilicon structure 240a located in the upper half of the element trench 120a is etched, and only the first polysilicon structure 240a' located in the lower half of the element trench 120a is left. After completing the aforementioned etching process, the photoresist layer 3 is removed.

Next, referring to FIG. 4E , an oxide layer 250 is formed to cover the surface of the third dielectric material 230 and fill in the element trench 120a and the terminal trench 120b. It should be noted that, in the process of forming the oxide layer 250, the top of the first polysilicon structure 240a' located in the lower half of the element trench 120a, and the top of the first polysilicon structure 240b located in the terminal trench 120b The tops are slightly oxidized. After the aforementioned steps are completed, in the lower half of the element trench 120a, a shield electrode 165' has been formed.

4F, the oxide layer 250 located on the surface of the epitaxial layer 120 and the oxide layer 250 located on the upper half of the element trench 120a are removed, and only part of the oxide layer 250' located on the top of the shielding electrode 165' is left, wherein The oxide layer 250 ′ may be equivalent to the interelectrode dielectric layer 166 as shown in FIG. 1 .

In addition, in the step of removing the oxide layer 250, part of the third dielectric material 230 located on the surface of the epitaxial layer 120 and located in the element trench 120a and the terminal trench 120b is also removed. In detail, in the element trench 120a, the third dielectric material 230 located on the inner wall surface of the upper half of the element trench 120a will be removed, leaving only the inner wall surface of the lower half of the element trench 120a. The third dielectric material 230 ′ is formed to form the third dielectric layer 163 as shown in FIGS. 1 and 2 .

Please refer to Figure 4G. Next, a second polysilicon structure 260 is formed in a blanket manner to cover the surface of the epitaxial layer 120 and fill in the element trench 120a and the terminal trench 120b. In detail, the second polysilicon structure 260 covers the surface of the second dielectric material 220 and fills the upper half of the element trench 120a and the remaining space of the terminal trench 120b. The manner of forming the second polysilicon structure 260 may be the same as the manner of forming the first polysilicon structure, which will not be repeated here.

Referring to FIG. 4H, the second polysilicon structure 260 above the epitaxial layer 120 is etched back to form a gate electrode 167" in the element trench 120a, and a terminal electrode 172' is formed in the termination trench 120b. Accordingly, , the first dielectric material 210 and the second dielectric material 220 formed on the inner wall surface of the element trench 120 a can be regarded as the first dielectric layer 161 and the second dielectric layer 162 in FIG. 1 , respectively.

It should be noted that, in the process steps of forming the trench gate structure and the terminal electrode structure, neither the first dielectric material 210 nor the second dielectric material, which were initially formed in the element trench 120a and the terminal trench 120b Electrical material 220 is removed. Therefore, no gaps or holes are left in the device trench 120a as in the prior art, and the generation of gate/source leakage current can be avoided.

Please refer to Figure 3 again. Go to step S304 and step S305. In step S304, a base doping process is performed on the epitaxial layer to form a base region. In step S305, a source doping process is performed to form a source region, wherein the source region is located above the body region.

Referring to FIG. 4I , after a base doping process is performed on the epitaxial layer 120 , a first doped region is formed on the side of the epitaxial layer 120 away from the substrate 100 . After the first doping region is formed, a source doping process is performed on the first doping region to form the source region 150 and the body region 140 . It should be noted that, the source doping process may include performing a thermal diffusion process after ion implantation on the first doping region to form the source region 150 . In addition, it can be seen from FIG. 4I that the lowermost edge of the base region 140 in this embodiment is higher than the horizontal position where the top surface of the third dielectric material 230' is located.

The manufacturing process of the trench power transistor provided by the embodiment of the present invention may further include forming a circuit redistribution layer on the epitaxial layer, so that the source region 150 , the gate electrode 167 and the shielding electrode 165 can be electrically connected to external control circuit. The following will take the formation of the source contact plug shown in FIG. 1 as an example, and in conjunction with FIGS. 4J to 4K , to describe the specific steps of the line redistribution layer.

Referring to FIG. 4J, a flat layer 270 is formed to fully cover the surface of the second dielectric material 220, the trench gate structure 160' and the terminal electrode structure 170'. The material constituting the flat layer 270 can be selected from borophosphosilicate glass (BPSG), phosphorous silicate glass (PSG), oxide, nitride or a combination thereof.

Then, corresponding to the position of the source region 150, at least one source contact window 270a (two are shown in FIG. 4J as an example) is formed. In this example. The technical means for forming the source contact window 270a can be realized by conventional steps such as coating photoresist, photolithography, and etching.

Next, please refer to FIG. 4K. A source conductive plug 280 is formed in the corresponding source contact window 270a. It should be noted that the source conductive plug 280 extends into the epitaxial layer 120 after passing through the planarization layer 270 , the first dielectric material 210 and the second dielectric material 220 , and is located on one side of the source region 150 , so as to It is electrically connected to the source region 150 .

It should be noted that, before the source conductive plugs 280 are formed on the corresponding source contact windows 270a, a doping process may be performed on the epitaxial layer 120 through the source contact windows 270a, so that a doping process can be performed on the epitaxial layer 120 under the source contact windows 270a. A contact doped region 121 is formed in the epitaxial layer 120 . In one embodiment, the impurity doped in the contact doped region 121 is boron difluoride (BF2).

In addition, after the source conductive plugs 280 are formed on the corresponding source contact windows 270 a , a conductive layer 290 may be formed to cover the flat layer 270 and be electrically connected to the source conductive plugs 280 . The material of the conductive layer 290 can be titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum-silicon alloy (Al-Si) or aluminum-silicon-copper alloy (Al-Si-Cu), etc. Not limited to this. Accordingly, the conductive layer 290 can be electrically connected to the source region 150 and the contact doped region 121 through the source conductive plug 280 . Through the description of the above embodiments, those skilled in the art should be able to easily infer other implementation structure details, which will not be repeated here.

It should be further explained that the functions of the part of the first dielectric material 210 and the second dielectric material 220 located on the surface of the epitaxial layer 120 are equivalent to the protective layer 181 shown in FIG. 1 , and the planarization layer 270 is equivalent to The planarization layer 182 shown in FIG. 1 . In addition, the first dielectric material 210 , the second dielectric material 220 and the third dielectric material 230 sequentially located on the inner wall surface of the element trench 120 a may be equivalent to the insulating layers of the trench gate structure 160 shown in FIG. 1 . 164.

The present invention also provides another embodiment of the fabrication process of the trench power transistor. Please refer to FIG. 5A to FIG. 5B , which are partial cross-sectional schematic diagrams of each step in the fabrication process of the trench power transistor according to another embodiment, respectively.

It should be noted that the process steps of FIG. 5A are performed after the process steps shown in FIGS. 4A to 4F in the previous embodiment are completed. That is to say, after removing the oxide layer 250 on the surface of the epitaxial layer 120 and the oxide layer 250 on the upper half of the element trench 120a, leaving only part of the oxide layer 250' on the top of the shielding electrode 165, a first The four dielectric material 300 conformally covers the surface of the second dielectric material 220 and is formed in the element trench 120a and the terminal trench 120b. The process of forming the fourth dielectric material 300 can be selected from a known deposition process, and the fourth dielectric material 300 can be an oxide or a nitride.

Next, a second polysilicon structure 260' is formed on the fourth dielectric material 300 by blanketing. For the process of forming the second polysilicon structure 260', reference may be made to the process previously described corresponding to FIG. 4G , and details are not repeated here.

Then, referring to FIG. 5B , the second polysilicon structure 260 above the epitaxial layer 120 and covering the terminal trench 120b is removed by etching back, and the second polysilicon structure in the element trench 120a is left, so as to form Gate electrode 167a. Accordingly, the first to fourth dielectric materials 210, 220, 230', 300 formed on the inner wall surface of the element trench 120a can be equivalent to the insulating layer 164' shown in FIG. 2 . In addition, within the element trench 120a, the oxide layer 250' and the fourth dielectric layer 300a located between the first polysilicon structure 165' and the second polysilicon structure 260' may be respectively as shown in FIG. 2 . The first film layer 181a and the second film layer 181b.

Please refer to FIG. 5C. Subsequently, the base body region 140 and the source region 150 are respectively formed in the epitaxial layer 120 , and a line redistribution layer is formed on the epitaxial layer 120 , ie, the fourth dielectric layer 300 . The detailed process steps of forming the line redistribution layer are similar to the steps shown in FIGS. 4J to 4K , including: forming a flat layer 270 to fully cover the surface of the second dielectric material 220 , the trench gate structure and the terminal electrode structure; The source contact 270a is subjected to a doping process to the epitaxial layer 120 to form a contact doped region 121 in the epitaxial layer 120 under the source contact 270a; source conductive plugs 280 are formed in the corresponding source contact 280 ; and a conductive layer 290 is formed to cover the flat layer 270 and electrically connected to the source conductive plug 280 . Through the above process, the trench power transistor as shown in FIG. 2 can be formed.

Please refer to Figure 6. FIG. 6 is a schematic partial cross-sectional perspective view of a trench power transistor according to another embodiment of the present invention.

The trench power transistor 3 of this embodiment can be applied to a voltage conversion circuit as a low side power transistor. In detail, the trench power transistor 3 of this embodiment includes a substrate 310, an epitaxial layer 330, a trench gate structure 360, a terminal electrode structure 370, first to third terminal electrode structures 380a-380c, a plurality of A body region 340a , a plurality of second body regions 340b and source regions 350 . In addition, similar to the embodiments of FIGS. 1 and 2 , there is a buffer layer 320 between the substrate 310 and the epitaxial layer 330 . It should be explained first that the elements in this embodiment that are the same as those in the embodiments of FIG. 1 and FIG. 2 will not be specifically described.

In this embodiment, the epitaxial layer 330 defines an active region AR, a termination region TR and a rectification region SR. The epitaxial layer 330 also has at least one element trench 360h located in the active region AR, a termination trench 370h located in the termination region TR, and a first termination trench 381, a second termination trench 382 located in the rectification region SR and The third terminal trench 383 .

The element trenches 360h, the termination trenches 370h, the first termination trenches 381, the second termination trenches 382, and the third termination trenches 383 are formed in parallel in the epitaxial layer 330 along a first direction D1. In this embodiment, the element trench 360h is adjacent to the first termination trench 381 and has a first pitch P1. In addition, in the rectification region SR, the first to third terminal trenches 381 to 383 are separated from each other by a second pitch P2, wherein the second pitch P2 is slightly smaller than the first pitch P1, and the first pitch P1 and the second pitch The difference between P2 is between 0.1 μm and 0.3 μm.

In this embodiment, the structure of the trench gate structure 360 may be the same as that of the trench gate structure 160 shown in FIG. 1 or FIG. 2, and is positioned in the element trench (not numbered), wherein the element trench is located in the within the source area AR. In addition, the first body region 340a and the source region 350 are located in the active region AR, and are formed in the epitaxial layer 330 on both sides of the trench gate structure 360 .

The termination electrode structure 370 may be the same as the termination electrode structure 170 shown in FIG. 1 or FIG. 2 and is located in a termination trench (not numbered), wherein the termination trench is located in the termination region TR. Similarly, the first to third terminal electrode structures 380a˜380c may have the same structure as the terminal electrode structure 170 shown in FIG. 1 or FIG. 2 . The first to third terminal electrode structures 380 a ˜ 380 c are located in the first terminal trench 381 , the second terminal trench 382 and the third terminal trench 383 , respectively.

It should be noted that a plurality of second base regions 340b are formed between two adjacent first and second terminal electrode structures 380a, 380b, or two adjacent second and third terminal electrode structures 380b, 380c in the epitaxial layer 330 in between.

Further, the plurality of second base regions 340b located between two adjacent first and second terminal electrode structures 380a, 380b are arranged along a second direction D2, and any two adjacent second base regions 340b are arranged along a second direction D2. The regions 340b are spaced apart from each other by a predetermined distance, thereby defining at least one Schottky contact region 330s. In other words, the distance between two adjacent second base regions 340b arranged along the second direction D2 is the length L of the Schottky contact region 330s in the second direction D2. In one embodiment, the length L of the Schottky contact region 330s in the second direction D2 is between 0.6 μm and 1.2 μm. In the embodiment of the present invention, the trench power transistor 3 may further include an interlayer dielectric layer (not shown) formed on the epitaxial layer and at least one conductive plug (not shown) passing through the interlayer dielectric layer. not shown).

In detail, the interlayer dielectric layer may have at least one contact window (not shown) corresponding to the Schottky contact region 330s, and the conductive plug contacts the epitaxial layer located in the Schottky contact region through the contact window, so as to A Schottky diode is formed.

Since the forward voltage for turning on the Schottky diode is lower than the forward voltage drop of the body diode, the switching loss can be reduced by constructing the Schottky diode in the trench power transistor 3 . In addition, the reverse recovery characteristics of the Schottky diode are better, and when the trench power transistor 3 is applied to a higher frequency circuit, the switching loss can be reduced more effectively.

To sum up, in the trench power transistor and its manufacturing process provided by the embodiments of the present invention, after the step of forming the oxide layer and the nitride layer on the inner wall surface of the device trench and the surface of the epitaxial layer, there is no further The oxide layer in contact with the epitaxial layer and the nitride layer covering the aforementioned oxide layer are removed. In addition, without removing the nitride layer, the subsequent process of shielding the electrode and the gate electrode is directly performed, which can avoid the generation of holes or voids in the trench gate structure. The trench gate structure can be avoided. Holes or voids are created in the insulating layer. Therefore, when the gate electrode is biased, the leakage current between the gate electrode and the drain can be avoided, thereby improving the electrical performance of the trench power transistor.

Although the embodiments of the present invention have been disclosed above, the present invention is not limited to the above-mentioned embodiments, and any person of ordinary skill in the art can make some changes and adjustments without departing from the scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

【Symbol Description】

Trench Power Transistors 1, 1’, 3

Substrate 100, 310

Buffer layer 110, 320

Epitaxial layer 120, 330

Drift Zone 130

Matrix area 140

first substrate region 340a

second base region 340b

Source region 150, 350

Trench gate structures 160, 160', 360

Schottky Contact Area 330s

Active area AR

Termination area TR

Rectification area SR

Element trenches 120a, 360h

Termination grooves 120b, 370h

first terminal groove 381

Second Termination Groove 382

Third Termination Groove 383

Shield electrode 165, 165’

Gate electrodes 167, 167', 167", 167a

Insulation 164, 164'

Interpolar dielectric layer 166, 166’

first insulating layer 166a

The second insulating layer 166b

first dielectric layer 161

second dielectric layer 162

third dielectric layer 163

Termination electrode structure 170, 170’, 370

The first terminal electrode structure 380a

second terminal electrode structure 380b

Third terminal electrode structure 380c

Terminal electrodes 172, 172'

Termination Dielectric Layer 171

first oxide layer 171a

Nitride layer 171b

Second oxide layer 171c

Interlayer Dielectric Layer 180

Source conductive plug 184, 280

Source contacts 183, 270a

Conductive layer 190, 290

protective layer 181

first film layer 181a

Second film layer 181b

Flat layer 182, 270

Contact Doping Region 121

fourth dielectric layer 168

first dielectric material 210

second dielectric material 220

third dielectric material 230, 230'

first polysilicon structures 240a, 240b, 240a', 240b'

Photoresist Layer 3

Opening 3a

Oxide 250, 250’

Second polysilicon structure 260, 260’

Fourth dielectric material 300, 300a

first direction D1

Second direction D2

The first pitch P1

The second pitch P2

length L

Process steps S300-S305.

Claims (9)

1. A trench power transistor, comprising:

a substrate;

an epitaxial layer on the substrate, wherein the epitaxial layer has at least one device trench formed therein;

a trench gate structure in the device trench, wherein the trench gate structure comprises:

a shielding electrode located at the lower half part of the element groove;

a gate electrode located at the upper half part of the element groove and electrically insulated with the shielding electrode;

an insulating layer disposed in the device trench and having a profile corresponding to an inner wall surface of the device trench, wherein the gate electrode and the shielding electrode are isolated from each other by the insulating layer, wherein the insulating layer at least includes a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the third dielectric layer is located at a lower half portion of the device trench, and a part of the second dielectric layer located at the lower half portion of the device trench is sandwiched between the first dielectric layer and the third dielectric layer, wherein a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer; and

an inter-electrode dielectric layer between the gate electrode and the shield electrode;

a substrate region formed in the epitaxial layer and surrounding the trench gate structure; and

a source region formed above the body region,

the width of the inter-electrode dielectric layer is the same as that of the shielding electrode, and the first dielectric layer and the second dielectric layer extend from the upper half part of the element groove to the lower half part of the element groove.

2. The trench power transistor of claim 1, wherein the epitaxial layer further comprises at least one termination trench formed in the epitaxial layer, and the trench power transistor further comprises at least one termination electrode structure formed in the termination trench, wherein the termination electrode structure comprises:

a terminal electrode in the terminal trench; and

and a terminal dielectric layer disposed on the inner wall surface of the terminal trench and having a profile corresponding to the inner wall surface of the terminal trench to isolate the terminal electrode from the epitaxial layer, wherein the terminal dielectric layer comprises at least two oxide layers and a nitride layer sandwiched between the oxide layers.

3. The trench power transistor of claim 1 wherein the thickness of the first dielectric layer is between 10nm and 35nm, the thickness of the second dielectric layer is between 20nm and 30nm, and the thickness of the third dielectric layer is between 50nm and 200 nm.

4. The trench power transistor of claim 1, wherein the insulating layer further comprises a fourth dielectric layer formed on the upper half of the device trench, the fourth dielectric layer being sandwiched between the second dielectric layer and the gate electrode.

5. The trench power transistor of claim 4 wherein the thickness of the first dielectric layer is 10nm, the thickness of the second dielectric layer is between 20nm and 30nm, the thickness of the third dielectric layer is between 50nm and 200nm, and the thickness of the fourth dielectric layer is between 10nm and 25 nm.

6. The trench power transistor of claim 1, further comprising:

an interlayer dielectric layer formed on the epitaxial layer, wherein the interlayer dielectric layer has at least one source contact window; and

at least one source conductive plug formed in the source contact window to electrically connect to the source region.

7. The trench power transistor of claim 6 wherein the interlayer dielectric layer comprises a passivation layer directly formed on the surface of the epitaxial layer, wherein the passivation layer is a stack of oxide and nitride layers.

8. A trench power transistor, comprising:

a substrate;

an epitaxial layer located on the substrate, wherein the epitaxial layer is defined to have an active region and a rectifying region, and the epitaxial layer has at least one device trench located in the active region, and a first terminal trench and a second terminal trench located in the rectifying region;

a trench gate structure formed in the device trench, wherein the trench gate structure comprises:

a shielding electrode located at the lower half part of the element groove;

a gate electrode located at the upper half part of the element groove and electrically insulated with the shielding electrode; and

an insulating layer disposed in the device trench, wherein the gate electrode and the shielding electrode are isolated from the epitaxial layer by the insulating layer, the insulating layer at least includes a first dielectric layer, a second dielectric layer and a third dielectric layer, the first dielectric layer and the second dielectric layer extend from the upper half of the device trench to the lower half of the device trench, and the third dielectric layer is located at the lower half of the device trench;

a first substrate region formed in the epitaxial layer, located in the active region and surrounding the trench gate structure;

a source region formed above the first body region;

a first terminal electrode structure formed in the first terminal trench;

a second terminal electrode structure formed in the second terminal trench, wherein the trench gate structure, the first terminal electrode structure and the second terminal electrode structure are adjacent and parallel along a first direction; and

and at least two second substrate regions located in the epitaxial layer between the first terminal electrode structure and the second terminal electrode structure and arranged along a second direction, wherein two adjacent second substrate regions are spaced apart from each other by a predetermined distance to define at least one Schottky contact region.

9. The trench power transistor of claim 8 wherein the device trench is adjacent to the first termination trench and separated by a first pitch, the first termination trench is adjacent to the second termination trench and has a second pitch, wherein the second pitch is smaller than the first pitch, and the difference between the first pitch and the second pitch is between 0.1 μm and 0.3 μm.

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